SRM VALLIAMMAI ENGINEERING COLLEGE

(An Autonomous Institution)

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF MEDICAL ELECTRONICS

QUESTION BANK

III SEMESTER

1910301 ANALOG ELECTRONICS

Regulation – 2019

Academic Year 2021 – 22(Odd)

Prepared by

Ms. Sandhya V.P, Assistant Professor/MDE

 SRM VALLIAMMAI ENGINEERING COLLEGE
(An Autonomous Institution)
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF MEDICAL ELECTRONICS

QUESTION BANK

SUBJECT : 1910301 – ANALOG ELECTRONICS

SEM / YEAR: III / II

UNIT I - BJT AC ANALYSIS

BJT Transistor Modelling, The re transistor model, Common emitter fixed bias, Voltage divider bias, Emitter
follower configuration. Darlington connection- DC bias; The Hybrid equivalent model, Approximate Hybrid
Equivalent Circuit- Fixed bias, Voltage divider, Emitter follower configuration; Complete Hybrid equivalent
model, Hybrid π Model.
PART – A

Q.No Questions BT Level Domain

1. Define biasing and its need. BTL 1 Remembering

2. Name the commonly used model in the small – signal ac analysis BTL 1 Remembering
of transistor networks.
3. Outline the methods used for transistor biasing. Which one is BTL 2 Understanding
popular?
4. Evaluate the importance of Darlington circuit. BTL 5 Evaluating
5. Examine the hybrid model of BJT in CE configuration. BTL 1 Remembering
6. Mention the requirements for biasing circuits. BTL 3 Applying
7. Give the limitations of h-parameters. BTL 2 Understanding
8. Draw the fixed bias single stage transistor circuit. BTL 3 Applying
9. Differentiate small signal equivalent & hybrid π equivalent circuit. BTL 4 Analyzing
10. Distinguish between dc and ac load line with suitable diagram. BTL 2 Understanding
11. Summarize the amplifiers classification according to the input. BTL 2 Understanding
12. Name the elements in the hybrid π model. BTL 1 Remembering
13. Write the techniques used to improve input impedance. BTL 3 Applying
14. Mention the need for bootstrapped Darlington circuit. BTL 4 Analyzing
15. SCreate the hybrid π equivalent model of the BJT. BTL 6 Creating
t
16. aCommon base amplifier is preferred for high frequency signal BTL 5 Evaluating
twhen compared to CE amplifier. Justify.
17. eList out the advantages of h parameter. BTL 1 Remembering
18. Short circuit CE current gain of transistor is 25 at a frequency of 2 BTL 4 Analyzing
MHz if fᵦ = 200 kHz Examine i) hfe ii) find |Ai| at frequency of 10
MHz and 100 MHz.
19. Quote the requirements for biasing circuits. BTL 1 Remembering
20. Assess the stability factor S for a fixed bias circuit. BTL 6 Creating
PART – B
1. Illustrate the working of a voltage divider biasing circuit and (13) BTL 3 Applying
calculate the stability factor for BJT.
2. Design the Common Emitter re model of npn transistor. (13) BTL 6 Creating
3. (i) Distinguish between CE,CB and CC amplifiers. (6) BTL 2 Understanding
(ii) Explain the concept of bootstrapping. (7)
4. Find the equation for the CE short circuit current gain Ai as a (13) BTL 1 Remembering
function of frequency using hybrid - π model.
5. Draw the h-parameter equivalent circuit for a typical common emitter (13) BTL 3 Applying
amplifier and derive expression for Ai, AV, Ri and RO.
6. With suitable diagram, explain about fixed bias Common-Emitter (13) BTL 5 Evaluating
Configuration with un bypassed RE .
7. (i) Summarize the characteristics and features of emitter follower (6) BTL 2 Understanding
circuit.
(ii) Illustrate the working of darlington amplifier with neat sketch. (7)
8. For a BJT with a voltage divider bias circuit, find the change in (13) BTL 1 Remembering
Q-point with the variation in β when the circuit contains an emitter
resistor. Let the biasing resistors be RB1 = 56kΩ, RB2=12.2 kΩ,
RC = 2kΩ, RE = 0.4kΩ, VCC = 10V, VBE(ON) = 0.7V and β =100.
9. Examine the operation of a Voltage Divider biasing in Common- (13) BTL 4 Analyzing
Emitter Configuration.
10. Explain bootstrapped Darlington emitter follower with necessary (13) BTL 4 Analyzing
equations.
11. With neat diagram, explain hybrid π Model of Common Emitter (13) BTL 2 Understanding
configuration.
12. Explain voltage divider bias method for BJT and derive an (13) BTL 1 Remembering
expression for stability factor.
13. (i) Analyze the transconductance, gm for hybrid π Model of (8) BTL 4 Analyzing
Common Emitter configuration.
(ii) Outline the biasing methods for BJT. (5)
14. U
Briefly write the concept of the Common Emitter amplifier using (13) BTL 1 Remembering
approximate
n h-model.
d PART-C
1. e (15) BTL 5 Evaluating
Ther hybrid parameters for a CE amplifier are ℎ𝑖𝑒 =1000 ohms,
ℎ𝑜𝑒s = 25 x 10−6 ohms, ℎ𝑓𝑒=150 𝑎𝑛𝑑 ℎ𝑟𝑒=1.2 x 10−4. The transistor
hast a load resistance of 10 kΩ in collector and supplied from
a
signal source of resistance 5 kΩ.Calculate the values of input
n
impedance, output impedance, current gain and voltage gain.
2. d (15) BTL 5 Evaluating
Evaluate
i the Ai, Av, Ri, Ro, Ais, Avs of a single stage Common
Emitter
n amplifier with Rs = 500 Ω, RL = 2000Ω, hfe = 50,
hieg =1kΩ, hoe = 25µ A/V and hre = 2x10-4.
3. A given transistor with Ic =10𝑚A (Collector current), VCE =10 V (15) BTL 6 Creating
(Collector-Emitter voltage) and at room temperature has the
following set of low frequency parameters: ℎ𝑖𝑒=500Ω,
ℎ𝑜𝑒=10−5𝐴/𝑉, ℎ𝑓𝑒=100 𝑎𝑛𝑑 ℎ𝑟𝑒=10−4. Design the values of all
hybrid -π parameters of a low frequency model and draw the
equivalent low frequency hybrid -π model.
 4. Design a voltage divider bias circuit for bipolar junction transistor (15) BTL 6 Creating
to establish the quiescent point at Collector Emitter voltage,VCE
=12V,Collector current,IC =1.5mA,Stability factor S≤ 3,β
=50,VBE=0.7V,VCC = 22.5V and RC=5.6 kΩ.
UNIT II - FIELD EFFECT TRANSISTORS
Construction and Characteristics of JFETs, Transfer Characteristics, Depletion type MOSFET, Enhancement type
MOSFET. FET Amplifiers: JFET small signal model, Fixed bias configuration, Self bias configuration, Voltage
divider configuration, Common Gate configuration. Source- Follower Configuration, Cascade configuration.
PART – A
Q.No Questions BT Level Domain

1. List the advantages of common drain amplifier. BTL 1 Remembering

2. Analyze the output impedance for the MOSFET amplifier given: BTL 4 Analyzing
Kn = 1mA/V, VTN = 1.2V, Av = 0.855 ,λ = 0.01V −1, and
IDQ = 1mA.
3. How a MOSFET can be used to amplify a time varying voltage? BTL 1 Remembering
4. Differentiate the three FET configurations (CS, CD and CG). BTL 4 Analyzing
5. Comparison between JFET and MOSFET. BTL 1 Remembering
6. The parameters for the transistor below are Kn = 0.5 mA/V2, VTN BTL 4 Analyzing
= 1.2V, and λ = 0. Simplify VDS and VGS for IQ=50 µA.
7. Measure the value of ideal voltage gain for a certain JFET which BTL 5 Evaluating
has a gm of 4 mS. with an external drain resistance of 1.5kΩ.
8. Evaluate the value of Transconductance. When VGS of a FET BTL 5 Evaluating
changes from -3.1V to -3V, the drain current changes from 1 mA
to 1.3 mA.
9. Identify the impact of including a source resistor in the FET BTL 1 Remembering
amplifier.
10. Design the hybrid small signal model of Common Gate BTL 6 Creating
configuration.
11. If the midband gain of an amplifier is 100 and half power BTL 3 Applying
frequencies are fL =40Hz and fH=16kHz. Calculate the amplifier
gain at 20Hz and 20kHz frequency.
12. Construct a basic circuit for an operation of enhancement type BTL 6 Creating
MOSFET.
13. Mention the methods used for biasing circuits in FET. BTL 2 Understanding
14. List the characteristics of JFET. BTL 2 Understanding
15. Express the drain current equation of JFET. BTL 2 Understanding
16. Draw the block diagram of two stage cascaded amplifier. BTL 3 Applying
17. Construct a small signal model of JFET. BTL 3 Applying
18. Cite three basic configuration of FET. BTL 1 Remembering
19. Why transformer coupling is not used in the initial stages of a BTL 1 Remembering
multistage amplifier?
20. Two amplifiers having gain of 20 dB and 40 dB are cascaded. BTL 2 Understanding
Infer the overall gain in dB.
PART – B
1. Illustrate the construction and operation of MOSFET with neat (13) BTL 3 Applying
diagram.
2. Describe the construction and working of BTL 2 Understanding
(i) n-channel JFET. (7)
(ii) p-channel JFET. (6)
3. (i) How to compute the small signal parameters for a MOSFET. (7) BTL 4 Analyzing
(ii) Analyze and configure a common-source amplifier with (6)
source resistor.
4. Describe the biasing methods of MOSFET. (13) BTL 2 Understanding
5. Deduce the derivation for the Zi, Av, Ai and Zo for FET amplifier (13) BTL 5 Evaluating
with voltage divider bias using hybrid model.
6. With neat sketch explain two stage cascaded amplifier and (13) BTL 4 Analyzing
analyze its overall Av, At, Rt and Ro.
7. (i) Interpret how JFET can be used as an amplifier (6) BTL 3 Applying
(ii) Examine the drain and transfer characteristics of JFET. (7)
8. Outline the need for cascading and explain the block diagram of (13) BTL 1 Remembering
two stage cascaded amplifier.
9. Sketch the diagram of a Common drain amplifier and derive the (13) BTL 1 Remembering
expression for the voltage gain.
10. Explain
(i) Listthethe
expression
biasing for commonofgate
methods circuit of JFET
MOSFET and derive an (6) BTL 1 Remembering
expression for stability factor.
(ii) Explain the expression for common gate circuit of JFET. (7)
11. Design a small signal low frequency model for JFET and derive (13) BTL 6 Creating
an expression for Zi, Av, Ai and Zo.
12. Analyze a simple JFET source-follower amplifier circuit and (13) BTL 4 Analyzing
discuss the general AC circuit characteristics.
13. Draw the small-signal high-frequency circuit of a common source (13) BTL 1 Remembering
amplifier and derive the expression for voltage gain.
14. With the help of a neat diagram explain the operation of an n- (13) BTL 2 Understanding
channel enhancement type MOSFET.
PART – C
1. Design the circuit shown below with transistor parameters (15) BTL 6 Creating
IDSS = 12mA, Vp = -4V and λ = 0.008V-1. Determine the small
signal voltage gain Av=Vo/Vi.
 2. The amplifier shown in Fig. an n-channel FET for which, (15) BTL 5 Evaluating
ID=0.8mA, VP = -2V, Vdd = 24V and IDSS=1.6mA. Assume that
rd>Rd. Evalulate the parameters VGS, gm, Rs.

3. With a neat diagram, assess the source and drain resistance (15) BTL 5 Evaluating
biasing of MOSFET.
4. Formulate the stability factors for any two biasing methods in (15) BTL 6 Creating
detail.
UNIT III - BJT AND JFET FREQUENCY RESPONSE
Logarithms, Decibels, Low frequency response – BJT Amplifier with RL, Low frequency response-FET Amplifier,
Miller effect capacitance, High frequency response – BJT Amplifier, High frequency response-FET Amplifier,
Multistage Frequency Effects.
PART – A
Q.No Questions BT Level Domain

1. What is the effect of miller’s capacitance on the frequency BTL 1 Remembering

response of an amplifier?
2. Define rise time. Give the relationship between bandwidth and rise BTL 1 Remembering
time.
3. For an amplifier, midband gain = 100 and lower cutoff frequency BTL 3 Applying
is 1 kHz. Find the gain of an amplifier at frequency 20 Hz.
4. Assess the transistor switching times. BTL 5 Evaluating
5. Develop the high frequency equivalent model for MOSFET. BTL 6 Creating
6. Quote the reason for reduction in gain for lower and higher BTL 1 Remembering
frequencies in case of amplifiers.
7. If the rise time of a BJT is 35 nano seconds. Identify the BTL 1 Remembering
bandwidth that can be obtained using this BJT.
8. Analyze the expressions for gain bandwidth product for voltage BTL 4 Analyzing
and current.
9. Draw the general frequency response curve of an amplifier. BTL 3 Applying
10. Determine the effect of coupling capacitors on the bandwidth of BTL 3 Applying
the amplifier.
11. Infer the effects of emitter bypass capacitor on high frequency BTL 4 Analyzing
response.
12. Summarize the need of cascading multistage amplifiers. BTL 1 Remembering
13. Differentiate small signal equivalent & hybrid π equivalent circuit. BTL 2 Understanding
14. Express the equation of overall lower and upper cutoff frequency BTL 2 Understanding
of multistage amplifier.
15. Calculate the amplification factor µ of Field Effect Transistor, if BTL 5 Evaluating
rd = 4 kΩ and gm = 4 mA/V.
16. Compare BJT and MOSFET Amplifiers. BTL 4 Analyzing
17. List out the advantages of h parameter. BTL 1 Remembering
18. Identify and mention the limitations of multistage amplifiers. BTL 2 Understanding
19. Design the high frequency model of FET. BTL 6 Creating
20. Give the main reason for the drop in gain at the low frequency BTL 2 Understanding
region & high frequency region.
PART - B

1. (i) Tabulate the effect of capacitors on frequency response. (6) BTL 1 Remembering
(ii) Describe with neat diagram and derive the expression for cut
off frequency of a BJT. (7)
2. (i) With neat diagram, explain the frequency response of BJT (6) BTL 4 Analyzing
amplifier.
(ii) What are the significance of cut off frequencies and (7)
Bandwidth of the amplifier.
3. How would you describe the relation between rise time, upper cut (13) BTL 1 Remembering
off frequency and bandwidth.
4. Develop the high frequency equivalent circuit of a MOSFET (13) BTL 6 Creating
from its geometry and derive the expression for short circuit
current gain in the common source configuration.
5. (i) Draw the Hybrid π equivalent circuit of a BJT. (3) BTL 3 Applying
(ii)Using hybrid model, draw the high frequency equivalent (10)
circuit of CE amplifier and derive for higher cut-off frequencies.
6. Elaborate the effect of coupling and bypass capacitors.in the low (13) BTL 2 Understanding
frequency response of BJT amplifier.
7. Explain the upper and lower cut off frequencies of multistage (13) BTL 1 Remembering
amplifier with expressions.
8. Assess the operation of high frequency common source FET (13) BTL 5 Evaluating
amplifier with neat diagram. Derive the expression for (i) voltage
gain (ii) input admittance (iii) input capacitance (iv) output
admittance.
9. (i)Derive the expression for frequency response of multistage (8) BTL 1 Remembering
amplifier.
(ii) List the significance of cut off frequencies and Gain (5)
bandwidth product of amplifier.
10. Describe the high frequency equivalent circuit of FET and hence (13) BTL 2 Understanding
derive gain bandwidth product for any one configuration.

11. Outline the low frequency analysis of amplifier to obtain lower (13) BTL 4 Analyzing
cut-off frequency.
12. Explain the function of transistor and derive the expression for (13) BTL 4 Analyzing
input conductance (gbe) and output resistance (gce) for hybrid – π
common emitter transistor model.
13. Summarize the expressions for the short circuit current gain of (13) BTL 2 Understanding
common emitter amplifier at a high frequency. Define alpha cut-
off frequency, beta cut-off frequency and transition frequency and
derive their values in terms of the circuit parameters.
14. Illustrate the Common Drain Amplifier Circuit and determine the (13) BTL 3 Applying
Small signal equivalent circuit at high frequencies.
PART – C
 1. (i)Design the high frequency analysis of JFET with necessary (8) BTL 6 Creating
circuit diagram& gain bandwidth product.
(ii)Explain the frequency response of MOSFET CS amplifier. (7)
2. Obtain the low frequency response and high frequency response of (15) BTL 5 Evaluating
an amplifier, derive its cutoff frequency & discuss the terms rise
time and sag.
3. Determine the midband gain Am and upper 3dB frequency fH of a (15) BTL 5 Evaluating
CS amplifier fed with a signal source having an internal resistance
Rsig=100kΩ.The amplifier has RG=4.7MΩ, RD=RL=15kΩ,
gm=1mA/V, ro=150kΩ, cgs=1pF and cgd = 0.4pF.
4. Develop the high frequency equivalent circuit of a FET amplifier (15) BTL 6 Creating
and derive the expression for output admittance for common drain
configuration.
UNIT IV- FEEDBACK AND OSCILLATOR CIRCUITS
Feedback concepts, Feedback connection types, Practical feedback circuits, Oscillator operation, FET Phase shift
oscillator, Wien bridge oscillator, Tuned Oscillator circuit, Crystal oscillator, UJT construction, UJT Oscillator.

PART - A
Q.No Questions BT Level Domain

1. The overall gain of a multistage amplifier is 140.When negative BTL 1 Remembering

voltage feedback is applied the gain is reduced to 17.5.Find the
fraction of the output that is feedback to the input.
2. Assess the two Barkhausen conditions required for sinusoidal BTL 5 Evaluating
oscillation to be sustained.
3. Define intrinsic stand-off ratio in UJT? BTL 1 Remembering
4. List the disadvantages of negative feedback in amplifiers and BTL 1 Remembering
how it can be overcome?
5. Show the expression for the frequency of oscillations of a in BTL 3 Applying
phase shift oscillator.
6. An amplifier has a current gain of 240 and input impedence of BTL 5 Evaluating
15kΩ without feedback. If negative current feedback (current
attenuation = 0.015) is applied, What will be the input
impedence of the amplifier?
7. What is the advantage of a Colpitts oscillator compared to a BTL 4 Analyzing
phase shift oscillator?
8. Which is the most commonly used feedback arrangement in BTL 1 Remembering
cascaded amplifier and why?
9. Name the type of feedback circuit that increases gain of an BTL 1 Remembering
amplifier.
10. Outline the advantages of crystal oscillator. BTL 2 Understanding
11. Discuss about Nyquist’s stability criteria for feedback BTL 2 Understanding
amplifiers.
12. Develop the oscillator model which uses both positive and BTL 6 Creating
negative feedback.
13. Determine the operating frequency of transistor Hartley BTL 3 Applying
oscillator if L1 = 50μH, L2 = 1mH, and mutual inductance
between the coils M = 10 μH and C = 10pF.
14. Categorize the characteristics of an amplifier which are BTL 4 Analyzing
modified by negative feedback.
15. List out the advantages of phase shift oscillator. BTL 1 Remembering
16. Analyzing the effects on bandwidth and output impedance due BTL 4 Analyzing
to feedback.
17. Illustrate the expression for frequency of oscillation of a Wein- BTL 3 Applying
bridge oscillator.
18. Distinguish between negative and positive feedback. BTL 2 Understanding
19. Give the limitations of LC and RC oscillators. BTL 2 Understanding
20. Design a wein bridge oscillator with an operating frequency at BTL 6 Creating
f0 =10 kHz. If the value of R is 100Ω, obtain the value of the
capacitor in the feedback network.
PART - B
1. With neat block diagram, explain the operation of following BTL 4 Analyzing
feedback amplifiers. (7)
(i) Voltage series feedback amplifier. (6)
(ii) Current shunt feedback amplifier.
2. (i) Explain with neat circuit diagram, the working of Hartley (6) BTL 1 Remembering
oscillator using transistor.
(ii)Derive an expression for frequency of oscillation. (7)
3. (i) Describe the operation of Wien – Bridge oscillator with (6) BTL 1 Remembering
suitable diagram. (7)
(ii)Derive an expression for frequency of oscillation.
4. Explain the basic construction and equivalent circuit of a UJT (13) BTL 3 Applying
and briefly explain the device operation.
5. Illustrate the operation of UJT as a relaxation oscillator and (13) BTL 3 Applying
express its frequency of oscillation.
6. (i) With neat circuit diagram, discuss the operation of Colpitts (6) BTL 2 Understanding
Oscillator with neat circuit diagram.
(ii) Derive the expressions for the frequency of oscillation and (7)
the condition for maintenance of oscillation.
7. Describe the construction and working of crystal oscillator with (13) BTL 2 Understanding
neat diagram.
8. Assess the working principle of Hartley oscillator with neat BTL 5 Evaluating
diagram.
9. Design a Colpitts oscillator with capacitance C1 = 100 pF and (13) BTL 6 Creating
C2 = 7500 pF.The inductance is variable. Determine the range
of inductance values, if the frequency of oscillation is to vary
between 950 kHz and 2050 kHz.
10. Sketch a circuit diagram of a two stage capacitor coupled BJT (13) BTL 4 Analyzing
amplifier that uses series voltage negative feedback. Explain
how the feedback operates.
11. Examine the working of a phase shift oscillator. Discuss its (13) BTL 1 Remembering
advantages and disadvantages.
 12. Analyze the operation of current series feedback amplifier and BTL 4 Analyzing
derive its expression for
(4)
(i)Input resistance.
(4)
(ii)Output resistance.
(3)
(iii)Voltage gain.
(2)
(iv)Feedback ratio.
13. (i) Enumerate the basic concept of feedback. (6) BTL 1 Remembering
(ii) List the different types of feedback. Explain about the (7)
positive feedback.
14. (i) Mention the condition for oscillation of an oscillator. (5) BTL 2 Understanding
(ii) Summarize the advantages of negative current feedback on (8)
the performance of amplifiers.
PART – C
1. Determine the frequency of oscillations hen a RC phase shift (15) BTL 6 Creating
oscillator has R=12 𝑘𝛺,C=0.01 μF and RC=3.3 𝑘𝛺.Also find the
minimum current gain needed for this purpose.
2. (i)When negative voltage feedback is applied to an amplifier of (5) BTL 6 Creating
gain 100,the overall gain falls to 50.Find the fraction of the
output voltage feedback. If this fraction is maintained , find
the value of the amplifier gain required if the overall stage
gain is to be 75.
(ii)Calculate the amplifier gain, when negative (10)
feedback ratio is 0.01. An amplifier has voltage gain of 400,
=50Hz, = 200kHz and distortion of 10% without
feedback.
3. (i)In a Colpitts oscillator,C1=C2=C and L=100 x 10-6H. The (8) BTL 5 Evaluating
frequency of oscillation is 500 KHz. Determine the value of
the capacitance C. (7)
(ii)In Colpitts oscillator, the desired frequency is 500 kHz. Find
the value of L. Assume C=1000 pF.
4. An amplifier has a mid frequency gain of 100 and a bandwidth BTL 5 Evaluating
of 200 kHz.
(i)Compute the new bandwidth and gain if 5% negative (8)
feedback is introduced.
(ii)Evaluate the amount of feedback, if the bandwidth is (7)
restricted to 1 MHz.
UNIT V - POWER AMPLIFIERS
Definition and amplifier types, Series fed class A amplifier, Transformer coupled class A amplifier, Class B
amplifier operation and circuits, Amplifier distortion, Class C and Class D amplifiers. Voltage Regulators: Discrete
transistor voltage regulation - Series and Shunt Voltage regulators.
PART –A

Q.No Questions BT Level Domain

1. Define conversion efficiency of a power amplifier. BTL 1 Remembering

2. Summarize the temperature effects in power amplifier. BTL 2 Understanding
3. A transformer-coupled class A power amplifier supplies power BTL 3 Applying
to an 80Ωload connected across the secondary of a step-down
transformer having a turn ratio 5:1. Calculate the maximum
power output for a zero signal collector of 120mA.
4. What is meant by second order harmonic distortion? BTL 1 Remembering
5. Mention two conditions to be satisfied by a complementary BTL 3 Applying
symmetry power stage.
6. List out the classifications of Power amplifiers. BTL 1 Remembering
7. Express the power relations of Class B amplifier. BTL 2 Understanding
8. Name the types of voltage regulators. BTL 1 Remembering
9. Identify the typical characteristics for the transformer-coupled BTL 1 Remembering
circuit.
10. Why class A amplifier must not be operated under no signal BTL 4 Analyzing
conditions?
11. Construct the circuit diagram of a Push Pull amplifier. BTL 6 Creating
12. Outline the advantages of the transformer coupled class A BTL 2 Understanding
power amplifier?
13. Differentiate between Voltage and Power amplifier. BTL 4 Analyzing
14. Interpret the efficiency of Class C amplifier. BTL 2 Understanding
15. Assess the configuration used in complementary symmetry BTL 5 Evaluating
power amplifier. How does it help?
16. Draw the output characteristics of class A amplifier. BTL 3 Applying
17. State the advantages of transformer-coupled class A amplifier BTL 1 Remembering
over the RC-coupled circuit.
18. Compare the efficiencies of all the power amplifiers. BTL 4 Analyzing
19. Compose the characteristics of Class B amplifier. BTL 6 Creating
20. Write the applications of Class C amplifier. BTL 5 Evaluating
PART –B
1. (i) Explain the working of Transformer coupled Class-A (8) BTL 1 Remembering
power amplifier with the help of a neat circuit diagram.
(ii)Give the expression for dc power input, ac power output (5)
and efficiency?
2. Write about the Class B transformer coupled power (13) BTL 1 Remembering
amplifier with necessary derivations.
3. Examine the circuit operation and output resistance of Class (13) BTL 1 Remembering
AB power amplifiers.
4. Summarize the transfer characteristic, signal waveforms, (13) BTL 2 Understanding
power dissipation, and power conversion efficiency of Class A
amplifier.
5. (i) Explain in detail about the Class C power amplifier. (6) BTL 2 Understanding
(ii) Distinguish between series and shunt voltage regulators. (7)
6. (i) Illustrate the operation of class-AB power amplifier with a (6) BTL 2 Understanding
neat sketch.
(ii) Describe Class AB power amplifier using MOSFETs. (7)
7. Enumerate the working of Series fed, directly coupled Class-A (13) BTL 1 Remembering
power amplifier with the help of a neat circuit diagram. Give
the expression for dc power input, ac power output and
efficiency?
8. Analyze the circuit diagram of class B push pull amplifier and (13) BTL 4 Analyzing
explain its operation. Also prove that its conversion efficiency is
78.5%.
9. (i)Sketch the transformer coupled class A amplifier and (10) BTL 3 Applying
compute its maximum efficiency is 50%.
(ii)Compare the push-pull class B and complementary (3)
symmetry class B amplifier.
10. (13)
(i) Construct the circuit diagram of push-pull amplifier and (10) BTL 3 Applying
explain why even harmonics are not present in a push- pull
amplifier.
(ii)Mention two additional advantages of this circuit over that of (3)
a single transistor amplifier.
11. Outline the power amplifier classes with respect to its operating (13) BTL 4 Analyzing
cycle, position of Q-point and efficiency.
12. (i) Differentiate power MOSFET with BJTs. (6) BTL 4 Analyzing
(ii) Evaluate the temperature effects of Power MOSFET. (7)
13. (i)Construct the class AB power amplifier using MOSFET. (6) BTL 5 Evaluating
(ii)Design the structure of Power MOSFETs and explain its (7)
characteristics.
14. Explain the working of Class-B power amplifier with the help (13) BTL 6 Creating
of a neat circuit diagram.
PART –C
1. A class B push pull amplifier supplies power to a resistive load BTL 5 Evaluating
of 12 Ohms. The output transformer has a turn of 3:1 and
efficiency of 78.5%.
(i) Maximum power output. (5) (5)
(ii) Maximum power dissipation in each transistor. (5) (5)
(iii) Maximum base and collector current for each (5)
transistor Assume hfe=25 and Vcc=20V.
2. For the Class-B complementary A.F power amplifier, calculate (15) BTL 6 Creating
maximum AC power which can be developed, collector
dissipation while developing maximum AC power, efficiency,
maximum power dissipation per transistor, efficiency under
maximum power dissipation condition.
3. For the circuit shown ,find (15) BTL 5 Evaluating
(i) the output voltage (5)

(ii) the voltage drop across series resistance (5)

(iii) the current through zener diode. (5)

4. Design the circuit diagram of a linear voltage regulator and (15) BTL 6 Creating
explain about its types.