Scribd
Upload
19 views2 pages

DLC Sat QP

Uploaded by

Soorya Priya Gopala Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
19 views2 pages

DLC Sat QP

Uploaded by

Soorya Priya Gopala Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

LOYOLA INSTITUTE OF TECHNOLOGY

Palanchur, Chennai – 123


Marks: 100
DEPARTMENT OF EEE Time: 3 Hrs
MODEL EXAM Date : .11.21
EE8351 / DIGITAL LOGIC CIRCUITS Session:
3rd SEM / II YEAR

Answer ALL questions

PART-A ANSWER ALL QUESTIONS (50 x2 = 100)


No Question
1. Give the characteristic table and characteristic equation of T flipflop
2. State the differences between Mealy and Moore state machines.
3. What is a flow table? Give example.
4. Draw the state diagram of JK flipflop.
5. What is static hazard and dynamic hazard.
6. Define races in an asynchronous sequential circuit.
7. Draw the truth table and state diagram of SR flipflop.
8. What is edge triggered flip flops?
9. Compare pulse mode and fundamental mode asynchronous circuit
10. Define Hazard.
11. With reference to a JK flip flop, what is racing?
12. How many states are there in a 3-bit ring counter? What are they?
13. Draw the diagram of T flip flop and discuss its working.
14. What is a shift register?
15. Define race around condition.
16. Define flip-flop
17. What is the minimum number of flip flops needed to build a counter of modulus 8?
18. Write any two applications of shift register.
19. What is the significance of state assignment?
20. What is lockout? How it is avoided?
21. Which gates are called as the universal gates? What are its advantages?
22. Write the maxterms corresponding to the logical expression
Y = (A + B + C’ )(A + B’ +C’)(A’ + B’ + C)
23. Define FPGA.
24. State the differences between PROM, PAL and PLA.
25. What are called don’t care conditions?
26. Define propagation Delay.
27. Compare Combinational and Sequential circuit
28. List out the applications of multiplexer
29. What is priority encoder?
30. Give the syntax for package declaration and package body in VHDL.
31. Write the VHDL code for 2 to 1 Multiplexer using behavioural modelling.
32. What is data flow modelling in VHDL? Give its basic mechanism.
33. Write VHDL behavioural model for D flip flop.
34. Write the VHDL code for a logic gate which gives high output only when both the input are
high.
35. What is a package in VHDL?
36. List out the operators present in VHDL.
37. What is VHDL?
38. Write structural code for D-latch.
39. Write VHDL code for 3:8 Decoder.
40. State the associative property of Boolean algebra.
41. Reduce A(A+B)
42. Reduce a(b+bc’)+ab’
43. Convert 14310 into its binary and binary coded decimal equivalent.
44. What are the two steps in Gray to binary conversion?
45. What is meant by self-complementing code?
46. What is meant by parity bit?
47. Convert 7368 into an equivalent binary number.
48. What are the different classification of binary codes?
49. Define Duality property.
50. What is a Karnaugh map?

You might also like