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Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN

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 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

19-3955; Rev 4; 4/12

KIT
ATION
EVALU BL E
AVAILA
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
General Description Features

MAX9247
The MAX9247 digital video parallel-to-serial converter o Preemphasis Improves Eye Diagram and Signal
serializes 27 bits of parallel data into a serial-data stream. Integrity at the Output
Eighteen bits of video data and 9 bits of control data are o Proprietary Data Encoding for DC Balance and
encoded and multiplexed onto the serial interface, reduc- Reduced EMI
ing the serial-data rate. The data-enable input determines o Control Data Sent During Video Blanking
when the video or control data is serialized. o Five Control Data Inputs are Single-Bit-Error
The MAX9247 pairs with the MAX9248/MAX9250 dese- Tolerant
rializers to form a complete digital video serial link. o Programmable Phase-Shifted LVDS Signaling
Interconnect can be controlled-impedance PCB traces or Reduces EMI
twisted-pair cable. Proprietary data encoding reduces o Output Common-Mode Filter Reduces EMI
EMI and provides DC balance. DC balance allows AC- o Greater Than 10m STP Cable Drive
coupling, providing isolation between the transmitting o Wide ±2% Reference Clock Tolerance
and receiving ends of the interface. The LVDS output is o ISO 10605 and IEC 61000-4-2 Level 4
internally terminated with 100Ω. For operating frequen- ESD Protection
cies less than 35MHz, the MAX9247 can also pair with o Separate Input Supply Allows Interface to 1.8V
the MAX9218 deserializer. to 3.3V Logic
ESD tolerance is specified for ISO 10605 with ±10kV o +3.3V Core Supply
Contact Discharge and ±30kV Air-Gap Discharge. o Space-Saving LQFP Package
The MAX9247 operates from a +3.3V core supply and o -40°C to +85°C and -40°C to +105°C Operating
features a separate input supply for interfacing to 1.8V Temperature Ranges
to 3.3V logic levels. This device is available in a 48-lead
LQFP package and is specified from -40°C to +85°C or Ordering Information
-40°C to +105°C.
PART TEMP RANGE PIN-PACKAGE
Applications
MAX9247ECM+ -40°C to +85°C 48 LQFP
Navigation System Displays
MAX9247ECM/V+ -40°C to +85°C 48 LQFP
In-Vehicle Entertainment Systems
MAX9247GCM+ -40°C to +105°C 48 LQFP
Video Cameras MAX9247GCM/V+ -40°C to +105°C 48 LQFP
LCDs +Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.

Pin Configuration
RGB_IN9
RGB_IN8
RGB_IN7
RGB_IN6
RGB_IN5
RGB_IN4
RGB_IN3
RGB_IN2
RGB_IN1
RGB_IN0

GND

TOP VIEW
VCC
48
47
46
45
44
43
42
41
40
39
38
37

+
GND 1 36 RNG0
VCCIN 2 35 RNG1
RGB_IN10 3 34 VCCLVDS
RGB_IN11 4 33 OUT+
RGB_IN12 5 32 OUT-
RGB_IN13 6 31 LVDSGND
RGB_IN14 7 MAX9247 30 LVDSGND
RGB_IN15 8 29 CMF
RGB_IN16 9 28 PWRDWN
RGB_IN17 10 27 VCCPLL
CNTL_IN0 11 26 PLLGND
CNTL_IN1 12 25 PRE
13
14
15
16
17
18
19
20
21
22
23
24
GND
VCC
CNTL_IN2
CNTL_IN3
CNTL_IN4
CNTL_IN5
CNTL_IN6
CNTL_IN7
CNTL_IN8
DE_IN
PCLK_IN
I.C.

LQFP

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
ABSOLUTE MAXIMUM RATINGS
MAX9247

VCC_ to _GND........................................................-0.5V to +4.0V All Pins to GND ..............................................................±200V

Any Ground to Any Ground...................................-0.5V to +0.5V Human Body Model (RD = 1.5kΩ, CS = 100pF)
OUT+, OUT-, CMF to LVDSGND...........................-0.5V to +4.0V All Pins to GND ................................................................±3kV
OUT+, OUT- Short Circuit to LVDSGND ISO 10605 (RD = 2kΩ, CS = 330pF)
or VCCLVDS .............................................................Continuous Contact Discharge (OUT+, OUT-) to LVDSGND ...........±10kV
OUT+, OUT- Short Through 0.125µF (or smaller), Air-Gap Discharge (OUT+, OUT-) to LVDSGND ...........±30kV
25V Series Capacitor..........................................-0.5V to +16V IEC 61000-4-2 (RD = 330Ω, CS = 150pF)
RGB_IN[17:0], CNTL_IN[8:0], DE_IN, Contact Discharge (OUT+, OUT-) to LVDSGND ...........±10kV
RNG0, RNG1, PRE, PCLK_IN, Air-Gap Discharge (OUT+, OUT-) to LVDSGND ...........±15kV
PWRDWN to GND ...............................-0.5V to (VCCIN + 0.5V) Storage Temperature Range .............................-65°C to +150°C
Continuous Power Dissipation (TA = +70°C) Junction Temperature ......................................................+150°C
48-Lead LQFP (derate 20.8mW/°C above +70°C)....1666.7mW Lead Temperature (soldering, 10s)..................................+300°C
ESD Protection Soldering Temperature (reflow) .......................................+260°C
Machine Model (RD = 0Ω, CS = 200pF)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, PRE = low, TA = -40°C to +105°C, unless otherwise noted. Typical
values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, PRE)
VCCIN = 1.71V to < 3V (Note 3) 0.65 x VCCIN VCCIN + 0.3
High-Level Input Voltage VIH V
VCCIN = 3.0V to 3.6V 2 0.3 + VCCIN
VCCIN = 1.71V to < 3V (Note 3) -0.3 0.3 x VCCIN
Low-Level Input Voltage VIL V
VCCIN = 3.0V to 3.6V -0.3 +0.8
VIN = -0.3V to 0V
VCCIN = 1.71V (MAX9247ECM),
to 3.6V, -100 +20
Input Current IIN VIN = -0.15V to 0V µA
PWRDWN = (MAX9247GCM)
high or low
VIN = 0V to (VCCIN + 0.3V) -20 +20
Input Clamp Voltage VCL ICL = -18mA -1.5 V
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage VOD Figure 1 250 335 450 mV
Change in VOD Between
∆VOD Figure 1 20 mV
Complementary Output States
Common-Mode Voltage VOS Figure 1 1.125 1.29 1.475 V
Change in VOS Between
∆VOS Figure 1 20 mV
Complementary Output States
Output Short-Circuit Current IOS VOUT+ or VOUT- = 0V or 3.6V -15 ±8 +15 mA
Magnitude of Differential
IOSD VOD = 0V 5.5 15 mA
Output Short-Circuit Current
VOUT+ = 0V,
Output High-Impedance PWRDWN = low VOUT- = 3.6V
IOZ -1 +1 µA
Current or VCC_ = 0V VOUT+ = 3.6V,
VOUT- = 0V

2 _______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
DC ELECTRICAL CHARACTERISTICS (continued)

MAX9247
(VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, PRE = low, TA = -40°C to +105°C, unless otherwise noted. Typical
values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Differential Output Resistance RO 78 110 147 Ω
PRE = 0 15 25
2.5MHz
PRE = 1 27
PRE = 0 18 25
5MHz
PRE = 1 27

RL = 100Ω ±1%, PRE = 0 23 28

10MHz
Worst-Case Supply Current CL = 5pF, PRE = 1 30
ICCW mA
continuous 10 PRE = 0 33 39
transition words 20MHz
PRE = 1 42
PRE = 0 50 65
35MHz
PRE = 1 69
PRE = 0 60 70
42MHz
PRE = 1 75
Power-Down Supply Current ICCZ (Note 4) 50 µA

AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40°C to +105°C, unless otherwise noted.
Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PCLK_IN TIMING REQUIREMENTS
MAX9247ECM 23.8 400.0
Clock Period tT Figure 2 ns
MAX9247GCM 28.6 400.0
MAX9247ECM 2.5 42.0
Clock Frequency fCLK MHz
MAX9247GCM 2.5 35.0
Clock Frequency Difference from
∆fCLK -2 +2 %
Deserializer Reference Clock
Clock Duty Cycle DC tHIGH/tT or tLOW/tT, Figure 2 35 50 65 %
Clock Transition Time tR, tF Figure 2 2.5 ns
SWITCHING CHARACTERISTICS
20% to 80%, PRE = low 280 370
Output Rise Time tRISE ps
VOD ≥ 250mV, Figure 3 PRE = high 240 320
80% to 20%, PRE = low 280 370
Output Fall Time tFALL ps
VOD ≥ 250mV, Figure 3 PRE = high 240 320
Input Setup Time tSET Figure 4 3 ns
Input Hold Time tHOLD Figure 4 3 ns

_______________________________________________________________________________________ 3
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Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
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27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
AC ELECTRICAL CHARACTERISTICS (continued)
MAX9247

(VCC_ = +3.0V to +3.6V, RL = 100Ω±1%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40°C to +105°C, unless otherwise noted.
Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

3.10 x 3.10 x
Serializer Delay tSD Figure 5 ns
tT + 2.0 tT + 8.0
17,100 x
PLL Lock Time tLOCK Figure 6 ns
tT
Power-Down Delay tPD Figure 7 1 µs
Measured with PRBS input pattern at
Peak-to-Peak Output Jitter tJITT 150 ps
840Mbps data rate
840Mbps data rate,
22 70
Peak-to-Peak Output Offset CMF open, Figure 8
VOS(P-P) mV
Voltage 840Mbps data rate,
12 50
CMF 0.1µF to ground, Figure 8
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except VOD, ∆VOD, and ∆VOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCCIN - 0.3V. PWRDWN is ≤ 0.3V.

4 _______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Typical Operating Characteristics

MAX9247
(VCC_ = +3.3V, RL = 100Ω, TA = +25°C, unless otherwise noted.)

WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY EYE DIAGRAM WITHOUT PREEMPHASIS EYE DIAGRAM WITH PREEMPHASIS
70

MAX9247 toc03
MAX9247 toc02
MAX9247 toc01

PRE = LOW 2 METER CAT5 CABLE PRE = HIGH 2 METER CAT5 CABLE
60 fREFCLK = 42MHz 100Ω TERMINATION fREFCLK = 42MHz 100Ω TERMINATION
SUPPLY CURRENT (mA)

50 WITH PREEMPHASIS GND

40
100mV/div 100mV/div
30
GND
WITHOUT PREEMPHASIS
20

10

0
0 10 20 30 40 200ps/div 200ps/div
FREQUENCY (MHz)

CABLE LENGTH
BIT-ERROR RATE vs. CABLE LENGTH vs. FREQUENCY BIT-ERROR RATE < 10-9
1.00E-14 45
MAX9247 toc04

MAX9247 toc05
CAT5 CABLE
40

1.00E-13 35
FREQUENCY (MHz)
BIT-ERROR RATE

30

1.00E-12 25

20
fREFCLK = 42MHz
1.00E-11 15
840Mbps DATA RATE
FOR CABLE LENGTH < 10m
10
BER < 10-12
1.00E-10 5
0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20
CAT5 CABLE LENGTH (m) CABLE LENGTH (m)

_______________________________________________________________________________________ 5
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Pin Description
MAX9247

PIN NAME FUNCTION

1, 13, 37 GND Input Buffer Supply and Digital Supply Ground
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
2 VCCIN
close to the device as possible, with the smallest value capacitor closest to the supply pin.
RGB_IN10–
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
3–10, RGB_IN17,
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
39–48 RGB_IN0–
GND.
RGB_IN9
CNTL_IN0,
CNTL_IN1, LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
11, 12, 15–21 CNTL_IN2– when DE_IN is low. Internally pulled down to GND.
CNTL_IN8
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
14, 38 VCC
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
22 DE_IN selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
23 PCLK_IN
reference clock. Internally pulled down to GND.
24 I.C. Internally Connected. Leave unconnected for normal operation.
25 PRE Preemphasis Enable Input. Drive PRE high to enable preemphasis.
26 PLLGND PLL Supply Ground
PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as close to
27 VCCPLL
the device as possible, with the smallest value capacitor closest to the supply pin.
28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
Common-Mode Filter. Optionally connect a capacitor between CMF and LVDSGND to filter
29 CMF
common-mode switching noise.
30, 31 LVDSGND LVDS Supply Ground
32 OUT- Inverting LVDS Serial-Data Output
33 OUT+ Noninverting LVDS Serial-Data Output
LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as
34 VCCLVDS
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
35 RNG1
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
36 RNG0
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

6 _______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Functional Diagram

MAX9247
PRE
RGB_IN 1 OUT+
DC BALANCE/
INPUT LATCH PAR-TO-SER
0 ENCODE OUT-
CNTL_IN
CMF
DE_IN

PCLK_IN
RNG0 PLL TIMING AND CONTROL
RNG1

PWRDWN MAX9247

RL/2
OUT+

VOD
OUT- VOS
RL/2

GND
((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)

OUT+

∆VOS = |VOS(+) - VOS(-)|

VOD(+)
VOD = 0V

VOD(-) VOD(-)
∆VOD = |VOD(+) - VOD(-)|
(OUT+) - (OUT-)

Figure 1. LVDS DC Output Load and Parameters

_______________________________________________________________________________________ 7
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Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
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27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247

tT

VIHmin
PCLK_IN tHIGH
VILmax

tF tR tLOW

Figure 2. Parallel Clock Requirements

OUT+

RL
OUT-

CL CL

80% 80%

20% 20%
(OUT+) - (OUT-)
tRISE tFALL

Figure 3. Output Rise and Fall Times

VIHmin
PCLK_IN
VILmax

tSET tHOLD

RGB_IN[17:0]
VIHmin VIHmin
CNTL_IN[8:0]
VILmax VILmax
DE_IN

Figure 4. Synchronous Input Timing

8 _______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer

MAX9247
EXPANDED TIME SCALE

RGB_IN
N N+1 N+2 N+3 N+4
CNTL_IN

PCLK_IN

N-1 N

OUT_

tSD
BIT 0 BIT 19

Figure 5. Serializer Delay

VILmax
PWRDWN
tLOCK

(OUT+) - (OUT-) HIGH IMPEDANCE VOD = 0V

PCLK_IN

Figure 6. PLL Lock Time

PWRDWN
VILmax

tPD

(OUT+) - (OUT-) HIGH IMPEDANCE

PCLK_IN

Figure 7. Power-Down Delay

_______________________________________________________________________________________ 9
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
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27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247

OUT-

OUT+

((OUT+) + (OUT-))/2
VOS(P-P) VOS(P-P)

Figure 8. Peak-to-Peak Output Offset Voltage

Detailed Description maintains DC balance across the serial cable. Two

transition words, which contain a unique bit sequence,
The MAX9247 DC-balanced serializer operates at a
are inserted at the transition boundaries of video-to-
2.5MHz-to-42MHz parallel clock frequency, serializing
control and control-to-video phases.
18 bits of parallel video data RGB_IN[17:0] when the
data-enable input DE_IN is high, or 9 bits of parallel Control data inputs C0 to C4 are mapped to 3 bits each
control data CNTL_IN[8:0] when DE_IN is low. The in the serial control word (see Table 2). At the deserial-
RGB video input data are encoded using 2 overhead izer, 2 or 3 bits at the same state determine the state of
bits, EN0 and EN1, resulting in a serial word length of the recovered bit, providing single-bit-error tolerance
20 bits (see Table 1). Control inputs are mapped to 19 for C0 to C4. Control data that may be visible if an error
bits and encoded with 1 overhead bit, EN0, also result- occurs, such as VSYNC and HSYNC, can be connect-
ing in a 20-bit serial word. Encoding reduces EMI and ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.

Table 1. Serial Video Phase Word Format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.

Table 2. Serial Control Phase Word Format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.

10 ______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
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27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer

MAX9247
CONTROL TRANSITION TRANSITION CONTROL
PHASE PHASE VIDEO PHASE PHASE PHASE

PCLK_IN

CNTL_IN

DE_IN

RGB_IN

= NOT SAMPLED BY PCLK_IN

Figure 9. Transition Timing

Transition Timing 13 show the AC-coupled serializer and deserializer with

The transition words require interconnect bandwidth four capacitors per link.
and displace control data. Therefore, control data is not
sampled (see Figure 9): Selection of AC-Coupling Capacitors
See Figure 14 for calculating the capacitor values for
• Two clock cycles before DE_IN goes high AC-coupling depending on the parallel clock frequen-
• During the video phase cy. The plot shows capacitor values for two- and four-
• Two clock cycles after DE_IN goes low capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
The last sampled control data are latched at the deserial-
izer control data outputs during the transition and video Frequency-Range Setting RNG[1:0]
phases. Video data are latched at the deserializer RGB The RNG[1:0] inputs select the operating frequency
data outputs during the transition and control phases. range of the MAX9247 serializer. An external clock with-
in this range is required for operation. Table 3 shows
Applications Information the selectable frequency ranges and corresponding
AC-Coupling Benefits data rates for the MAX9247.
AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are Table 3. Parallel Clock Frequency Range
sufficient for isolation, but four capacitors—two at the Select
serializer output and two at the deserializer input—pro-
vide protection if either end of the cable is shorted to a PARALLEL SERIAL-DATA RATE
RNG1 RNG0
high voltage. AC-coupling blocks low-frequency CLOCK (MHz) (Mbps)
ground shifts and common-mode noise. The MAX9247 0 0 2.5 to 5 50 to 100
serializer can also be DC-coupled to the MAX9248/
0 1 5 to10 100 to 200
MAX9250 deserializers.
1 0 10 to 20 200 to 400
Figures 10 and 12 show an AC-coupled serializer and
1 1 20 to 42 400 to 840
deserializer with two capacitors per link. Figures 11 and

______________________________________________________________________________________ 11
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247

VCC

130Ω 130Ω
PRE R/F
* OUTEN

DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
PAR-TO-SER

RGB_IN 1 RGB_OUT

DECODE
1
ENCODE

OUT * IN
0 0 CNTL_OUT
CNTL_IN
DE_OUT
CMF 82Ω 82Ω
DE_IN

PCLK_OUT
RNG0
PCLK_IN PLL
TIMING AND RNG1 REF_IN
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9247 MAX9250

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

*CAPACITORS CAN BE AT EITHER END.

Figure 10. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link

VCC

130Ω 130Ω
PRE R/F
OUTEN
DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
PAR-TO-SER

RGB_IN 1 RGB_OUT
DECODE

1
ENCODE

OUT IN
0 0 CNTL_OUT
CNTL_IN
DE_OUT
CMF 82Ω 82Ω
DE_IN

PCLK_OUT
RNG0
PCLK_IN PLL
TIMING AND RNG1 REF_IN
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9247 MAX9250

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

Figure 11. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link

12 ______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer

MAX9247
VCC

130Ω 130Ω
PRE R/F
*
IN+

DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
PAR-TO-SER

RGB_IN 1 RGB_OUT

DECODE
1
ENCODE

FIFO
OUT * IN- 0 CNTL_OUT
CNTL_IN 0
DE_OUT
CMF 82Ω 82Ω
DE_IN PCLK_OUT

PCLK_IN REFCLK PLL

TIMING AND SSPLL SS
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9247
MAX9248

RNG[0:1]

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

*CAPACITORS CAN BE AT EITHER END.

Figure 12. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link

VCC

130Ω 130Ω
PRE R/F
IN+
DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
PAR-TO-SER

RGB_IN 1 RGB_OUT
DECODE

1
ENCODE

FIFO

OUT
IN- 0 CNTL_OUT
CNTL_IN 0
DE_OUT
CMF 82Ω 82Ω
DE_IN PCLK_OUT

PCLK_IN REFCLK PLL

TIMING AND SSPLL SS
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9247
MAX9248

RNG[0:1]

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

Figure 13. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link

______________________________________________________________________________________ 13
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
LVDS Output Preemphasis (PRE)
MAX9247

AC-COUPLING CAPACITOR VALUE The MAX9247 features a preemphasis mode where extra
vs. PARALLEL CLOCK FREQUENCY current is added to the output and causes the ampli-
140 tude to increase by 40% to 50% at the transition point.
120
Preemphasis helps to get a faster transition, better eye
diagram, and improve signal integrity. See the Typical
Operating Characteristics . The additional current is
CAPACITOR VALUE (nF)

100 FOUR CAPACITORS PER LINK

turned on for a short time (360ps, typ) during data transi-
80 tion, and then turned off. Enable preemphasis by driving
60
PRE high.

40
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the
20 integrated 100Ω output termination, and puts the output
TWO CAPACITORS PER LINK
0
in high impedance to ground and differential. With PWRD-
18 21 24 27 30 33 36 39 42 WN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥
PARALLEL CLOCK FREQUENCY (MHz) VCCIN - 0.3V, supply current is reduced to 50µA or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency switches in the 100Ω output termination resistor. The
of 18MHz to 42MHz LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
Termination tial. The 100Ω integrated termination pulls OUT+ and
The MAX9247 has an integrated 100Ω output-termina- OUT- together while the PLL is locking so that VOD = 0V.
tion resistor. This resistor damps reflections from If VCC = 0, the output resistor is switched out and the LVDS
induced noise and mismatches between the transmis- outputs are high impedance to ground and differential.
sion line impedance and termination resistors at the PLL Lock Time
deserializer input. With PWRDWN = low or with the sup-
ply off, the output termination is switched out and the The PLL lock time is set by an internal counter. The lock
LVDS output is high impedance. time is 17,100 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Common-Mode Filter
Input Buffer Supply
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
is connected to the CMF pin for connecting an optional DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN)
common-mode filter capacitor. Connect the filter are powered from VCCIN. VCCIN can be connected to a
capacitor to ground close to the MAX9247 as shown in 1.71V to 3.6V supply, allowing logic inputs with a nomi-
Figure 15. The capacitor shunts common-mode switch- nal swing of VCCIN. If no power is applied to VCCIN
ing current to ground to reduce EMI. when power is applied to VCC, the inputs are disabled
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Sequencing of MAX9247
OUT+ and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can
RO/2 be powered up in several ways. The best approach is
CMF to keep both MAX9247 and MAX9248 powered down
while supplies are ramping up and PCLK_IN of the
RO/2 CCMF MAX9247 and REFCLK of the MAX9248/MAX9250 are
stabilizing. After all of the power supplies of the
OUT- MAX9247 and MAX9248/MAX9250 are stable, including
PCLK_IN and REFCLK, do the following:
1) Power up the MAX9247 first

Figure 15. Common-Mode Filter Capacitor Connection

14 ______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
2) Wait for at least tLOCK of MAX9247 (or 17100 x tT) Twisted-pair and shielded twisted-pair cables offer

MAX9247
to get activity on the link superior signal quality compared to ribbon cable and
3) Power up the MAX9248 tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
Power-Supply Circuits and Bypassing mode, which is rejected by the LVDS receiver.
The MAX9247 has isolated on-chip power domains. The
digital core supply (VCC) and single-ended input supply Board Layout
(VCCIN) are isolated but have a common ground (GND). Separate the LVTTL/LVCMOS inputs and LVDS output
The PLL has separate power and ground (VCCPLL and to prevent crosstalk. A four-layer PCB with separate lay-
PLLGND) and the LVDS input also has separate power ers for power, ground, and signals is recommended.
and ground (VCCLVDS and LVDSGND). The grounds are ESD Protection
isolated by diode connections. Bypass each VCC, VCCIN, The MAX9247 ESD tolerance is rated for IEC 61000-4-
VCCPLL, and VCCLVDS pin with high-frequency, surface- 2, Human Body Model, Machine Model, and ISO 10605
mount ceramic 0.1µF and 0.001µF capacitors in parallel standards. IEC 61000-4-2 and ISO 10605 specify ESD
as close to the device as possible, with the smallest value tolerance for electronic systems. The IEC 61000-4-2
capacitor closest to the supply pin. discharge components are C S = 150pF and R D =
330Ω (Figure 16). For IEC 61000-4-2, the LVDS outputs
LVDS Output
are rated for ±8kV Contact Discharge and ±15kV Air-
The LVDS output is a current source. The voltage swing
Gap Discharge. The Human Body Model discharge
is proportional to the termination resistance. The output
components are CS = 100pF and RD = 1.5kΩ (Figure
is rated for a differential load of 100Ω ±1%.
17). For the Human Body Model, all pins are rated for
Cables and Connectors ±3kV Contact Discharge. The ISO 10605 discharge
Interconnect for LVDS typically has a differential imped- components are CS = 330pF and RD = 2kΩ (Figure
ance of 100Ω. Use cables and connectors that have 18). For ISO 10605, the LVDS outputs are rated for
matched differential impedance to minimize impedance ±10kV contact and ±30kV air discharge. The Machine
discontinuities. Model discharge components are C S = 200pF and
RD = 0Ω (Figure 19).

RD RD
330Ω 2kΩ

CHARGE-CURRENT- DISCHARGE CHARGE-CURRENT- DISCHARGE

LIMIT RESISTOR RESISTANCE LIMIT RESISTOR RESISTANCE
HIGH- HIGH-
DEVICE CS STORAGE DEVICE
VOLTAGE CS STORAGE VOLTAGE
UNDER 330pF CAPACITOR UNDER
DC 150pF CAPACITOR DC
TEST TEST
SOURCE SOURCE

Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 18. ISO 10605 Contact Discharge ESD Test Circuit

RD RD
1MΩ 1.5kΩ 0Ω

CHARGE-CURRENT- DISCHARGE CHARGE-CURRENT- DISCHARGE

LIMIT RESISTOR RESISTANCE LIMIT RESISTOR RESISTANCE
HIGH- HIGH-
CS STORAGE DEVICE CS DEVICE
VOLTAGE VOLTAGE STORAGE
100pF CAPACITOR UNDER 200pF UNDER
DC DC CAPACITOR
TEST TEST
SOURCE SOURCE

Figure 17. Human Body ESD Test Circuit Figure 19. Machine Model ESD Test Circuit

______________________________________________________________________________________ 15
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Chip Information Package Information
MAX9247

PROCESS: CMOS For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE LAND
OUTLINE NO.
TYPE CODE PATTERN NO.
48 LQFP C48+5 21-0054 90-0093

16 ______________________________________________________________________________________
 Distributor of Maxim Integrated: Excellent Integrated System Limited
Datasheet of MAX9247ETM+ - IC SERIALIZER LVDS 48-TQFN
Contact us: [email protected] Website: www.integrated-circuit.com

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Revision History

MAX9247
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Corrected LQFP package, added +105°C part, changed temperature limits
2 5/08 1–6, 15–19
for +105°C rated part, and added Machine Model ESD text and diagram
Added /V parts in the Ordering Information table and added new Power-
3 4/09 1, 14
Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section
4 4/12 Corrected errors in Absolute Maximum Ratings and Pin Description sections 2, 6

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

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