Report for Lab Assignment 2

Name: Parmar Vishal Pravin (20110126)

Pratyaksh Bhayre(22110205)
TA Name: Teja Prathipati

Part 1:

Objective: Determine the threshold voltage (Vth) of the MOSFET, and identify Vgs,dc.

Circuit Analyzed:
1) 2N7000 Transistor
2) We are giving Vgs using dc voltage source which is between 0.8 V to 2 V with increment
of 0.01 V and note I-drain at the applied voltage to find Threshold Voltage and Vgs,dc
Circuit Diagram:

Methodology : In the circuit first Ground and Source of the transistor is shorted and drain is
connected with an ammeter in series. First we give Vgs = 0.8 using DC Voltage Source. And
note the current using the ammeter in the microampere reading function. After that we increase
the value of voltage by 0.01 V and take readings to find Threshold voltage of the circuit. After
current increases up to 100 microampere we start taking readings in milliampere. And increase
voltage by 0.1V until we find Idc(drain current) between 2.8 and 3 milliampere. Then we take
that value of that voltage as Vgs,dc.
Threshold voltage: Voltage at which current starts flowing from source to drain in Mosfet is
called Threshold voltage.
Vgs,dc : is biased Voltage you add to input signal to get mosfet in saturation region.

Result:

Idc(drain current)(in
Voltage(in V) microampere)
0.8 0
0.81 0
0.87 0
1 1
1.01 1.1
1.02 1.3
1.03 1.6
1.04 1.9
1.05 2.2
1.06 2.6
1.1 5
1.2 23
1.3 90
1.4 264

Voltage (V) Idc(milliampere)

1.5 1.06
1.6 2.6
1.61 2.93
1.615 2.93
1.62 3.04
1.7 5.41
1.8 9.83
1.9 16.16
2 23.7
Ans: We can see that current starts flowing after Voltage = 1 V from that we can say that Vth =
1V. Now we can see that in observation we get Idc = 2.93 mA at 1.61V voltage. We can say that
Vgs,dc = 1.61V at 2.93 mA.

Part 2:

Objective : Calculate the Rd using Vgc,dc, Idc and Vth given. Use this configuration to find
the gain of the MOS amplifier and explain the impact of VAC Small-Signal on Vout.

Circuit analyzed:
1) 2N7000 Transistor
2) Resistor: 1700 ohm
3) We apply 10 V using dc voltage source to drain and give Vgs= sinusoidal signal with
offset of 1.59 DC Voltage.
4) We do frequency analysis in part c of the problem
Circuit diagram:
Methodology:

First we use Rd equal to 1700 ohm and Idc equal to 2.93 mA and find Vgc. which we
give as offset to input sinusoidal signal we are giving to the circuit as input at Vgc.we
give Vd = 10V and connect output to DSO. Then we take frequency 100 to give the
input signal as Vary Vac Small-Signal starting from 20 mV(pk-pk) – 120 mV(pk-pk) in
steps of 10 mV (pk-pk). And draw conclusions about how a small signal affects Vout.
Then we plot the frequency response of the 80 mV(pk-pk) signal.

Finding Rd calculation:

Results:
A) Gain: for 20mV(pk-pk) Voltage at 100 Hz Vout is 920mV (pk-pk) which is
-16.23 dB.
B) Table of gain for frequency 100 Hz and small V signal.
Vin (mV(pk-pk)) Output(V) gain
20 0.92 33.25515663
30 1.36 33.12835307
40 1.8 33.06425028
50 2.2 32.86905353
60 2.66 32.93460772
70 3.06 32.81246773
80 3.46 32.71972224
90 3.9 32.73644195
100 4.34 32.74979459
110 4.84 32.86905353
120 5.28 32.86905353

We can see from above data that there is little to no change in gain. If we check distortion,
cut-off distortion is coming at 800 mV(pk-pk) and linear distortion is coming at 180 mVpp. And
output for that is 7.36 V. but in our case on changing frequency the maximum output is 3.56 Vpp
hence it never goes out of saturation region due to our low resistor (1.7kohm). We took
approximately half the value of maximum resistance we can take. If we take too little resistance
or to high resistance some of our input might get distorted as we met on middle ground. We were
able to reduce this distortion to a minimum. That's why the gain is almost the same.

Key Observations:

1. The gain remains relatively constant despite varying input amplitudes.

2. Distortion:
Cut-off distortion occurs at 800 mV (pk-pk).
Linear distortion begins at 180 mVpp.
3. The maximum output observed is 3.56 Vpp, ensuring the signal stays within the
saturation region.
4. The resistor value of 1.7 kΩ effectively minimized distortion.
-> Graph 180 mVpp and frequency 100 KHz

-> Graph 800mVpp and 100Hz

At 80mVpp make bode plot:

frequency
(KHz) Output(Vpp) gain
0.1 3.48 32.76978514
0.2 3.52 32.86905353
0.4 3.52 32.86905353
0.5 3.52 32.86905353
1 3.52 32.86905353 Observations:
10 3.52 32.86905353 Bode plot :
25 3.56 32.96720022
50 3.48 32.76978514
100 3.44 32.66936911
200 3.24 32.14910046
300 3 31.48062535
500 2.56 30.10299957
700 2.16 28.62727528
800 1.92 27.60422483
1000 1.68 26.44438589
1200 1.4 24.86076097
1500 1.2 23.52182518
As frequencies increase, gain starts decreasing.At high frequencies, the coupling capacitor effect
is negligible and parasitic capacitance reduces the gain of the amplifier.

Challenges faced:
● Measurement Errors: Small discrepancies in measuring R, L, and C.
● Breadboard Issues: Parasitic effects impacted accuracy.
● Frequency Variations: Signal generator inconsistencies.
● Calculation Gaps: Theory didn’t exactly match experiments.
● We took lower value resistor than other people. Our output was different than others we
had confusion about that before finding out the reason behind it.