EEE434 VLSI Design

The CMOS Inverter

circuit perspective
(2)

Instructor: Dr. Muhammad Awais

Department of Electrical & Computer Engineering.

COMSATS University Islamabad, Wah Campus.
 Objectives

▪ The propagation delay of Inverter

▪ Calculation of basic MOS transistor capacitances
▪ Inverter Capacitances
▪ Examples
 Objectives

▪ The propagation delay of Inverter

▪ Calculation of basic MOS transistor capacitances
▪ Inverter Capacitances
▪ Examples
 Propagation Delay
▪ Time it takes for the effect of change at the inputs to be visible at the output
▪ Time required for inputs to be propagated to output

▪ Normally, it is the difference between the time when the input reaches 50% of
its final value to the time when the output reaches 50% of its final value showing
the effect of change
tpHL = prop. delay for high to low output
transition

tpLH = prop. delay for low to high output

transition

tr = rise time (time b/w 10%

and 90% of maximum output
value)
tf= fall time (time b/w 90% and
10% of maximum output value)
 CMOS Inverter – Propagation Delay
For both High to low and low to high transitions, the inverter can be modelled as a 1st
order RC network

𝑡
−𝜏
𝑉𝑜𝑢𝑡 = 1 −𝑒 𝑉𝑑𝑑
To find ‘t’ at Vdd/2
𝑉𝑑𝑑 𝑡
−𝜏
= 1 − 𝑒 𝑉𝑑𝑑
2
𝑡 = ln 2 𝜏 = 0.69𝜏
 CMOS Inverter – Propagation Delay

𝒕𝒑𝑯𝑳 = 𝟎. 𝟔𝟗𝑹𝒆𝒒𝒏 𝑪𝑳 𝒕𝒑𝑳𝑯 = 𝟎. 𝟔𝟗𝑹𝒆𝒒𝒑 𝑪𝑳

Overall propagation delay

𝒕𝒑𝑯𝑳 + 𝒕𝒑𝑳𝑯 𝟎. 𝟔𝟗𝑪𝑳 𝑹𝒆𝒒𝒏 + 𝑹𝒆𝒒𝒑

𝒕𝒑 = =
𝟐 𝟐
2
3 𝑉𝐷𝐷 7 𝑊 𝑉𝐷𝑆𝐴𝑇𝑛
𝑅𝑒𝑞𝑛 ≈ 1 − 𝑉𝐷𝐷 𝐼𝐷𝑆𝐴𝑇𝑛 = 𝐾 ′ ( 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝐷𝑆𝐴𝑇𝑛 − )
4 𝐼𝐷𝑆𝐴𝑇𝑛 9 𝐿 𝑛 2
3 𝑉𝐷𝐷 7 𝑊 2
𝑉𝐷𝑆𝐴𝑇𝑝
𝑅𝑒𝑞𝑝 ≈ 1 − 𝑉𝐷𝐷 𝐼𝐷𝑆𝐴𝑇𝑝 = 𝐾 ′ ( 𝑉𝐷𝐷 − 𝑉𝑇𝑝 𝑉𝐷𝑆𝐴𝑇𝑝 − )
4 𝐼𝐷𝑆𝐴𝑇𝑝 9 𝐿 𝑝 2
 Objectives

▪ The propagation delay of Inverter

▪ Calculation of basic MOS transistor capacitances
▪ Inverter Capacitances
▪ Examples
 MOS TRANSISTOR CAPACITANCE MODEL
In order to compute the load capacitance CL of inverter, we must study the
capacitance model (dynamic behavior) of MOS transistor

The dynamic behavior of MOS transistor

The dynamic response of MOS transistor depends upon the time taken to (dis) charge
its intrinsic capacitance and extra capacitance introduced by load and connecting wires.

Capacitance Model of MOS Transistor

MOS TRANSISTOR CAPACITANCE MODEL

These capacitances originate from three sources of capacitances

1) The structure Capacitances

2) The channel capacitance
3) The junction capacitances
 MOS TRANSISTOR CAPACITANCE MODEL
1) The structure Capacitances
• The gate of MOS transistor is isolated from the conducting channel by gate-oxide
𝝐
which has capacitance per unit area 𝑪𝒐𝒙 = 𝒕 𝒐
𝒐𝒙
• Overlap Capacitances
• Ideally, the source and drain diffusion takes place right at the edge of gate oxide
• But practically, it diffuses below gate oxide by an amount 𝒙𝒅 called lateral diffusion length

• Hence the overlap capacitances for gate to source and drain are computed as

𝑪𝑮𝑺𝑶 = 𝑪𝑮𝑫𝑶 = 𝑪𝒐𝒙 𝒙𝒅 𝑾 = 𝑪𝒐 𝑾

• Overlap capacitances are largely affected by dopping concentrations and oxide thickness
 MOS TRANSISTOR CAPACITANCE MODEL
(2) The Channel Capacitance
• The most significant MOS parasitic capacitance is the gate-to-channel capacitance
𝑪𝑮𝑪 which consists of three components i.e. 𝑪𝑮𝑪𝑺 (gate-source), 𝑪𝑮𝑪𝑫 (gate-drain)
and 𝑪𝑮𝑪𝑩 (gate-body) channel capacitances

𝑪𝑮𝑪

𝑪𝑮𝑪𝑺 𝑪𝑮𝑪𝑩 𝑪𝑮𝑪𝑫

• The individual contributions of these capacitances depend upon the region of

operation and applied terminal voltages
 MOS TRANSISTOR CAPACITANCE MODEL
𝑪𝑮𝑪
(2) The Channel Capacitance

Cut-off Mode
𝑪𝑮𝑪𝑺 𝑪𝑮𝑪𝑩 𝑪𝑮𝑪𝑫
• When VGS< Vth, there is no channel charge. Hence total
gate-channel capacitance is between gate and body
i.e. 𝐶𝐺𝐶𝑆 = 𝐶𝐺𝐶𝐷 = 0 and 𝐶𝐺𝐶 = 𝐶𝐺𝐶𝐵 = 𝐶𝑜𝑥 𝑊𝐿

Triode Mode
• In resistive region, inversion layer is formed hence 𝐶𝐺𝐶𝐵 = 0
𝐶 𝑊𝐿
• 𝐶𝐺𝐶𝑆 = 𝐶𝐺𝐶𝐷 = 𝑜𝑥2
• Total gate capacitance is equally contributed by source & drain

Saturation Mode

• The pinch-off occurs, inversion layer is formed

2𝐶 𝑊𝐿
𝐶𝐺𝐶𝐵 = 𝐶𝐺𝐶𝐷 = 0, CGC= 𝐶𝐺𝐶𝑆 = 𝑜𝑥3
•
MOS TRANSISTOR CAPACITANCE MODEL
The total gate capacitance
𝑪𝑮 = 𝑪𝑮𝑪 + 𝑪𝑮𝑺𝑶 + 𝑪𝑮𝑫𝑶

Operation 𝑪𝑮𝑪𝑩 𝑪𝑮𝑪𝑺 𝑪𝑮𝑪𝑫 𝑪𝑮𝑪 𝑪𝑮

Region
Cut-off 𝑪𝑶𝑿 𝑾𝑳 0 0 𝑪𝑶𝑿 𝑾𝑳 𝑪𝑶𝑿 𝑾𝑳+2𝑪𝒐𝒙 𝒙𝒅 𝑾

Resistive 0 𝑪𝑶𝑿 𝑾𝑳 𝑪𝑶𝑿 𝑾𝑳 𝑪𝑶𝑿 𝑾𝑳 𝑪𝑶𝑿 𝑾𝑳+2𝑪𝒐𝒙 𝒙𝒅 𝑾

2
𝟐
Saturation 0 𝟐 0 𝟐 𝟐
𝑪 𝑾𝑳+2𝑪𝒐𝒙 𝒙𝒅 𝑾
𝑪 𝑾𝑳 𝑪 𝑾𝑳 𝟑 𝑶𝑿
𝟑 𝑶𝑿 𝟑 𝑶𝑿
 MOS TRANSISTOR CAPACITANCE MODEL
(3) The Junction (Diffusion) Capacitance

This capacitance is due to reversed bias source-body and drain-body pn junctions

Ls 𝑥𝑗 : Thickness source (drain) - body junction

𝑊: width of source (drain) junction
𝐿𝑠 : Length of source (drain) – body junction

Source (drain) –body

diffusion capacitance
Cdiff
Picture source: S.M. Kang, Y. Leblebici, “CMOS Digital Circuits”, McGraw Hill, 2003

Bottom Plate Side wall

𝐶𝑏𝑜𝑡𝑡𝑜𝑚 𝐶𝑠𝑤
 MOS TRANSISTOR CAPACITANCE MODEL
(3) The Junction (Diffusion) Capacitance Ls

3.a : Bottom Plate Capacitance

▪ Formed by the source (drain) region (with doping ND)
and the substrate (with doping NA ) underneath it
𝑪𝒃𝒐𝒕𝒕𝒐𝒎 = 𝑪𝒋 𝑾𝑳𝒔 where 𝐶𝑗 : Junction capacitance per unit area

▪ The junction capacitance is a strong non-linear function of applied bias. For a given
reversed bias voltage V between source (drain) and body junctions
𝑪𝒋𝟎 𝐶𝑗0 : Zero bias junction capacitance per unit area
𝑪𝒋 = 𝑽
𝒎𝒋 𝜙𝑏 : built in potential of body junction
𝟏−𝝓
𝒃 𝑚𝑗 : Grading coefficient of PN junction (0.5 or 0.3)

▪ For a given voltage swing from voltages 𝑉ℎ𝑖𝑔ℎ to 𝑉𝑙𝑜𝑤 , the junction capacitance is
approximated by as average junction capacitance
𝒎𝒋
𝝓𝟎 𝟏−𝒎𝒋 𝟏−𝒎𝒋
𝑪𝒋 = 𝑲𝒆𝒒 𝑪𝒋𝒐 where 𝑲𝒆𝒒 = − [ 𝝓𝟎 − 𝑽𝒉𝒊𝒈𝒉 − 𝝓𝟎 − 𝑽𝒍𝒐𝒘 ]
𝑽𝒉𝒊𝒈𝒉 −𝑽𝒍𝒐𝒘 𝟏−𝒎𝒋
 MOS TRANSISTOR CAPACITANCE MODEL
(3) The Junction (Diffusion) Capacitance Ls

3.b : Sidewall junction capacitance

▪ Formed by the source (drain) region (with doping ND)
and p+ channel stop implant (with doping NA ) around it
𝑪𝒔𝒘 = 𝑪𝒋𝒔𝒘 (𝟐𝑳𝒔 + 𝑾) where 𝐶𝑗𝑠𝑤 : Sidewall Junction capacitance per unit
perimeter
▪ The sidewall junction capacitance is also a non-linear function of applied bias. For a given
constant bias voltage V
𝑪𝒋𝒔𝒘𝟎 𝐶𝑗𝑠𝑤0 : Zero bias side junction capacitance per unit area
𝑪𝒋𝒔𝒘 = 𝑽
𝒎𝒋𝒔𝒘 𝜙𝑏𝑠𝑤 : built in potential of body side wall junction
𝟏−𝝓
𝒃𝒔𝒘 𝑚𝑗𝑠𝑤 : Grading coefficient of PN junction (0.5 or 0.3)

▪ For a given voltage swing from voltages 𝑉ℎ𝑖𝑔ℎ to 𝑉𝑙𝑜𝑤 , the sidewall junction capacitance
is approximated by as average junction capacitance
𝑪𝒋𝒔𝒘 = 𝑲𝒆𝒒𝒔𝒘 𝑪𝒋𝒔𝒘𝒐 where
𝒎𝒋𝒔𝒘
𝝓𝒃𝒔𝒘 𝟏−𝒎𝒋𝒔𝒘 𝟏−𝒎𝒋𝒔𝒘
𝑲𝒆𝒒𝒔𝒘 = − [ 𝝓𝒃𝒔𝒘 − 𝑽𝒉𝒊𝒈𝒉 − 𝝓𝒃𝒔𝒘 − 𝑽𝒍𝒐𝒘 ]
𝑽𝒉𝒊𝒈𝒉 − 𝑽𝒍𝒐𝒘 𝟏 − 𝒎𝒋𝒔𝒘
 MOS TRANSISTOR CAPACITANCE MODEL
Putting it altogether

𝑪𝒈𝒔 = 𝑪𝒈𝒄𝒔 + 𝑪𝒈𝒔𝒐

𝑪𝒈𝒅 = 𝑪𝒈𝒄𝒅 + 𝑪𝒈𝒅𝒐

𝑪𝒈𝒃 = 𝑪𝒈𝒄𝒃

𝑪𝒔𝒃 = 𝑪𝒅𝒃 = 𝑪𝒅𝒊𝒇𝒇 = 𝑪𝒃𝒐𝒕𝒕𝒐𝒎 + 𝑪𝒔𝒘 = 𝑪𝒋 𝑾𝑳𝒔 + 𝑪𝒋𝒔𝒘 (𝟐𝑳𝒔 + 𝑾)

 MOS TRANSISTOR CAPACITANCE MODEL
Example : Consider 0.25 um CMOS technology with given parameters
Device 𝒕𝒐𝒙 𝑪𝒐𝒙 𝑪𝒐 𝑳𝒅 = 𝑳𝒔 𝑪𝒋𝟎 𝒎𝒋 𝝓𝒃 𝑪𝒋𝒔𝒘𝟎 𝒎𝒋𝒔𝒘 𝝓𝒃𝒔𝒘
(nm) (𝒇𝑭 (𝒇𝑭/𝝁𝒎) (𝝁𝒎)
/𝝁𝒎 )𝟐 𝒇𝑭 (V) 𝒇𝑭/𝝁𝒎 (V)
/𝝁𝒎𝟐

nMOS 6 6 0.31 0.625 2 0.5 0.9 0.28 0.44 0.9

pMOS 6 6 0.27 0.625 1.9 0.48 0.9 0.22 0.32 0.9

Determine the zero-bias values of all relevant capacitances of nMOS transistor with L=0.24um
and W=0.36um
Solution: Transistor is in cutoff mode under zero bias
𝑪𝒈𝒔 = 𝑪𝒈𝒄𝒔 + 𝑪𝒈𝒔𝒐 = 𝟎 + 𝑪𝒐𝒙 𝒙𝒅 𝑾 = 𝑪𝒐 𝑾 = 𝟎. 𝟏𝟏𝟓𝒇𝑭
𝑪𝒈𝒅 = 𝑪𝒈𝒄𝒅 + 𝑪𝒈𝒅𝒐 = 𝟎 + 𝑪𝒐𝒙 𝒙𝒅 𝑾 = 𝑪𝒐 𝑾 = 𝟎. 𝟏𝟏𝟓𝒇𝑭
𝑪𝒈𝒃 = 𝑪𝒈𝒄𝒃 = 𝑪𝒐𝒙 𝑾𝑳 = 𝟎. 𝟓𝟏𝟖𝟒 𝒇𝑭
𝑪𝒈 = 𝑪𝒐𝒙 𝑾𝑳 + 𝟐𝑪𝑶 𝑾 = 𝟎. 𝟕𝟒𝟏𝟔 𝒇𝑭
𝑪𝒔𝒃 = 𝑪𝒅𝒃 = 𝑪𝒅𝒊𝒇𝒇 = 𝑪𝒃𝒐𝒕𝒕𝒐𝒎 + 𝑪𝒔𝒘 = 𝑪𝒋𝒐 𝑳𝒔 𝑾 + 𝑪𝒋𝒔𝒘𝟎 𝟐𝑳𝒔 + 𝑾
= 𝟐 𝟎. 𝟔𝟐𝟓 𝟎. 𝟑𝟔 𝒇𝑭 + 𝟎. 𝟐𝟖(𝟐 𝟎. 𝟔𝟐𝟓 + 𝟎. 𝟑𝟔))𝒇𝑭 = 𝟎. 𝟗𝟎𝟔𝟒𝒇𝑭
+
 MOS TRANSISTOR CAPACITANCE MODEL
Example : Consider 0.25 um CMOS technology with given parameters
Device 𝒕𝒐𝒙 𝑪𝒐𝒙 𝑪𝒐 𝑳𝒅 = 𝑳𝒔 𝑪𝒋𝟎 𝒎𝒋 𝝓𝒃 𝑪𝒋𝒔𝒘𝟎 𝒎𝒋𝒔𝒘 𝝓𝒃𝒔𝒘
(nm) (𝒇𝑭 (𝒇𝑭/𝝁𝒎) (𝝁𝒎)
/𝝁𝒎 )𝟐 𝒇𝑭 (V) 𝒇𝑭/𝝁𝒎 (V)
/𝝁𝒎𝟐

nMOS 6 6 0.31 0.625 2 0.5 0.9 0.28 0.44 0.9

pMOS 6 6 0.27 0.625 1.9 0.48 0.9 0.22 0.32 0.9

Determine the source (drain) diffusion capacitances of NMOS with L=0.24um

and W=0.36um under the bias conditions when source is connected to GND, drain is connected
to 3 volts, gate is connected to 3 volts supply and body is connected to GND.
Solution: Transistor is in saturation mode. Since source is at zero bias
𝑪𝒔𝒃 = 𝑪𝒅𝒊𝒇𝒇 = 𝑪𝒃𝒐𝒕𝒕𝒐𝒎 + 𝑪𝒔𝒘 = 𝑪𝒋𝒐 𝑳𝒔 𝑾 + 𝑪𝒋𝒔𝒘𝟎 𝟐𝑳𝒔 + 𝑾
= 𝟐 𝟎. 𝟔𝟐𝟓 𝟎. 𝟑𝟔 𝒇𝑭 + 𝟎. 𝟐𝟖(𝟐 𝟎. 𝟔𝟐𝟓 + 𝟎. 𝟑𝟔))𝒇𝑭 = 𝟎. 𝟗𝟎𝟔𝟒𝒇𝑭
𝑪𝒅𝒃 = 𝑪𝒅𝒊𝒇𝒇 = 𝑪𝒃𝒐𝒕𝒕𝒐𝒎 + 𝑪𝒔𝒘 = 𝑪𝒋 𝑳𝒔 𝑾 + 𝑪𝒋𝒔𝒘 𝟐𝑳𝒔 + 𝑾
𝑪𝒋𝟎 𝟐𝒇𝑭
𝑪𝒋 = 𝑽
𝒎𝒋 = −𝟑𝑽 𝟎.𝟓
= 𝟎. 𝟗𝟔𝒇𝑭
𝟏−𝝓 𝟏−𝟎.𝟗𝑽
𝒃
 MOS TRANSISTOR CAPACITANCE MODEL
Problem: Consider 0.25 um CMOS technology with given parameters
Device 𝒕𝒐𝒙 𝑪𝒐𝒙 𝑪𝒐 𝑳𝒅 = 𝑳𝒔 𝑪𝒋𝟎 𝒎𝒋 𝝓𝒃 𝑪𝒋𝒔𝒘𝟎 𝒎𝒋𝒔𝒘 𝝓𝒃𝒔𝒘
(nm) (𝒇𝑭 (𝒇𝑭/𝝁𝒎) (𝝁𝒎)
/𝝁𝒎 )𝟐 𝒇𝑭 (V) 𝒇𝑭/𝝁𝒎 (V)
/𝝁𝒎𝟐

nMOS 6 6 0.31 0.625 2 0.5 0.9 0.28 0.44 0.9

pMOS 6 6 0.27 0.625 1.9 0.48 0.9 0.22 0.32 0.9

Determine all the capacitances capacitances of NMOS with L=0.24um and W=0.36um
under the bias conditions when source is connected to GND, drain is
Switched between 0V to 3V , gate is connected to 3 volts supply and body is connected to GND.
 Objectives

▪ The propagation delay of Inverter

▪ Calculation of basic MOS transistor capacitances
▪ Inverter Capacitances
▪ Examples
 CMOS INVERTER : The Dynamic Behavior
CMOS Inverter Capacitance Model
𝑡𝑝𝐻𝐿 = 0.69 𝑅𝑒𝑞 𝐶𝐿 Time take to charge the load capacitance CL through PMOS
𝑡𝑝𝐿𝐻 = 0.69 𝑅𝑒𝑞 𝐶𝐿 Time take to discharge the load capacitance CL through NMOS

𝑪𝒈𝒅𝟏𝟐 = 𝐂𝐠𝐝𝟏 + 𝐂𝐠𝐝𝟐

Cgd1, Cgd2 : Gate-drain overlap capacitance
of M1 and M2
Cdb1, Cdb2 : drain-body diffusion
capacitance of M1 and M2
Cw = wiring capacitance
Cg3, Cg4 : gate capacitance of fan-out
transistors M3 and M4

Source: Rabaey, Digital Integrated Circuits, 2nd Ed

𝑪𝑳 = ∑(𝑪𝒈𝒅𝟏𝟐 , 𝑪𝒅𝒃𝟏 , 𝑪𝒅𝒃𝟐 , 𝑪𝒘 , 𝑪𝒈𝟑 , 𝑪𝒈𝟒 )

 CMOS INVERTER : The Dynamic Behavior
Computing the capacitances
Overlap capacitances

𝑪𝒈𝒅𝟏𝟐 = 𝑪𝒈𝒅𝟏 + 𝑪𝒈𝒅𝟐

𝑪𝒈𝒅𝟏 = 𝟐𝑪𝑮𝑫𝑶𝒏 𝑾𝒏 = 𝟐𝑪𝑶 𝑾𝒏
𝑪𝒈𝒅𝟐 = 𝟐𝑪𝑮𝑫𝑶𝒑 𝑾𝒑 = 𝟐𝑪𝑶 𝑾𝒑

Where 𝐶𝐺𝐷𝑂 is the gate-drain overlap capacitance per unit width (Spice Parameter)

Diffusion capacitances (Cdb1, Cdb2)

𝐶𝑑𝑏 = 𝐶𝑑𝑖𝑓𝑓 = 𝐶𝑏𝑜𝑡𝑡𝑜𝑚 +𝐶𝑠𝑤 = Cj WLd + Cjsw (2Ld + W)
= K eq Cj0 𝐴𝑑 + K eqsw Cjsw0 𝑃𝑑
𝒎𝒋
𝝓𝟎 𝟏−𝒎𝒋 𝟏−𝒎𝒋
𝑲𝒆𝒒 = − [ 𝝓𝟎 − 𝑽𝒉𝒊𝒈𝒉 − 𝝓𝟎 − 𝑽𝒍𝒐𝒘 ]
𝑽𝒉𝒊𝒈𝒉 − 𝑽𝒍𝒐𝒘 𝟏 − 𝒎𝒋
𝒎𝒋𝒔𝒘
𝝓𝒃𝒔𝒘 𝟏−𝒎𝒋𝒔𝒘 𝟏−𝒎𝒋𝒔𝒘
𝑲𝒆𝒒𝒔𝒘 = − [ 𝝓𝒃𝒔𝒘 − 𝑽𝒉𝒊𝒈𝒉 − 𝝓𝒃𝒔𝒘 − 𝑽𝒍𝒐𝒘 ]
𝑽𝒉𝒊𝒈𝒉 − 𝑽𝒍𝒐𝒘 𝟏 − 𝒎𝒋𝒔𝒘
 CMOS INVERTER : The Dynamic Behavior
Computing the capacitances
Wiring Capacitance
▪ CW depends the length and width of
connecting wires
▪ and it is a function of the distance of
fanout from the driving gate and number of fanouts
▪ A layout extraction program precisely gives value
of this parasitic capacitance
Gate Capacitance of Fanout Cg3 and Cg4

▪ The fanout capacitance equal to the total gate capacitance of loading gates M3 and M4

𝐶𝑔3 = 𝐶𝑔(𝑛𝑚𝑜𝑠) = 𝐶𝑔𝑠𝑜 + 𝐶𝑔𝑑𝑜 + 𝐶𝑔𝑐 = 𝑪𝑮𝑫𝑶𝒏 𝑾𝒏 + 𝑪𝑮𝑺𝑶𝒏 𝑾𝒏 + 𝑪𝒐𝒙 𝑾𝒏 𝑳𝒏

𝐶𝑔4 = 𝐶𝑔(𝑝𝑚𝑜𝑠) = 𝐶𝑔𝑠𝑜 + 𝐶𝑔𝑑𝑜 + 𝐶𝑔𝑐 = 𝑪𝑮𝑫𝑶𝒑 𝑾𝒑 + 𝑪𝑮𝑺𝑶𝒑 𝑾𝒑 + 𝑪𝒐𝒙 𝑾𝒑 𝑳𝒑
 CMOS INVERTER : The Dynamic Behavior
Putting it Altogether

Capacitance Expression
𝐶𝑔𝑑1 2𝐶𝐺𝐶𝐷𝑂𝑛 𝑊𝑛
𝐶𝑔𝑑2 2𝐶𝐺𝐶𝐷𝑂𝑝 𝑊𝑝
𝐶𝑑𝑏1 𝐾𝑒𝑞𝑛 𝐴𝑑𝑛 𝐶𝑗𝑜 + 𝐾𝑒𝑞𝑠𝑤𝑛 𝐶𝑗𝑠𝑤𝑛 𝑃𝑑𝑛
𝐶𝑑𝑏2 𝐾𝑒𝑞𝑝 𝐴𝑑𝑝 𝐶𝑗𝑜 + 𝐾𝑒𝑞𝑠𝑤𝑝 𝐶𝑗𝑠𝑤𝑝 𝑃𝑑𝑛
𝐶𝑔3 (𝐶𝐺𝐷𝑂𝑛 +𝐶𝐺𝑆𝑂𝑛 )𝑊𝑛 + 𝐶𝑜𝑥 𝑊𝑛 𝐿𝑛

𝐶𝑔4 (𝐶𝐺𝐷𝑂𝑝 +𝐶𝐺𝑆𝑂𝑝 )𝑊𝑝 + 𝐶𝑜𝑥 𝑊𝑝 𝐿𝑝

𝐶𝑤 From layout extraction tool

CL ∑
 CMOS INVERTER : The Dynamic Behavior
Example
Consider an inverter designed using 0.25um CMOS
technology @2.5Vdd, whose main parameters are given as
Device 𝒕𝒐𝒙 𝑪𝒐𝒙 𝑪𝒐 𝑳𝒅 = 𝑳𝒔 𝑪𝒋𝟎 𝒎𝒋 𝝓𝒃 𝑪𝒋𝒔𝒘𝟎 𝒎𝒋𝒔𝒘 𝝓𝒃𝒔𝒘
(nm) (𝒇𝑭 (𝒇𝑭/𝝁𝒎) (𝝁𝒎)
/𝝁𝒎 )𝟐 𝒇𝑭 (V) 𝒇𝑭/𝝁𝒎 (V)
/𝝁𝒎𝟐

nMOS 6 6 0.31 0.625 2 0.5 0.9 0.28 0.44 0.9

pMOS 6 6 0.27 0.625 1.9 0.48 0.9 0.22 0.32 0.9

Device 𝑾/𝑳 𝑨𝒅 (𝝁𝒎𝟐 ) 𝑷𝒅 (𝝁𝒎) 𝑨𝒔 (𝝁𝒎) 𝑷𝒔 (𝝁𝒎) 𝑹𝒆𝒒 (kOhm)

Compute the
Propagation delay
nMOS 0.375/0. 0.3 1.875 0.3 1.875 13/(W/L)
tp
25
pMOS 1.125/0. 0.7 2.375 0.7 2.375 31/(W/L)
25
 CMOS INVERTER : The Dynamic Behavior
Solution:
Tphl = time between Vout= VOH and 50% of VOH (i.e. time between Vout = Vdd and Vout=Vdd/2)
Tphl = time between Vout= VOL and 50% of VOH (i.e. time between Vout = 0 and Vout=Vdd/2)
Step 1
From the given parameters in previous tables.
𝐶𝑜 𝑛𝑚𝑜𝑠 = 𝐶𝐺𝐷𝑂𝑛 = 0.31 𝐶𝑜 𝑝𝑚𝑜𝑠 = 𝐶𝐺𝐷𝑂𝑝 = 0.27

𝟎. 𝟑𝟏𝒇𝑭
𝑪𝒈𝒅𝟏 = 𝟐𝑪𝑮𝑫𝑶𝒏 𝑾𝒏 = 𝟐 𝟎. 𝟑𝟕𝟓𝝁𝒎 = 𝟎. 𝟐𝟑𝒇𝑭
𝝁𝒎
𝟎. 𝟐𝟕𝒇𝑭
𝑪𝒈𝒅𝟐 = 𝟐𝑪𝑮𝑫𝑶𝒑 𝑾𝒑 = 𝟐 𝟏. 𝟏𝟐𝟓𝝁𝒎 = 𝟎. 𝟔𝟏𝒇𝑭
𝝁𝒎

Both overlap capacitances remain same during H->L and L->H transitions
 CMOS INVERTER : The Dynamic Behavior
Solution:
Step 2 Drain-body diffusion capacitances
▪ This capacitance depends upon the reversed bias voltage between drain and body

Cdb1 = drain-body diffusion capacitance for nMOS

High to Low transition Low to High transition

From Vout=2.5V to 1.25 V From Vout=0V to 1.25 V

Since body of nMOS is connected to GND.

𝑉ℎ𝑖𝑔ℎ = 𝑉𝑏 − 𝑉𝑑 = 0 − 𝑉𝑜𝑢𝑡 = −2.5 𝑉𝑙𝑜𝑤 = 𝑉𝑏 − 𝑉𝑑 = 0 − 0 = 0

𝑉𝑙𝑜𝑤 = 𝑉𝑏 − 𝑉𝑑 = 0 − 𝑉𝑜𝑢𝑡 = −1.5 𝑉ℎ𝑖𝑔ℎ = 𝑉𝑏 − 𝑉𝑑 = 0 − 1.25 = −1.25
Bottom Plate Bottom Plate
𝑚𝑗 = 0.5, 𝜙𝑏 = 0.9, 𝐶𝑗0 = 2 𝑚𝑗 = 0.5, 𝜙𝑏 = 0.9, 𝐶𝑗0 = 2
𝑲𝒆𝒒 = 𝟎. 𝟓𝟕 𝑲𝒆𝒒 = 𝟎. 𝟕𝟗

Sidewall Sidewall
𝑚𝑗𝑠𝑤 = 0.44, 𝜙𝑏𝑠𝑤 = 0.9, 𝐶𝑗𝑠𝑤 = 0.28 𝑚𝑗𝑠𝑤 = 0.44, 𝜙𝑏𝑠𝑤 = 0.9, 𝐶𝑗𝑠𝑤 = 0.28
𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟔𝟏 𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟖𝟏
 CMOS INVERTER : The Dynamic Behavior
Solution:
Step 2 Drain-body diffusion capacitances
▪ This capacitance depends upon the reversed bias voltage between drain and body

Cdb1 = drain-body diffusion capacitance for nMOS

High to Low transition Low to High transition

From Vout=2.5V to 1.25 V From Vout=0V to 1.25 V

𝐶𝑑𝑏1 = 𝐾𝑒𝑞𝑛 𝐴𝑑 𝐶𝑗0 + 𝐾𝑒𝑞𝑠𝑤 𝑃𝑑 𝐶𝑗𝑠𝑤0 𝐶𝑑𝑏1 = 𝐾𝑒𝑞𝑛 𝐴𝑑 𝐶𝑗0 + 𝐾𝑒𝑞𝑛 𝑃𝑑 𝐶𝑗𝑠𝑤0

𝑲𝒆𝒒 = 𝟎. 𝟓𝟕, 𝑨𝒅 = 𝟎. 𝟑𝝁𝒎𝟐 , 𝑪𝒋𝒐 = 𝟐𝒇𝑭/𝝁𝒎𝟐 𝑲𝒆𝒒 = 𝟎. 𝟕𝟗, 𝑨𝒅 = 𝟎. 𝟑𝝁𝒎𝟐 , 𝑪𝒋𝒐 = 𝟐𝒇𝑭/𝝁𝒎𝟐
𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟔𝟏, 𝑷𝒅 = 𝟏. 𝟖𝟕𝟓𝝁𝒎, 𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟖𝟏, 𝑷𝒅 = 𝟏. 𝟖𝟕𝟓𝝁𝒎,
𝑪𝒋𝑺𝑾𝒐 = 𝟎. 𝟐𝟖𝒇𝑭/𝝁𝒎 𝑪𝒋𝑺𝑾𝒐 = 𝟎. 𝟐𝟖𝒇𝑭/𝝁𝒎

𝑪𝒅𝒃𝟏 = 𝟎. 𝟗0
𝑪𝒅𝒃𝟏 = 𝟎. 𝟔𝟔
 CMOS INVERTER : The Dynamic Behavior
Solution:
Step 2 Drain-body diffusion capacitances
▪ This capacitance depends upon the reversed bias voltage between drain and body

Cdb2 = drain-body diffusion capacitance for pMOS

High to Low transition Low to High transition

From Vout=2.5V to 1.25 V From Vout=0V to 1.25 V

Since body of pMOS is connected to Vdd.

𝑉𝑙𝑜𝑤 = 𝑉𝑑 − 𝑉𝑏 = 2.5 − 2.5 = 0 𝑉ℎ𝑖𝑔ℎ = 𝑉𝑑 − 𝑉𝑏 = 0 − 2.5 = −2.5

𝑉ℎ𝑖𝑔ℎ = 𝑉𝑑 − 𝑉𝑏 = 1.25 − 2.5 = −1.25 𝑉𝑙𝑜𝑤 = 𝑉𝑑 − 𝑉𝑏 = 1.25 − 2.5 = −1.25
Bottom Plate Bottom Plate
𝑚𝑗 = 0.48, 𝜙𝑏 = 0.9, 𝐶𝑗0 =1.9 𝑚𝑗 = 0.48, 𝜙𝑏 = 0.9, 𝐶𝑗0 = 1.9
𝑲𝒆𝒒 = 𝟎. 𝟕𝟗 𝑲𝒆𝒒 = 𝟎. 𝟓𝟗

Sidewall Sidewall
𝑚𝑗𝑠𝑤 = 0.32, 𝜙𝑏𝑠𝑤 = 0.9, 𝐶𝑗𝑠𝑤 = 0.22 𝑚𝑗𝑠𝑤 = 0.32, 𝜙𝑏𝑠𝑤 = 0.9, 𝐶𝑗𝑠𝑤 = 0.22
𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟖𝟔 𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟕
 CMOS INVERTER : The Dynamic Behavior
Solution:
Step 2 Drain-body diffusion capacitances
▪ This capacitance depends upon the reversed bias voltage between drain and body

Cdb2 = drain-body diffusion capacitance for pMOS

High to Low transition Low to High transition

From Vout=2.5V to 1.25 V From Vout=0V to 1.25 V

𝐶𝑑𝑏1 = 𝐾𝑒𝑞 𝐴𝑑 𝐶𝑗0 + 𝐾𝑒𝑞𝑠𝑤 𝑃𝑑 𝐶𝑗𝑠𝑤0 𝐶𝑑𝑏1 = 𝐾𝑒𝑞 𝐴𝑑 𝐶𝑗0 + 𝐾𝑒𝑞𝑠𝑤 𝑃𝑑 𝐶𝑗𝑠𝑤0

𝑲𝒆𝒒 = 𝟎. 𝟕𝟏, 𝑨𝒅 = 𝟎. 𝟕𝝁𝒎𝟐 , 𝑪𝒋𝒐 = 𝟏. 𝟗𝒇𝑭/𝝁𝒎𝟐𝑲𝒆𝒒 = 𝟎. 𝟓𝟗, 𝑨𝒅 = 𝟎. 𝟕𝝁𝒎𝟐 , 𝑪𝒋𝒐 = 𝟏. 𝟗𝒇𝑭/𝝁𝒎𝟐

𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟖𝟔, 𝑷𝒅 = 𝟐. 𝟑𝟕𝟓𝝁𝒎, 𝑲𝒆𝒒𝒔𝒘 = 𝟎. 𝟕, 𝑷𝒅 = 𝟐. 𝟑𝟕𝟓𝝁𝒎,
𝑪𝒋𝑺𝑾𝒐 = 𝟎. 𝟐𝟐𝒇𝑭/𝝁𝒎 𝑪𝒋𝑺𝑾𝒐 = 𝟎. 𝟐𝟐𝒇𝑭/𝝁𝒎

𝑪𝒅𝒃𝟐 = 𝟏. 𝟏𝟓
𝑪𝒅𝒃𝟐 = 𝟏. 𝟓
 CMOS INVERTER : The Dynamic Behavior
Solution:
Step 3 Gate Capacitance of Fanout Cg3, Cg4

𝐶𝑔3 = Gate Capacitance of nMOS

= (𝐶𝐺𝐷𝑂𝑛 +𝐶𝐺𝑆𝑂𝑛 )𝑊𝑛 + 𝐶𝑜𝑥 𝑊𝑛 𝐿𝑛 = 2𝐶0 𝑊𝑛 + 𝐶𝑜𝑥 𝑊𝑛 𝐿𝑛

0.31𝑓𝐹 6𝑓𝐹
𝐶𝑜 = , 𝐶𝑜𝑥 = , 𝑊 = 0.375, 𝐿𝑛 = 0.25
𝜇𝑚 𝜇𝑚2 𝑛
𝑪𝒈𝟑 =0.76

𝐶𝑔4 = Gate Capacitance of pMOS

= (𝐶𝐺𝐷𝑂𝑝 +𝐶𝐺𝑆𝑂𝑝 )𝑊𝑝 + 𝐶𝑜𝑥 𝑊𝑝 𝐿𝑃 = 2𝐶0 𝑊𝑝 + 𝐶𝑜𝑥 𝑊𝑝 𝐿𝑝

0.27𝑓𝐹 6𝑓𝐹
𝐶𝑜 = , 𝐶𝑜𝑥 = , 𝑊 = 1.125, 𝐿𝑝 = 0.25
𝜇𝑚 𝜇𝑚2 𝑝
𝑪𝒈𝟒 =2.28
 CMOS INVERTER : The Dynamic Behavior
Capacita Expression Value for H-L Value for L-H
nce transition transition
𝐶𝑔𝑑1 2𝐶𝐺𝐶𝐷𝑂𝑛 𝑊𝑛 0.23fF 0.23fF
𝐶𝑔𝑑2 2𝐶𝐺𝐶𝐷𝑂𝑝 𝑊𝑝 0.61fF 0.61fF
𝐶𝑑𝑏1 𝐾𝑒𝑞𝑛 𝐴𝑑𝑛 𝐶𝑗𝑜 + 𝐾𝑒𝑞𝑠𝑤𝑛 𝐶𝑗𝑠𝑤𝑛 𝑃𝑑𝑛 0.6fF 0.90fF
𝐶𝑑𝑏2 𝐾𝑒𝑞𝑝 𝐴𝑑𝑝 𝐶𝑗𝑜 + 𝐾𝑒𝑞𝑠𝑤𝑝 𝐶𝑗𝑠𝑤𝑝 𝑃𝑑𝑛 1.5fF 1.15fF
𝐶𝑔3 (𝐶𝐺𝐷𝑂𝑛 +𝐶𝐺𝑆𝑂𝑛 )𝑊𝑛 + 𝐶𝑜𝑥 𝑊𝑛 𝐿𝑛 0.76fF 0.76fF

𝐶𝑔4 (𝐶𝐺𝐷𝑂𝑝 +𝐶𝐺𝑆𝑂𝑝 )𝑊𝑝 + 𝐶𝑜𝑥 𝑊𝑝 𝐿𝑝 2.28fF 2.28fF

𝐶𝑤 From layout extraction tool 0.12fF 0.12fF

CL ∑ 6.1fF 6.0fF

13 31
𝑅𝑒𝑞𝑛 = = 8.6𝑘Ω 𝑅𝑒𝑞𝑝 = = 6.8𝑘Ω
𝑊 𝑊/𝐿
𝐿 𝑛
𝑇𝑝𝐿𝐻 = 0.69𝑅𝑒𝑞𝑝 𝐶𝐿 𝐿 → 𝐻 = 0.69 × 6.8𝐾 × 6.0𝑓 = 29𝑝𝑠𝑒𝑐
𝑇𝑝𝐻𝐿 = 0.69𝑅𝑒𝑞𝑛 𝐶𝐿 𝐻 → 𝐿 = 0.69 × 8.6𝐾 × 6.1𝑓 = 36𝑝𝑠𝑒𝑐
(𝑇𝑝𝐻𝐿 +𝑇𝑝𝐿𝐻 )
𝑇𝑝 = = 32.5 𝑝𝑠𝑒𝑐
2
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