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Indrajit RTL Design Engineer 11+ 002

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Avinash Chiguluri
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23 views2 pages

Indrajit RTL Design Engineer 11+ 002

indra3

Uploaded by

Avinash Chiguluri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Indrajit Paul

Email: [email protected]
Mobile: +91-9614480169 (Whatsapp)
Languages: English, Hindi, Bengali (Mother Tongue), German (B1) India

Objective: Experienced Design & Validation Engineer with 11+ years of expertise in RTL
Frontend development. Proficient in digital design, Seeking challenging opportunities to
contribute skills and knowledge in cutting-edge projects.

Education:
University Institute of Technology, Burdwan, India
Bachelor's Degree (B.E) in Electronics & Instrumentation Engineering (08/2008-07/2012) - 70%

Skills:
RTL Design (Verilog, VHDL)
MATLAB, Python (Basic)
AMBA AHB, APB, AXI Bus protocol, USB 2.0 & 3.0, I2C, SPI, UART
FPGA (Xilinx ISE 14.7 & Vivado & Vitis, Quartus)
Verification & UVM, ModelSim
SoC Design

Summary: Highly skilled Digital Design professional with expertise in FPGA development,
VHDL, Verilog, and C/C++. Proven track record in synthesis, implementation, debugging, RTL,
CDC, and timing analysis. Capable of creating Intellectual Property (IP) and adept in schematic
design. Experienced in utilizing lab instruments such as oscilloscopes, frequency generators,
and multimeters.

Professional Experience:

Sr. Design Lead, Green Semiconductor Pvt Ltd. (Aug 2022 - Present)
Project: MRAM interfacing with PCIe
Responsible for RTL design using Verilog, IP development, Soc development, synthesis,
implementation, simulation, and debugging.
Prototyped on Xilinx Vivado.

Sr. Design Lead, Xilinx Inc. (Aug 2021- June 2022)


Project: CIPS (Versal ACAP) Design and Validation
Led design and validation efforts for CIPS enhancements.
Created block diagrams and applications using Vitis with C.

Design Lead, Innominds Software Pvt Ltd. (Mar 2021- Aug 2021)
Project: MIPI CSI-2.0 (Transmitter) for Video Processing
Developed RTL, performed CDC and timing analysis, and conducted synthesis.
Implemented features such as image pixel value to binary conversion, merging in 4-data lane,
PLL frequency generation, low-pass filter, and error correction.

Sr. Design Engineer, ALBOT Technologies (Contractual Position) (04/2020-02/2021)


Project: Positive Ventilator Design Using FPGA (Bio-Medical)
Designed I2C, SPI, and UART using VHDL, created complex IPs, and integrated into the Zynq
Mpsoc using Vivado.
Conducted synthesis, implementation, and hardware debugging, ensuring CDC and timing error
checks.

Design Engineer, Endivite Technology (01/2019-04/2020)


Project: Camera Module using Zynq7000 Board (Automation & Automotive)
Developed I2C, SPI, and display control (RGB) code using VHDL, simulated and integrated into
Zynq IP using Vivado.
Ensured successful implementation, debugging, and thorough CDC and timing error checks.

Design Engineer, Intel, Germany (Outsourcing by UST Global) (09/2017-01/2019)


Project: Driving Control Using Moisture Sensor (Automotive)
Contributed to RTL development using VHDL, board-level hardware development, and driving
technology projects from specification to release.
Played a key role in project coordination, technical reviews, and compliance with standards.

FPGA Developer, CosMicIT GmbH (05/2016-09/2017)


Project: Cutting Edge Design Machine (Automotive)
Responsible for RTL development and hardware debugging.

Embedded Hardware Engineer, (06/2015-07/2015)


Instructed on embedded hardware design, Embedded C programming, circuit design, and
schematic capture using NI Multisim & NI Ultiboard.

Project Engineer, Power One Solar Ltd (08/2012-11/2013)


Project: Solar Inverter Design
RTL Design for the solar inverter controller and validation on FPGA

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