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Indrajit RTL Design Engineer 11+ 003

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Avinash Chiguluri
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41 views3 pages

Indrajit RTL Design Engineer 11+ 003

indra4

Uploaded by

Avinash Chiguluri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Indrajit Paul

Professional: FPGA Design& Validation Engineer


Email: [email protected] Mobile: +91-9614480169(Whatsapp)
Language: English (Native), Hindi, Bengali (Mother's tongue), German (B1)
India

Education: 08/2008-07/2012University Institute of Technology, Burdwan, India.


Bachelor's Degree (B.E) in Electronics & Instrumentation Engineering with 70%.
Professional Experience: Sr. FPGA Design (RTL Frontend) Engineer with 11+ Years of
experience.
Skills:

 Digital Design  Quartus


 FPGA  SoC Design
 RTL Design  ModelSim
 MATLAB  Ethernet
 Python (Basic)  Measurement & Calibration
 VHDL  Debugging
 Verilog  Oscilloscope, Function Generator &
 AMBA AHB,APB, AXI Bus protocol Signal Analyzer
 USB 2.0 & 3.0, I2C, SPI, UART  Chipscope, ILA
 Verification & UVM  Linux & Windows10
 Xilinx ISE 14.7 & Vivado & Vitis

Summary:
Having an experience in Digital Design.
Having an experience in FPGA Design.
Having experience in VHDL, Verilog.
Having an experience in C/C++
Having an experience in Synthesis, Implementation and Debug.
Having experience in RTL, CDC and Timing analysis
Having the experience to create a new IP (Intellectual Property).
Having a good understanding of schematic design
Having experience in Lab Instruments just oscilloscopes, Frequency generators, multimeters
etc.

Professional Experience:

08/2022-Currently: Currently working as Sr. RTL Design (Frontend) at Green Semiconductor


Pvt Ltd.
Project: MRAM interfacing with PCIe
Client: Avalanche Tech Inc
Task: Creating RTL using Verilog, IP design and Soc Development, Synthesis, Implementation,
Simulation and Debugging
Software: Xilinx Vivado
07/2021-06/2022: Working as Senior FPGA Design Engineer at Xilinx Inc. (outsourcing by
Vaaluka Solution Pvt Ltd).
Project Name: CIPS (Versal ACAP) Validation.
CIPS Validation and Peripheral Testing.
Project Responsibility: Creating a block diagram and also creating an application of the project
in Vitis using C.
Hardware Used: VCK 190, Tenzing.

03/2021-07/2021: Working as an FPGA Design Engineer at Innominds Software Pvt Ltd.


Project Name: MIPI CSI-2.0 (Transmitter) for Video Processing.
Industry: Bio-Medical
Project Responsibility: Creating RTL and checking CDC, timing error and also synthesis.
1. Image Pixel value to binary
2. Merging in 4-Data lane
3. Creating 1.5 GHz (PLL) Frequency for the clock lane.
4. Low Pass Filter.
5. Packet Header Error Correction Code (Hamming Code)
6. ECC Generation on TX Side (Parity Generator)
Make the code and also make the test bench.

04/2020-02/2021: Working as an FPGA Design Engineer at ALBOT Technologies (Contractual


Position).
Project Name: Positive Ventilator Design Using FPGA.
Industry: Bio-Medical
My Responsibility:
1. Create the I2C, SPI, and UART using VHDL and also simulate it.
2. Make a complex IP and simulate it.
3. Take the Zynq Mpsoc IP from Vivado add your IP in Vivado and synthesise the design.
4. Check the Implementation and also debug into the hardware.
5. Check also cdc and timing error.

01/2019-04/2020: Working as an FPGA Design Engineer (Endivite Technology).


Project Name: Camera module using Zynq7000 Board (Zynq 7000 SoC) or Zed Hardware.
Industry: Automation & Automotive
My Responsibility:
1. Create the I2C, SPI, and Display control (RGB) code using VHDL and also simulate it.
2. Make a complex IP and simulate it.
3. Take the Zynq IP from Vivado add your IP in Vivado and synthesise the design.
4. Check the Implementation and also debug into the hardware.
5. Check also cdc and timing error.

09/2017-01/2019: FPGA Design Engineer at Intel, Germany (Outsourcing by UST Global)


(Munich, Germany).
Project Name: Driving Control Using by Sensor (Moisture).
Industry: Automotive
My Role: RTL Development by VHDL and Hardware Development (Board)
Key Result Areas:
Driving technology/development projects in all phases from specification to release
Participating in development projects to help teams choose the best embedded platform
solution
Design and test circuits and other electronic components
Leveraging knowledge of embedded solutions to contribute to ongoing product development work
Participating in technical and quality reviews of embedded development work
Coordinating with project managers, product/solutions certification
Creating and reviewing specification documents ensuring that the designs comply with relevant
international, project-specific and internal standards; leading design reviews and upholding
hardware design standards and methodologies.

05/2016-09/2017: CosMicIT GmbH (Munich, Germany) as FPGA Hardware developer.


Projects: Cutting Edge Design Machine
Industry: Automotive
Role: Make the RTL and also debug into the Hardware

06/2015-07/2015: Embedded hardware trainer Apex online IT training.


Tasks: Instructor
My responsibility as an embedded hardware trainer. My Tasks field includes embedded
hardware design, Embedded C programming in the wedge, circuit design and schematic
Capture using NI Multisim & NI Ultiboard. Use ichSAMV71 ARM9 Cortex microcontroller.

08/2012-11/2013: Project ("Power one solar Lrg"): Solar Inverter Design. (Developers of
electrical engineering)
Tasks: As an electrical engineer I was responsible for the hardware Design as well as analogue
and digital, PCB design and schematics capture and Programming for the automatic (embedded
C).

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