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Electronics and Digital Circuit Project 2.0

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39 views9 pages

Electronics and Digital Circuit Project 2.0

Uploaded by

sumitpandey8569
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELECTRONICS AND DIGITAL CIRCUIT PROJECT

BATCH 2023-27

TITLE: NOR, OR GATE USING MOSFET


GROUP NO. 08
PROF: Mousumi Bhanja

STUDENT NAME’S:
1] Sreejita Bharadwaj [23070123130]
2] Srihari Nair [23070123131]
3] Subham [23070123132]
4] Sumit Pandey [23070123133]
5] Sundaravadivelan Karthikeyan
[23070123136]
6]Sunidhi Choubey [23070123137]
ABSTRACT:
This report outlines the design and simulation of NOR and OR logic
gates using NMOS and PMOS transistors in LTSpice. These gates are
essential components in digital logic circuits. A NOR gate performs the
logical NOR operation, while an OR gate performs the OR operation.

In CMOS technology, both NMOS and PMOS transistors are utilized to


construct logic gates. CMOS logic gates have low static power
consumption, high noise immunity, and good performance.

Objective:
The primary objective of this project is to design and simulate:
1. A NOR gate using NMOS and PMOS transistors.
2. An OR gate using NMOS and PMOS transistors.

The functionality of the gates will be verified through simulation in


LTSpice, and the results will be compared with
theoretical expectations.
Theory:
NOR Gate:
A NOR gate is a universal gate and performs the complement of the
OR operation. The output of a NOR gate is high (1) only when all
inputs are low (0). The output is low (0) if any one of the inputs is
high (1).

The truth table for a 2-input NOR gate is as follows:


A B Y
0 0 1
0 1 0
1 0 0
1 1 0

OR Gate:
An OR gate outputs high (1) when at least one of the inputs is high
(1). The truth table for a 2-input OR gate is as follows:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
MOSFET Logic Design:

In CMOS (Complementary Metal-Oxide-Semiconductor) technology,


logic gates are constructed using both NMOS and PMOS transistors.

NMOS Transistors: Conduct when the gate voltage is high (logic 1),
creating a low-resistance path between the drain and source.
PMOS Transistors: Conduct when the gate voltage is low (logic 0),
creating a low-resistance path between the drain and source.

In a NOR gate:
The NMOS transistors are connected in parallel for the OR operation.
The PMOS transistors are connected in series to invert the OR
operation (achieving NOR).

For an OR gate (as an additional step):


A combination of two NOR gates, with the output of the first NOR
gate is the input of the second NOR gate is used to achieve the
OR functionality.
NOR Gate Circuit Design:

The NOR gate circuit is designed using 2 PMOS transistors in series


and 2 NMOS transistors in parallel, as shown in Figure 1 below.

• PMOS Configuration: The PMOS transistors are placed in series


between Vdd (high) and the output node.
• NMOS Configuration: The NMOS transistors are placed in
parallel between the output node and ground (GND).

Schematic Diagram:
OR Gate Circuit Design:

The OR gate circuit is designed using 4 PMOS transistors in series and


4 NMOS transistors in parallel, as shown in Figure 2 below.

• PMOS Configuration: The PMOS transistors are placed in series


between Vdd (high) and the output node.
• NMOS Configuration: The NMOS transistors are placed in
parallel between the output node and ground (GND).
• A combination of two NOR gates, with the output of the first
NOR gate is the input of the second NOR gate is used to achieve
the OR functionality.

Schematic Diagram:
NOR Gate Simulation Results:

The transient response of the NOR gate is shown in Figure below. The
simulation results match the expected truth table for a NOR gate. The
output is high (1) only when both inputs (A and B) are low (0). For all
other input combinations, the output is low (0).

Simulation Waveform:
OR Gate Simulation Results:

The OR gate was simulated using the NOR gate followed by an


inverter. The results, as shown in Figure below, confirm the correct
operation of the OR gate. The output is high (1) if either of the inputs
is high, which matches the truth table for the OR gate.

Simulation Waveform:
Conclusion:
In this project, we successfully designed and simulated NOR and OR
gates using NMOS and PMOS transistors in LTSpice. The NOR gate
was constructed using a series configuration of PMOS transistors and
a parallel configuration of NMOS transistors. The OR gate was derived
by inverting the output of the NOR gate.

The simulation results matched the expected behaviour based on the


truth tables, confirming that the design was correct. This project
demonstrates the effectiveness of CMOS technology in designing
low-power and high-performance digital logic gates.

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