SLM34x

5.0kVRMS Opto-Compatible Single Channel Isolated Gate Driver

GENERAL DESCRIPTION FEATURES
The SLM34x isolated driver family is an opto-  1.0A to 4.0A peak output current
compatible, single channel, isolated MOSFET, IGBT  120ns (Max.) propagation delay
gate driver with different drive current capability and  25ns (Max.) part-to-part delay matching
UVLO voltage level. The peak output currents are
 35ns (Max.) pulse width distortion
from 1.0A to 4.0A. Key features and characteristics
bring significant performance and reliability upgrades  150kV/us (Min.) common mode transient
over standard opto-coupler based gate drivers while immunity (CMTI)
maintaining pin-to-pin compatibility in both schematic  Wide gate drive supply voltage
and layout design. Performance highlights include
high common mode transient immunity (CMTI), low  10 V to 40 V for SLM345/6
propagation delay, and small pulse width distortion.  14 V to 40 V for SLM340/1/3
 30V reverse polarity voltage handling capability
The input stage is an emulated diode which means
on input stage
long term reliability and excellent aging
characteristics compared to traditional LEDs. It is  Pin to pin compatible to opto-coupler isolated
offered in a SOP6W package with ≥8.0mm creepage gate drivers
and clearance. A mold compound from material group  SOP6W package with ≥8.0mm creepage and
II which has a comparative tracking index clearance
(CTI) >400V. High performance and reliability of the  Junction temperature, TJ: –40°C to +150°C
SLM34x makes it ideal for use in all types of motor
 Safety certifications
drives, solar inverters, industrial power supplies, and
appliances.  5kVRMS isolation for 1 minute per UL 1577
 CQC certification per GB4943.1-2011
APPLICATION
 DIN VDE 0884-17: 2021-10
 AC and brushless DC motor drives
 Renewable energy inverters
 Industrial power supplies

137W ANODE VC C
ISOLATION

1 6
UVLO
VC C=15V
5V NC VOU T 10W
0V 2
e 2
5
0.1uF 1uF
BARRIER

CATHODE 10KW
137W VEE
3
2 4
2

137W ANODE VC C
ISOLATION

1 6
UVLO VC C=15V
5V 0.1uF 1uF
NC VOU T
2
e 2
5
10W
0V
BARRIER

10KW

137W CATHODE VEE VEE =-8V

1uF
3
2 4
2

Figure 1. SLM34x Single and Bipolar Power Supplies Application Circuit to Drive IGBT

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Rev1.2, Sep 2022
 SLM34x
Table of Contents
General Description ....................................................................................................................................................1
Application ..................................................................................................................................................................1
Features ......................................................................................................................................................................1
PIN Configuration........................................................................................................................................................3
PIN Description ...........................................................................................................................................................3
Functional Block Diagram ...........................................................................................................................................3
Ordering Information ...................................................................................................................................................4
Family Overiew ...........................................................................................................................................................4
Absolute Maximum Ratings ..........................................................................................................................................5
Recommended Opertion Conditions ..........................................................................................................................5
ESD Ratings ...............................................................................................................................................................5
Thermal Information ....................................................................................................................................................5
Package Specifications ...............................................................................................................................................6
Insulation Specifications .............................................................................................................................................6
Safety Related Certifications ......................................................................................................................................7
Safety Limiting Values ................................................................................................................................................7
Electrial Characteristics (DC) ......................................................................................................................................8
Switching Characteristics (AC) ...................................................................................................................................9
Parameter Measurement Information .......................................................................................................................10
Propagation Delay, Rise Time and Fall Time ....................................................................................................10
IOH and IOL Testing ..........................................................................................................................................10
CMTI Testing .....................................................................................................................................................10
Feature Description ..................................................................................................................................................11
Input Stage ........................................................................................................................................................11
Under Voltage Lockout (UVLO) .........................................................................................................................12
Typical Input Configuration Circuit ....................................................................................................................12
Layout ................................................................................................................................................................13
Package Case Outlines ............................................................................................................................................14
Reflow Profile Guidance ...........................................................................................................................................15
Revision History ........................................................................................................................................................16

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Rev1.2, Sep 2022
 SLM34x
PIN CONFIGURATION
Package Pin Configuration (Top View)

1 6
ANODE VCC
SOP6W 2 5
NC VOUT
3 4
CATHODE VEE

PIN DESCRIPTION
No. Pin Description

1 ANODE Anode
2 NC No Connection
3 CATHODE Cathode
4 VEE Negative Power Supply Rail
5 VOUT Gate Drive Output
6 VCC Positive Power Supply Rail

FUNCTIONAL BLOCK DIAGRAM

ISOLATION

ANODE 1 6 VCC
UVLO

e
NC 2 5
2 VOUT
BARRIER

CATHODE 3
2 4
2 VEE

Figure 2. SLM34x Functional Block Diagram

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Rev1.2, Sep 2022
 SLM34x
ORDERING INFORMATION
Order Part No. Package QTY
SLM340CK-DG SOP6W, Pb-Free 1000/Reel

SLM341CK-DG SOP6W, Pb-Free 1000/Reel

SLM343CK-DG SOP6W, Pb-Free 1000/Reel

SLM345CK-DG SOP6W, Pb-Free 1000/Reel

SLM346CK-DG SOP6W, Pb-Free 1000/Reel

FAMILY OVERIEW
Part Number Peak Output Current UVLO Isolation Rating

SLM340 1.0 A 12.5V 5.0kVrms

SLM341 3.0 A 12.5V 5.0kVrms

SLM343 4.0 A 12.5V 5.0kVrms

SLM345 1.0 A 8.5V 5.0kVrms

SLM346 3.0 A 8.5V 5.0kVrms

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 SLM34x
ABSOLUTE MAXIMUM RATINGS
Symbol Definition Min Max Unit
IF(AVG) Average Input Current 25 mA
VR Reverse Input Voltage 30 V
VCC -VEE Output supply voltage 45 V
TJ Junction temperature -40 150
°C
TS Storage temperature -55 150

RECOMMENDED OPERTION CONDITIONS

Symbol Definition Min Max Unit
Output Supply Voltage (SLM340/SLM341/ SLM343) 14 40 V
VCC -VEE
Output Supply Voltage (SLM345/SLM346) 10 40 V
IF(ON) Input Diode Forward Current (Diode “ON”) 7 16 mA
VF(OFF) Anode Voltage - Cathode Voltage (Diode “OFF”) -30 0.9 V
TJ Junction temperature -40 150 °C
TA Ambient temperature -40 125 °C

ESD RATINGS
Symbol Definition Value Unit
HBM 4000
VESD V
CDM 2000

THERMAL INFORMATION
Symbol Definition Value Unit
RθJA Junction to ambient thermal resistance 125 °C/W
RθJC Junction to case (top) thermal resistance 66 °C/W

ΨJT Junction to top characterization parameter 30 °C/W

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Rev1.2, Sep 2022
 SLM34x
PACKAGE SPECIFICATIONS
Symbol Definition Min Typ Max Units
RIO Resistance (Input Side to Output Side) 1012 W
CIO Capacitance (Input Side to Output Side) 0.8 pF
CIN Input Capacitance 30 pF

INSULATION SPECIFICATIONS
Symbol Definition Test Condition Value Units
Shortest terminal to terminal
CLR External clearance ≥8 mm
distance through air
Shortest terminal to terminal
CPG External creepage distance across the package ≥8 mm
surface
DTI Distance through the insulation Minimum internal gap >16 um
DIN EN 60112 (VDE 0303-11),
CTI Comparative tracking index >400 V
IEC 60112
Material Group II
Rated mains voltages 150Vrms IV
Rated mains voltages 300Vrms IV
Overvoltage category Rated mains voltages 600Vrms III
Rated mains voltages
II
1000Vrms
DIN V VDE 0884-11
Maximum repetitive peak isolation
VIORM 1414 VPK
voltage
VIOWM Maximum isolation working voltage 1000 VRMS
VIOTM Maximum transient isolation voltage 60s 7000 VPK
Test method per IEC62368,
VIOSM Maximum surge isolation voltage 1.2/50us waveform, VTEST=1.6 x 6250 VPK
VIOSM
Method b2: Vpd(m)=1.875 x VIORM,
qpd Apparent charge 5 pC
tm=1 s
Climatic Category 40/125/21
Pollution Degree 2
UL1577
VTEST=VISO, t=60s (qualification),
Withstand Isolation Voltage
VISO VTEST=1.2 x VISO, t=1s (100% 5000 VRMS
production)

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Rev1.2, Sep 2022
 SLM34x
SAFETY RELATED CERTIFICATIONS
VDE UL CQC
DIN VDE 0884-17: 2021-10 UL 1577 component recognition Certified according to
program
GB4943.1-2011
Reinforced Insulation Single protection, 5000 VRMS Reinforced insulation,
Altitude≤ 5000m, Tropical climate,
VIORM = 1414 VPK
400 VRMS maximum working voltage
VIOTM = 7000 VPK
VIOSM = 6250 VPK
Certification number: 40055782 File number: E521801 File number: CQC22001338757

SAFETY LIMITING VALUES

Symbol Parameter Condition Value Unit
RθJA=125°C/W, VCC-VEE = 15V, TJ
50 mA
Safety input, output, or supply =150°C, TA =25°C
IS
current RθJA=125°C/W, VCC-VEE = 30V, TJ
25 mA
=150°C, TA =25°C
Safety input, output, or total
PS RθJA=125°C/W, TJ =150°C, TA =25°C 750 mW
power
TS Maximum safety temperature 150 °C

60 800

700
Safety Limiting Current (mA)

50
Safety Limiting Power (mW)

VCC=15V
VCC=30V 600
40
500

30 400

300
20

200
10
100

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Ambient Temperature (oC) Ambient Temperature (oC)
Figure 3. Thermal Derating Curve for Limiting Current Figure 4. Thermal Derating Curve for Limiting Power
per VDE per VDE

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Rev1.2, Sep 2022
 SLM34x
ELECTRIAL CHARACTERISTICS (DC)
VCC-VEE = 15V, VEE = GND and TA = 25°C unless otherwise specified. All min and max specifications are at TA = -
40°C to 125°C

Symbol Parameter Condition Min Typ Max Unit

INPUT
Input Forward Threshold Current Low to
IFLH 1.8 2.1 3 mA
High

VF Input Forward Voltage IF=10mA 2.1 2.25 2.5 V

Temp Coefficient of Input Forward

VF/T IF=10mA 0.5 mV/°C
Voltage

VR Input Reverse Breakdown Voltage IR=10uA 30 V

OUTPUT(SLM340/SLM345)
VCC=15V, IF=10mA,
IOH High Level Peak Output Current CVDD=10uF, 1.0 A
CLOAD=220nF
VCC=15V, VF=0V,
IOL Low Level Peak Output Current CVDD=10uF, 1.0 A
CLOAD=220nF

IF=10mA, IO=-20mA
VOH High Level Output Voltage 105 mV
“With respect to Vcc”

VOL Low Level Output Voltage VF=0V, IO=20mA 50 mV

OUTPUT(SLM341/SLM346)
VCC=15V, IF=10mA,
IOH High Level Peak Output Current CVDD=10uF, 3.0 A
CLOAD=220nF
VCC=15V, VF=0V,
IOL Low Level Peak Output Current CVDD=10uF, 3.0 A
CLOAD=220nF
IF=10mA, IO=-20mA
VOH High Level Output Voltage 26 mV
“With respect to Vcc”

VOL Low Level Output Voltage VF=0V, IO=20mA 13 mV

OUTPUT(SLM343)
VCC=15V,IF=10mA,
IOH High Level Peak Output Current CVDD=10uF, 4.0 A
CLOAD=220nF
VCC=15V, VF=0V,
IOL Low Level Peak Output Current CVDD=10uF, 6.0 A
CLOAD=220nF
IF=10mA, IO=-20mA
VOH High Level Output Voltage 26 mV
“With respect to Vcc”
VOL Low Level Output Voltage VF=0V, IO=20mA 13 mV

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 SLM34x
Symbol Parameter Condition Min Typ Max Unit

UNDER VOLTAGE LOCKOUT(SLM340/SLM341/SLM343)

UVLOR Under Voltage Lockout VCC rising IF=10mA 11.5 12.5 13.5 V
UVLOF Under Voltage Lockout VCC falling IF=10mA 10.5 11.5 12.5 V
UVLOHYS Under Voltage Lockout Hysteresis 1.0 V
UNDER VOLTAGE LOCKOUT (SLM345/SLM346)
UVLOR Under Voltage Lockout VCC rising IF=10mA 8 8.5 9 V
UVLOF Under Voltage Lockout VCC falling IF=10mA 7 7.5 8 V
UVLOHYS Under Voltage Lockout Hysteresis 1.0 V

SWITCHING CHARACTERISTICS (AC)

VCC-VEE = 15V, VEE = GND and TA = 25°C unless otherwise specified. All min and max specifications are at TA = -
40°C to 125°C

Symbol Parameter Condition Min Typ Max Unit

tPLH Propagation delay, Low to High 90 120 ns

tPHL Propagation delay, High to Low 90 120 ns

CLOAD =1nF, fsw=20kHz,
tr Turn on rise time (50% Duty Cycle), 25 ns
VCC=15V
tf Turn off fall time 12 ns

tPWD Pulse Width Distortion 35 ns

Propagation Delay Difference

tPDD 25 ns
Between Any Two Parts

tUVLO_REC UVLO Recovery Delay VCC Rising from 0V to 15V 22 30 us

Output High Level Common Mode IF=10mA, VCM=1000V,

CMTIH 150 200 kV/us
Transient Immunity VCC=15V, TA=25°C
Output Low Level Common Mode VF=0V, VCM=1000V,
CMTIL 150 200 kV/us
Transient Immunity VCC=15V, TA=25°C

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Rev1.2, Sep 2022
 SLM34x
PARAMETER MEASUREMENT INFORMATION
Propagation Delay, Rise Time and Fall Time
Figure 5 shows the propagation delay from the input forward current I F,to VOUT. This figure also shows the circuit
used to measure the rise (tr)and fall(tf) times and the propagation delays tPDLH and tPDHL.

270W ANODE VC C

ISOLATION
1 6 50%
IF UVLO IF
NC VOU T tr tf
2
e BARRIER 2
5
1uF 15V

1nF 80%
CATHODE VEE 50%
3
2 4
2 VOUT 20%

tPDLH tPDHL

Figure 5. Propagation Delay, Rise Time and Fall Time

IOH and IOL Testing
Figure 6 shows the circuit used to measure the output drive current IOL and IOH. A load capacitance of 220nF is used
at the output. The peak dv/dt of the capacitor voltage is measured in order to determine the peak source and sink
currents of the gate driver.
270W ANODE VC C
ISOLATION

1 6
IF UVLO

NC VOU T IOH
2
e 2
5
1uF 15V

IOL 220nF
BARRIER

CATHODE VEE
3
2 4
2

Figure 6. IOH and IOL

CMTI Testing
Figure 7 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1000V. The test is performed
with IF=10mA (VOUT= High) and VF=0V (VOUT= Low).
137W ANODE VC C
ISOLATION

1 6
UVLO

NC VOU T 1uF
5V 2
e 2
5
15V

Battery
1nF
BARRIER

137W CATHODE VEE

3
2 4
2

VC M=1000V

Figure 7. CMTI Test Circuit

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Rev1.2, Sep 2022
 SLM34x
FEATURE DESCRIPTION
SLM34x is a single channel isolated gate driver, with an opto-compatible input stage, that can drive IGBTs and
MOSFETs. It has 1.0 A to 4.0A peak output current capability with maxim output driver supply voltage of 40V. The
inputs and the outputs are galvanically isolated. SLM34x is offered in SOP6W package with >8.5mm creepage and
clearance. The reinforced isolation rating is 5kVRMS for 60 seconds. It is pin-to-pin compatible with standard opto-
coupler isolated gate drivers. While standard opto-coupler isolated gate drivers use an LED as the input stage,
SLM34x uses an emulated diode as the input stage which does not use light emission to transmit signals across
the isolation barrier. The input stage is isolated from the driver stage by dual, series HV SiO2 capacitors in full
differential configuration that not only provides reinforced isolation but also offers great performance of common
mode transient immunity >150kV/us. The e-diode input stage along with capacitive isolation technology gives
SLM34x several performance advantages over standard opto-coupler isolated gate drivers.
 Since the emulated diode does not use light emission for its operation, the reliability and aging characteristics
of SLM34x are naturally superior to those of standard opto-coupler isolated gate drivers.
 Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto-coupler isolated
gate drivers
 The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.
Hence, the operating point of the input stage is more stable and predictable across different parts and operating
temperature
 Higher common mode transient immunity than opto-coupler isolated gate drivers
 Smaller propagation delay than opto-coupler isolated gate drivers
 Due to superior process controls achievable in capacitive isolation compared to opto-coupler isolation, there is
less part-to-part skew in the propagation delay, making the system design simpler and more robust
 Smaller pulse width distortion than opto-coupler isolated gate drivers
Input Stage
The input stage of SLM34x is an emulated diode. When the emulated diode is forward biased by applying a positive
voltage to the Anode with respect to the Cathode, a forward current, IF, flows into the e-diode. The forward voltage
drop across the e-diode is 2.25V (typ). An external resistor should be used to limit the forward current. The
recommended range for the forward current is 7mA to 16mA. When IF exceeds the input forward threshold current
IFLH (2.1mA typ), the VOUT is driver high. If the IF is lower than IFLH, or the voltage between Anode and Cathode is
reverse biased, the VOUT is driven low.
The reverse breakdown voltage of the e-diode is up to 30V. The large reverse breakdown voltage of the e-diode
enables SLM34x to be operated in interlock architecture as shown in Figure 8. The example shows two gate drivers
driving a set of IGBTs. The inputs of the gate drivers are connected as shown in Figure 8 and driven by two buffers
that are controlled by the MCU. Interlock architecture prevents both the e-diodes from being "ON" at the same time,
preventing shoot through in the IGBTs as shown in Figure 9. It also ensures that if both PWM signals are erroneously
stuck high (or low) simultaneously, both gate driver outputs will be driven low.
VD D
R1 ANODE VC C
HS_PWM
ISOLATION

HV
1 6
UVLO
VC C1

NC VOU T Rg1
2
e 2
5
CVC C1
BARRIER

VD D
CATHODE RPD 1
R2 VEE
LS_PWM
3
2 4
2

ANODE VC C
ISOLATION

1 6
UVLO VC C2

NC VOU T Rg2
2
e 2
5
CVC C2
BARRIER

CATHODE RPD 2
VEE
3
2 4
2

Figure 8. Interlock Architecture

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Rev1.2, Sep 2022
 SLM34x

CH1: HS_OUT, CH2: LS_OUT, CH3: HS_PWM, CH4: LS_PWM

Figure 9. Interlock PWM input and output waveform

Under Voltage Lockout (UVLO)
The SLM34x integrates the UVLO protection on the VCC to prevent an under driven condition on IGBTs and
MOSFETs. When VCC is lower than UVLOR during start up or lower than UVLOF after start up, the UVLO feature
holds the VOUT low, regardless of the input forward current. A hysteresis on the UVLO feature prevents glitch when
there is noise from the power supply. When VCC drops below UVLOF, a recovery delay (tUVLO_REC) occurs on the
output when the supply voltage rises above UVLOR again.
Typical Input Configuration Circuit
The circuit in Figure 10 and Figure 11 show two typical input configuration circuits for SLM34x to driver IGBT.
5V

137W
ANODE VC C
ISOLATION

1 6
UVLO
VC C=15V
NC VOU T 10W
2
e 2
5
1uF
BARRIER

CATHODE 10KW
VEE
3
2 4
2

137W

PWM

Figure 10. Single MOSFET Circuit as Input Drive of SLM34x to Drive IGBT
5V
137W ANODE VC C
PWM
ISOLATION

1 6
UVLO
VC C=15V
NC VOU T 10W
2
e 2
5
1uF
BARRIER

CATHODE 10KW
137W VEE
3
2 4
2

Figure 11. Buffer Circuit as Input Drive of SLM34x to Drive IGBT

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Rev1.2, Sep 2022
 SLM34x
Layout
In order to achieve optimum performance for the SLM34x, some suggestions on PCB layout.
Component placement:
 Low ESR and low ESL capacitors must be connected close to the device between the VCC and VEE pins to bypass
noise and to support high peak currents when turning on the external power transistor.
 To avoid large negative transients on the VEE pins connected to the switch node, the parasitic inductances
between the source of the top transistor and the source of the bottom transistor must be minimized.
Grounding considerations:
 Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area is
essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
High-voltage considerations:
 To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the driver device. A PCB cutout or groove is recommended in order to prevent contamination that
may compromise the isolation performance.

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 SLM34x
PACKAGE CASE OUTLINES

Figure 12. SOP6W Package Outline Dimensions

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Rev1.2, Sep 2022
 SLM34x
REFLOW PROFILE GUIDANCE

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Rev1.2, Sep 2022
 SLM34x
REVISION HISTORY
Note: page numbers for previous revisions may differ from page numbers in current version
Page or Item Subjects (major changes since previous revision)
Rev 1.0 datasheet: 2022-1-5
Whole document Initial release
Rev 1.1 datasheet: 2022-3-25
Page 5 Add thermal information
Page 6 Add the test condition in the Insulation specifications
Page 7 Add safety related certifications
Add safety limiting values
Rev 1.2 datasheet: 2022-9-25
Page 6 Update the specification values in the insulation specifications
Page 7 Update the VDE certification file number

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Rev1.2, Sep 2022