II B.

TECH I SEM- ECE – ELECTRONIC DEVICES & CIRCUITS UNIT-III

MOSFET as an Amplifier:

As we know, the Enhancement MOSFETS, or E-MOSFETS, only conduct when a suitable

gate-to-source positive voltage is applied, unlike Depletion type MOSFETs which conduct
only when the gate voltage is zero.
However, due to the construction and physics of an enhancement type MOSFET, there
is a minimum gate-to-source voltage, called the threshold voltage VTh that must be applied to
the gate before it starts to conduct, thus allowing the drain current to flow.
In other words, an E-MOSFET does not conduct until the gate-source voltage,VGS is less
than the threshold voltage, VTh. But as the forward bias at the gate increases, the drain current,
ID (or drain-source current, IDS) will also increase, making the E-MOSFET ideal for use in
MOSFET amplifier circuits. Let’s consider the basic E-MOSFET amplifier circuit below.

This simple enhancement-mode common source MOSFET amplifier configuration uses a

single supply at the drain and generates the required gate voltage, VG using a resistor divider.
As we know that for a MOSFET, no current flows into the gate terminal, we can make the
following basic assumptions about the MOSFET amplifiers DC operating conditions.

Then from this we can say that:

and

and the MOSFET gate-to-source voltage, VGS is given as:

For proper operation of the MOSFET, this gate-source voltage must be greater than the threshold
voltage of the MOSFET, that is VGS > VTH.
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Since IS = ID, the gate voltage, VG is therefore equal too:

To set the MOSFET amplifier gate voltage to this value we select the values of the
resistors, R1 and R2 within the voltage divider network to the required values. Since, no
current flows into the gate terminal of a MOSFET device so the formula for voltage
division is given as:

It can be noted that, this voltage divider equation only determines the ratio of the two
biasresistors, R1 and R2 and not their actual values.
It is always desirable to make the values of these two resistors as large as possible to
reduce their I2R power loss and increase the MOSFETs amplifiers input resistance.

MOSFET as a switch:

MOSFETs exhibit three regions of operation viz., Cut-off, Linear or Ohmic and Saturation.
Among these, when MOSFETs are to be used as amplifiers, they are required to be operated
in their ohmic region wherein the current through the device increases with an increase in the
applied voltage.
On the other hand, when the MOSFETs are required to function as switches, they should
be biased in such a way that they alter between cut-off and saturation states. This is because,
in cut-off region, there is no current flow through the device while in saturation region there
will be a constant amount of current flowing through the device, just mimicking the behaviour
of an open and closed switch, respectively.
Figure 1 shows a simple circuit which uses an n-channel enhancement MOSFET
as a switch. Here the drain terminal (D) of the MOSFET is connected to the supply voltage
VS via the drain resistor RD while its source terminal (S) is grounded. Further, it has an
input voltage Vi applied at its gate terminal (G) while the output Vo is drawn from its drain.

Figure 1: n-Channel Enhancement-type MOSFET Functioning as a Switch

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Now consider the case where Vi applied is 0V, which means the gate terminal of the
MOSFET is left unbiased. As a result, the MOSFET will be OFF and operates in its cutoff
region wherein it offers a high impedance path to the flow of current which makes the IDS
almost equivalent to zero. As a result, even the voltage drop across RD will become zero
due to which the output voltage Vo will become almost equal to VS.
Next, consider the case where the input voltage Vi applied is greater than the threshold
voltage VT of the device. Under this condition, the MOSFET will start to conduct and if the
VS provided is greater than the pinch-off voltage VP of the device, then the MOSFET starts
to operate in its saturation region. This further means that the device will offer low
resistance path for the flow of constant IDS, almost acting like a short circuit. As a result, the
output voltage will be pulled towards low voltage level, which will be ideally zero.
It is evident that the output voltage alters between VS and zero depending on whether
the input provided is less than or greater than VT, respectively. Thus, it can be concluded that
MOSFETs can be made to function as electronic switches when made to operate between cut-
off and saturation operating regions.
Similar to the case of n-channel enhancement type MOSFET, even n-channel depletion
type MOSFETs can be used to perform switching action as shownby Figure 2. The behaviour
of such a circuit is seen to be almost identical to that explained above except the fact that for
cut-off, the gate voltage VG needs to be made negative and should be lesser than -VT.

Figure 2: n-Channel Depletion-type MOSFET Functioning as a Switch

Similar to n-channel MOSFETs, even p-channel enhancement-type and depletion-type

MOSFETs can be used to perform switching action.
The table presented below summarizes the switching conditions of n-channel and
p-channel MOSFETs.

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Biasing in MOS Amplifier Circuits:

An essential step in the design of a MOSFET amplifier circuit is the establishment of an
appropriate dc operating point for the transistor. This is the step known as biasing or bias design.
An appropriate dc operating point or bias point is characterized by a stable and predictable dc
drain current ID and by a dc drain-to-source voltage VDS that ensures operation in the saturation
region for all expected input-signal levels.

Biasing by Fixing VGS:

The most straightforward approach to biasing a MOSFET is to fix its gate-to-source voltage VGS
to the value required to provide the desired ID. This voltage value can be derived from the power-
supply voltage VDD through the use of an appropriate voltage divider. Alternatively, it can be
derived from another suitable reference voltage that might be available in the system.
Independent of how the voltage VGS may be generated, this is not a good approach to biasing a
MOSFET. To understand the reason for this statement, recall that

and note that the values of the threshold voltage Vt, the oxide-capacitance Cox, and the transistor
aspect ratio W/L vary widely among devices of supposedly the same size and type.
To emphasize the point that biasing by fixing VGS is not a good technique, two iD–vGS
characteristic curves representing extreme values in a batch of MOSFETs of the same type is
shown in Figure 1. Observe that for the fixed value of VGS, the resultant spread in the values of
the drain current can be substantial.

Figure 1: The use of fixed bias (constant VGS) can result in a large variability in the value of ID.
Devices 1 and 2 represent extremes among units of the same type.
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Biasing by Fixing VG and Connecting a Resistance in the Source:

An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc voltage
at the gate, VG, and connecting a resistance in the source lead, as shown in Figure 2(a).

Figure 2: Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS:
(a) basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single
supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical
implementation using two supplies.

For this circuit we can write

Now, if VG is much greater than VGS, ID will be mostly determined by the values of VG
and RS. However, even if VG is not much larger than VGS, resistor RS provides negative
feedback, which acts to stabilize the value of the bias current ID.
Equation (1) indicates that since VG is constant, VGS will have to decrease. This in turn
results in a decrease in ID, a change that is opposite to that initially assumed. Thus, the action of
RS works to keep ID as constant as possible. This negative feedback action of RS gives it the
name degeneration resistance.

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Figure 2(b) provides a graphical illustration of the effectiveness of this biasing scheme.
Here the iD–vGS characteristics for two devices that represent the extremes of a batch of
MOSFETs is shown. Superimposed on the device characteristics is a straight line that represents
the constraint imposed by the bias circuit—namely, Eq. (1). The intersection of this straight line
with the iD–vGS characteristic curve provides the coordinates (ID and VGS) of the bias point.
Observe that compared to the case of fixed VGS, here the variability obtained in ID is much
smaller. Also, note that the variability decreases as VG and RS are made larger.
Two possible practical discrete implementations of this bias scheme are shown in Figure
2(c) and 2(e). The circuit in Figure 2(c) utilizes one power-supply VDD and derives VG through a
voltage divider (RG1, RG2). Since IG = 0, RG1 and RG2 can be selected to be very large (in the
megaohm range), allowing the MOSFET to present a large input resistance to a signal source
that may be connected to the gate through a coupling capacitor, as shown in Figure 2(d). Here
capacitor CC1 blocks dc and thus allows us to couple the signal vsig to the amplifier input without
disturbing the MOSFET dc bias point. The value of CC1 should be selected large enough to
approximate a short circuit at all signal frequencies of interest. Finally, note that in the circuit of
Figure 2(c), resistor RD is selected to be as large as possible to obtain high gain but small enough
to allow for the desired signal swing at the drain while keeping the MOSFET in saturation at all
times.
When two power supplies are available, as is often the case, the somewhat simpler bias
arrangement of Figure 2(e) can be utilized. This circuit is an implementation of Eq. (1), with VG
replaced by VSS. Resistor RG establishes a dc ground at the gate and presents a high input
resistance to a signal source that may be connected to the gate through a coupling capacitor.

Problem:
Design the circuit of below Figure to establish a dc drain current ID = 0.5 mA. The MOSFET is
specified to have Vt = 1 V and kn′W/L = 1 mA/V2. For simplicity, neglect the channel-length
modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15 V. Calculate the percentage
change in the value of ID obtained when the MOSFET is replaced with another unit having the
same Solution kn′W/L but Vt = 1.5 V.

Solution:
As a rule of thumb for designing this classical biasing circuit, we choose R D and RS to provide
one-third of the power-supply voltage VDD as a drop across each of RD, the transistor (i.e., VDS)
and RS. For VDD = 15 V, this choice makes VD = +10 V and VS = +5 V. Now, since ID is required
to be 0.5 mA, we can find the values of RD and RS as follows:

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The required value of VGS can be determined by first calculating the overdrive voltage VOV from

which yields VOV = 1 V, and thus,

Now, since VS = +5 V, VG must be

To establish this voltage at the gate we may select RG1 = 8 MΩ and RG2 = 7 MΩ. The final
circuit is shown in Figure 3. Observe that the dc voltage at the drain (+10 V) allows for a
positive signal swing of +5 V (i.e., up to VDD) and a negative signal swing of –4 V [i.e., down to
(VG – Vt)].

Figure 3: Circuit for Example

If the NMOS transistor is replaced with another having Vt = 1.5 V, the new value of ID can be
found as follows:

Solving Eqs. (1) and (2) together yields

ID = 0.455 mA
Thus the change in ID is

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 II B.TECH I SEM- ECE – ELECTRONIC DEVICES & CIRCUITS UNIT-III

Biasing Using a Drain-to-Gate Feedback Resistor:

A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor

connected between the drain and the gate is shown in Figure 4.

Figure 4: Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

Here the large feedback resistance RG (usually in the megaohm range) forces the dc
voltage at the gate to be equal to that at the drain (because IG = 0). Thus we can write

which can be rewritten in the form

which is identical in form to Eq. (1).

Thus, if ID for some reason changes, say increases, then Eq. (2) indicates that VGS must
decrease. The decrease in VGS in turn causes a decrease in ID, a change that is opposite in
direction to the one originally assumed. Thus the negative feedback or degeneration provided by
RG works to keep the value of ID as constant as possible.

The circuit of Figure 4 can be utilized as an amplifier by applying the input voltage signal
to the gate via a coupling capacitor so as not to disturb the dc bias conditions already established.
The amplified output signal at the drain can be coupled to another part of the circuit, again via a
capacitor.

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Biasing Using a Constant-Current Source:

The most effective scheme for biasing a MOSFET amplifier is that using a constant-current
source. Figure 5(a) shows such an arrangement applied to a discrete MOSFET.

Figure 5: (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of
the constant-current source I using a current mirror.

Here RG (usually in the megaohm range) establishes a dc ground at the gate and presents
a large resistance to an input signal source that can be capacitively coupled to the gate. Resistor
RD establishes an appropriate dc voltage at the drain to allow for the required output signal swing
while ensuring that the transistor always remains in the saturation region.

A circuit for implementing the constant-current source I is shown in Figure 5(b). The
heart of the circuit is transistor Q1, whose drain is shorted to its gate, and thus is operating in the
saturation region, such that

where we have neglected channel-length modulation (i.e., assumed λ = 0).

The drain current of Q1 is supplied by VDD through resistor R. Since the gate currents are
zero,

where the current through R is considered to be the reference current of the current source and is
denoted IREF.

Given the parameter values of Q1 and a desired value for IREF, Eqs. (1) and (2) can be
used to determine the value of R. Now consider transistor Q2: It has the same VGS as Q1; thus if
we assume that it is operating in saturation, its drain current, which is the desired current I of the
current source, will be
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where we have neglected channel-length modulation. Equations (2) and (3) enable us to relate the
current I to the reference current IREF,

Thus, I is related to IREF by the ratio of the aspect ratios of Q1 and Q2. This circuit, known as a
current mirror, is very popular in the design of IC MOS amplifiers.

The Body Effect:

In many applications the source terminal is connected to the substrate (or body) terminal B,
which results in the pn junction between the substrate and the induced channel having a constant
zero (cutoff) bias. In such a case the substrate does not play any role in circuit operation and its
existence can be ignored altogether.

In integrated circuits, however, the substrate is usually common to many MOS transistors. In
order to maintain the cutoff condition for all the substrate-to-channel junctions, the substrate is
usually connected to the most negative power supply in an NMOS circuit (the most positive in a
PMOS circuit). The resulting reverse-bias voltage between source and body (VSB in an n-channel
device) will have an effect on device operation. To appreciate this fact, consider an NMOS
transistor and let its substrate be made negative relative to the source. The reverse-bias voltage
will widen the depletion region. This in turn reduces the channel depth. To return the channel to
its former state, vGS has to be increased.

The effect of VSB on the channel can be most conveniently represented as a change in the
threshold voltage Vt. Specifically, it has been shown that increasing the reverse substrate bias
voltage VSB results in an increase in Vt according to the relationship

where Vt0 is the threshold voltage for VSB = 0; φf is a physical parameter with (2φf) typically 0.6
V; γ is a fabrication-process parameter given by

where q is the electron charge (1.6 × 10−19 C), NA is the doping concentration of the p-type
substrate, and εs is the permittivity of silicon (11.7ε0 = 11.7 × 8.854 × 10−14 = 1.04 × 10−12 F/cm).
The parameter γ has the dimension of √𝑉and is typically 0.4 V1/2. Finally, note that Eq. (1)
applies equally well for p-channel devices with VSB replaced by the reverse bias of the substrate,
VBS (or, alternatively, replace VSB by ǀVSBǀ) and note that γ is negative. Also, in evaluating γ, NA
must be replaced with ND, the doping concentration of the n well in which the PMOS is formed.
For p-channel devices, 2φf is typically 0.75 V, and γ is typically −0.5 V1/2.

Equation (1) indicates that an incremental change in VSB gives rise to an incremental change in
Vt, which in turn results in an incremental change in iD even though vGS might have been kept
constant. It follows that the body voltage controls iD; thus the body acts as another gate for the
MOSFET, a phenomenon known as the body effect. Here we note that the parameter γ is known
as the body-effect parameter.
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Modeling the Body Effect:

The body effect occurs in a MOSFET when the source is not tied to the substrate. Thus the
substrate (body) will be at signal ground, but since the source is not, a signal voltage vBS
develops between the body (B) and the source (S). The substrate then acts as a “second gate” or
a backgate for the MOSFET. Thus the signal vBS gives rise to a drain-current component, which
we shall write as gmbvBS, where gmb is the body transconductance, defined as

Recalling that iD depends on vBS through the dependence of Vt on VBS, we can show that

where

Typically the value of χ lies in the range 0.1 to 0.3.

Figure 1 shows the MOSFET model augmented to include the controlled source gmbvBS that
models the body effect. Ideally, this is the model to be used whenever the source is not
connected to the substrate.

Figure 1: Small-signal, equivalent-circuit model of a MOSFET in which the source is not

connected to the body.

Finally, although the analysis above was performed on a NMOS transistor, the results and the
equivalent circuit of Figure 1 apply equally well to PMOS transistors.

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