Homework 1
Homework 1
Homework 1
Structural Modeling of VHDL
Student Name:…………………………………لجين كمال عبيدة..
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX8to1_whenelse is
Port ( sel : in STD_LOGIC_VECTOR(2 downto 0); -- 3-bit selector
d : in STD_LOGIC_VECTOR(7 downto 0); -- 8 data inputs
y : out STD_LOGIC); -- output
end MUX8to1_whenelse;
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Figure 3 Flow Summary
RTL Viewer:
2
Simulation Results: (It could be more than one Figure)
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX8to1_selectwith is
Port ( sel : in STD_LOGIC_VECTOR(2 downto 0); -- 3-bit selector
d : in STD_LOGIC_VECTOR(7 downto 0); -- 8 data inputs
y : out STD_LOGIC); -- output
end MUX8to1_selectwith;
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d(2) when "010",
d(3) when "011",
d(4) when "100",
d(5) when "101",
d(6) when "110",
d(7) when others;
end dataflow;
RTL Viewer:
4
Simulation Results: (It could be more than one Figure)
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX4to1 is
Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end MUX4to1;
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
entity MUX8to1_component is
Port ( D : in STD_LOGIC_VECTOR(7 downto 0);
S : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC);
end MUX8to1_component;
component MUX4to1
Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end component;
begin
U1: MUX4to1 Port Map ( D => D(3 downto 0), S => S(1 downto 0), Y => Y0);
U2: MUX4to1 Port Map ( D => D(7 downto 4), S => S(1 downto 0), Y => Y1);
end Behavioral;
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RTL Viewer:
Conclusion
Total Logic 5 5 5
element
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RTLView
Conclusion
Based on the comparison of the three implementations of an 8-to-1 MUX in terms of propagation
delay, total logic elements, and RTL view, we can conclude the following:
1. Propagation Delay:
o All three implementations (using when-else, select-with, and a 4-to-1 MUX as a
component) have the same propagation delay of 11.568 ns. This indicates that,
regardless of the approach used, the delay in selecting the output remains constant.
2. Total Logic Elements:
o Each implementation also uses a total of 5 logic elements. This suggests that all three
methods are equally efficient in terms of resource utilization within the FPGA or
digital circuit environment.
3. RTL View:
o While the propagation delay and logic elements are the same, the RTL (Register
Transfer Level) view differs slightly between the methods. The when-else and
select-with approaches result in a straightforward RTL representation. In contrast,
the implementation using 4-to-1 MUX components is slightly more complex in
structure, as it involves using smaller MUXs to construct the 8-to-1 MUX.
Final Recommendation:
library ieee;
use ieee.std_logic_1164.all;
entity An16to1MUX is
port (
s: in std_logic_vector(3 downto 0);
8
x: in std_logic_vector(15 downto 0);
f: out std_logic
);
end An16to1MUX;