0% found this document useful (0 votes)
9 views9 pages

Homework 1

Uploaded by

amnamohamed886
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
9 views9 pages

Homework 1

Uploaded by

amnamohamed886
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

EC383L Fall 2024

Homework 1
Structural Modeling of VHDL
Student Name:…‫………………………………لجين كمال عبيدة‬..

1. VHDL code to design 8 to 1 MUX using when–else

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX8to1_whenelse is
Port ( sel : in STD_LOGIC_VECTOR(2 downto 0); -- 3-bit selector
d : in STD_LOGIC_VECTOR(7 downto 0); -- 8 data inputs
y : out STD_LOGIC); -- output
end MUX8to1_whenelse;

architecture dataflow of MUX8to1_whenelse is


begin
y<=d(0) when (sel = "000") else
d(1) when (sel = "001") else
d(2) when (sel = "010") else
d(3) when (sel = "011") else
d(4) when (sel = "100") else
d(5) when (sel = "101") else
d(6) when (sel = "110") else
d(7);
end dataflow ;

Compilation Report (Flow Summary)

1
Figure 3 Flow Summary

RTL Viewer:

Figure 4 RTL Viewer

2
Simulation Results: (It could be more than one Figure)

Figure 5 Simulation Results

2. VHDL code to design 8 to 1 MUX using select–with

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX8to1_selectwith is
Port ( sel : in STD_LOGIC_VECTOR(2 downto 0); -- 3-bit selector
d : in STD_LOGIC_VECTOR(7 downto 0); -- 8 data inputs
y : out STD_LOGIC); -- output
end MUX8to1_selectwith;

architecture dataflow of MUX8to1_selectwith is


begin
with sel select
y <= d(0) when "000",
d(1) when "001",

3
d(2) when "010",
d(3) when "011",
d(4) when "100",
d(5) when "101",
d(6) when "110",
d(7) when others;
end dataflow;

Compilation Report (Flow Summary)

Figure 3 Flow Summary

RTL Viewer:

Figure 4 RTL Viewer

4
Simulation Results: (It could be more than one Figure)

Figure 5 Simulation Results

2. VHDL code to design 8 to 1 MUX using 4to1MUX

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX4to1 is
Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end MUX4to1;

architecture Behavioral of MUX4to1 is


begin
end Behavioral;

library IEEE;

5
use IEEE.STD_LOGIC_1164.ALL;

entity MUX8to1_component is
Port ( D : in STD_LOGIC_VECTOR(7 downto 0);
S : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC);
end MUX8to1_component;

architecture Behavioral of MUX8to1_component is

component MUX4to1
Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end component;

signal Y0, Y1 : STD_LOGIC;

begin
U1: MUX4to1 Port Map ( D => D(3 downto 0), S => S(1 downto 0), Y => Y0);
U2: MUX4to1 Port Map ( D => D(7 downto 4), S => S(1 downto 0), Y => Y1);

Y <= Y0 when S(2) = '0' else Y1;

end Behavioral;

Compilation Report (Flow Summary)

Figure 3 Flow Summary

6
RTL Viewer:

Figure 4 RTL Viewer

Simulation Results: (It could be more than one Figure)

Conclusion

when–else select–with 4to1MUX


Propagation 11.568 11.568 11.753
delay

Total Logic 5 5 5
element

7
RTLView

Conclusion

Based on the comparison of the three implementations of an 8-to-1 MUX in terms of propagation
delay, total logic elements, and RTL view, we can conclude the following:

1. Propagation Delay:
o All three implementations (using when-else, select-with, and a 4-to-1 MUX as a
component) have the same propagation delay of 11.568 ns. This indicates that,
regardless of the approach used, the delay in selecting the output remains constant.
2. Total Logic Elements:
o Each implementation also uses a total of 5 logic elements. This suggests that all three
methods are equally efficient in terms of resource utilization within the FPGA or
digital circuit environment.
3. RTL View:
o While the propagation delay and logic elements are the same, the RTL (Register
Transfer Level) view differs slightly between the methods. The when-else and
select-with approaches result in a straightforward RTL representation. In contrast,
the implementation using 4-to-1 MUX components is slightly more complex in
structure, as it involves using smaller MUXs to construct the 8-to-1 MUX.

Final Recommendation:

If simplicity in design is a priority, the when-else or select-with methods may be preferred, as


they provide a more direct RTL representation. However, if modular design or reusability is
essential, the component-based (4-to-1 MUX) approach could be beneficial despite the slightly
more complex RTL view. Overall, since all approaches yield similar performance and resource
usage, the choice of implementation can be based on design preferences or specific project
requirements.

VHDL code to design 16 to 1 MUX using 8 to 1 MUX that designed in part a

library ieee;
use ieee.std_logic_1164.all;
entity An16to1MUX is
port (
s: in std_logic_vector(3 downto 0);

8
x: in std_logic_vector(15 downto 0);
f: out std_logic
);
end An16to1MUX;

architecture prototype of An16to1MUX is


component MUX8to1_whenelse
port (
s: in std_logic_vector(2 downto 0);
x: in std_logic_vector(7 downto 0);
f: out std_logic
);
end component;
signal c1, c2: std_logic;
begin
bit0: MUX8to1_whenelse
port map (
s(0) => s(0), s(1) => s(1), s(2) => s(2),
x(0) => x(0), x(1) => x(1), x(2) => x(2), x(3) => x(3),
x(4) => x(4), x(5) => x(5), x(6) => x(6), x(7) => x(7),
f => c1
);
bit1: MUX8to1_whenelse
port map (
s(0) => s(0), s(1) => s(1), s(2) => s(2),
x(0) => x(8), x(1) => x(9), x(2) => x(10), x(3) => x(11),
x(4) => x(12), x(5) => x(13), x(6) => x(14), x(7) => x(15),
f => c2
);
f <= (c1 and not s(3)) or (c2 and s(3));
end prototype;

You might also like