Digital System Design – EC661

M.Tech - VLSI SYSTEM

Dr. SRINIVASULU JOGI

Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHONOLOGY TIRUCHIRAPPALLI
TIRUCHIRAPPALLI-620015
 Digital System Design-EC661

Course Content
⚫ Mapping algorithms into Architectures: Data path synthesis, control structures,
critical path and worst case timing analysis. FSM and Hazards.

⚫ Combinational network delay. Power and energy optimization in combinational

logic circuit. Sequential machine design styles. Rules for clocking. Performance
analysis.

⚫ Sequencing static circuits. Circuit design of latches and flip-flops. Static

sequencing element methodology. Sequencing dynamic circuits. Synchronizers.

⚫ Data path and array subsystems: Addition / Subtraction, Comparators, counters,

coding, multiplication and division. SRAM, DRAM, ROM, serial access memory,
context addressable memory.

⚫ Reconfigurable Computing- Fine grain and Coarse grain architectures,

Configuration architectures-Single context, Multi context, partially reconfigurable,
Pipeline reconfigurable, Block Configurable, Parallel processing.
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Assessment Methodology

 Module 1-Mapping algorithms into architectures

Moore’s Law

⚫ Prediction of number of transistors per chip would grow

exponentially

⚫ Exponential improvement in technology is a natural trend.

 Module 1-Mapping algorithms into architectures

Products

⚫ Processors-CPU, DSP, Controllers

⚫ Memory Chips-RAM, ROM, EPROM

⚫ Programmable- PLA, FPGA

⚫ Embedded Systems-cars, factories

⚫ System on Chip-SoC
 Module 1-Mapping algorithms into architectures

Market Pressures

⚫ Design window reduction

⚫ Less tolerance for design revisions

 Module 1-Mapping algorithms into architectures

Design Specifications
⚫ Design Considerations
⚫ Design Feasibility

⚫ Performance

⚫ Power consumption

⚫ Cost

⚫ Design Spec.
⚫ Written

⚫ Executable

⚫ Implementation platform
⚫ FPGA

⚫ ASIC

⚫ Development Time
 Module 1-Mapping algorithms into architectures

RTL Specification

⚫ Determine I/O Signals

⚫ Standard Interface, protocol

⚫ Partition design into functional blocks

⚫ Datapath, control logic, memory, etc.

⚫ Determine block interfaces

⚫ Specify each block separately at RTL

⚫ MUXs, counters, adders, etc.
 Module 1-Mapping algorithms into architectures

Functional Simulation

⚫ Preparation for simulation

⚫ Generate simulation patterns

⚫ Waveform entry, HDL testbench

⚫ Functional Simulation
⚫ To verify the functionality of your design.

⚫ Simulation results
⚫ Waveform display

⚫ Text output
 Module 1-Mapping algorithms into architectures

HDL Synthesis
⚫ Synthesis=Translation+Optimization
⚫ Translate HDL design files into gate level netlist

⚫ Optimize according to your design constraints

⚫ Area constraints

⚫ Timing constraints

⚫ Power constraints

⚫ Main Challenges
⚫ Learn synthesizable coding style.

⚫ Use proper design partitioning for synthesis

⚫ Reasonable design constraints

⚫ Use HDL synthesis tools efficiently

 Module 1-Mapping algorithms into architectures

Timing Simulation

⚫ Post-layout simulation

⚫ Includes component and wire delays, clock skews, setup and hold
times

⚫ Same input vectors with functional simulation

⚫ Not necessary if STA shows no problem.

 Module 1-Mapping algorithms into architectures

Example-Half Adder
⚫ A combinational logic circuit which is designed to add two binary
digits is called as a half adder.
Truth Table
 Module 1-Mapping algorithms into architectures

Example-Half Adder
⚫ A combinational logic circuit which is designed to add two binary
digits is called as a half adder.
K-Map
 Module 1-Mapping algorithms into architectures

Example-Half Adder
⚫ A combinational logic circuit which is designed to add two binary
digits is called as a half adder.
Architecture
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Design Cycle
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Design Cycle
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Data Path Synthesis

⚫ In complex digital systems, the hardware is typically partitioned into two
parts:

⚫ Data Path: which consists of functional units where all the comutations are
carried out.
⚫ Typically consists of registers, multiplexers, bus, adders, multipliers, and

other functional blocks

⚫ Control Path: which implements a finite state machine and provides control
sinals to the data path in proper sequence.
⚫ In response to the control signals, various operations are carried out by the

data path
⚫ Also takes inputs from the data path regarding various status information.
 Module 1-Mapping algorithms into architectures

Data Path Synthesis B C

Let A, B, C, D reg[15:0] D
A
T
A=B+C + A
D=A-C P
A
Ld A A T
Ld A
S1 H

Ld D D
Ld D
S2
Control path
 Module 1-Mapping algorithms into architectures

Data Path Synthesis

Example: Consider a simple algorithm using repeated addition

START
⚫ Identify the functional blocks
required in the data path and
the corresponding control
READ A, B
signals

⚫ Design the FSM to implement

P=0
the multiplication algorithm
using data path
P=P+A
No

B=B-1 B=0 yes STOP

 Module 1-Mapping algorithms into architectures

Data Path Synthesis

 Module 1-Mapping algorithms into architectures

Data Path Synthesis

 Module 1-Mapping algorithms into architectures

Data Path Synthesis

 Module 1-Mapping algorithms into architectures

Data Path Synthesis

 Module 1-Mapping algorithms into architectures

Data Path Synthesis

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Data Path Synthesis

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Data Path Synthesis

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Control Structures
⚫ Program Logic need not run sequentially

⚫ Control structures takes decisions about program flow based on

given parameters

⚫ Control structures must be identified before any coding begins

⚫ Algorithms and pseudocodes help in identifying where control

structures are required

⚫ Three types
⚫ Decision control

⚫ Selection control

⚫ Loop/repetition control
 Module 1-Mapping algorithms into architectures

Control Structures
⚫ Decision control
⚫ Used when the next step to be executed depends upon a criteria

⚫ This criteria is usually one or more boolean expressions that must

be evaluated
⚫ For example, “if” statement

• Selection control
⚫ Used when program sequence depends upon the answer to a

specific question
⚫ For example, “switch”, “case” statements

⚫ Loop control

⚫ Used when a set of statements to be repeated many times

⚫ No. of repetitions may or may not be known beforehand

⚫ For example, “for” statement, “while” statement, “do while”

statement, etc
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Control Structures
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Control Structures-conditional statements

⚫ If else is a conditional statement where statements are evaluated
based on condition

⚫ Type-1: If (<expression>)
⚫ statement; //no else

⚫ Type-2: If (<expression>)
statement;
else
statement;

⚫ Type-3: nested if else..if

 Module 1-Mapping algorithms into architectures

Control Structures-IF statements-example

⚫ If(a) begin
⚫ Y<=x1;
⚫ elsif (b)
⚫ Y<=x2;
⚫ elsif (c)
⚫ Y<=x3;
⚫ else
⚫ Y<=x4;
⚫ end
 Module 1-Mapping algorithms into architectures
Control Structures-IF statements-example
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Control Structures-case statements-example
⚫ Case statement checks if the given expression matches the other
⚫ expression in the list. If many conditions are there then “if-else”
statement may not be suitable.

⚫ Case (something)
⚫ value: do something when something==value

⚫ othervalue:do something when something==othervalue

⚫ default: do something when something is none of the above

⚫ endcase
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Control Structures-case statements-example

⚫
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Control Structures-for statements-example

⚫ Syntax
⚫

⚫ for (var=0; var<value; var=var+1)

⚫ begin

⚫ //statement

⚫ end

⚫ Example: for (i=0; i<4; i=i+1)

⚫ begin

⚫ mem [i]=i;

⚫ end
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Control Structures-while statements-example

⚫ Syntax
⚫ while (condition)
⚫ begin
⚫ //statement
⚫ end
⚫ Example: integer count
⚫ initial begin

⚫ count=0;

⚫ end

⚫ while (count<128)

⚫ begin

⚫ $display(“count=%d”,count);

⚫ count=count+1;

⚫ end
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Control Structures-while statements-example

⚫ Example: module clockgen (clock);
⚫ ⚫ output reg clock;

⚫ initial

⚫ begin

⚫ clock=1’b0;

⚫ while (1)

⚫ begin

⚫ #5 clock=~clock;

⚫ end

⚫ end

⚫ end module
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Critical Path:
⚫ It is the path between an input and an output with maximum delay

⚫ It is also the longest path in the circuit that limits the clock speed.

⚫ Any further delays in the path slows down the entire operation of

the design
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Timing Analysis:
⚫ Measuring the speed of the circuit, i.e. clock

⚫ Estimation of critical delay.

⚫ Slack determination

⚫ Critical path identification

⚫ Timing Analysis Goals:

⚫ The main aspects of timing analysis is to ensure that

⚫ The circuit meets the timing specifications

⚫ There are no functional violations due to timing error

 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Worst Case Timing Analysis:
⚫ In order to identify the worst delay, we need to define:

⚫ Arrival Time at a node (AT)

⚫ Required Arrival Time at node (RAT)

⚫ Arrival Time at a node (AT): The longest path from source to node.
Ats at each node can be computed using the below expression.

⚫ Where FI(v) is the fan-in nodes, and t(u,v) is the delay between u
and v
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Worst Case Timing Analysis:
⚫ In order to identify the worst delay, we need to define:

⚫ Arrival Time at a node (AT)

⚫ Required Arrival Time at node (RAT)

⚫ Required Arrival Time at a node (RAT): The latest time the signal is
allowed to leave the node to make it to the sink in time.

⚫ Where FO(v) is the fan-out nodes, and t(u,v) is the delay between
u and v
⚫ Slack at “n” is defined as= RAT(n)-AT(n)
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?
⚫
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?

⚫ Step 1
⚫
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?

⚫ Step 2: Compute AATs at each node.

 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?

⚫ Step 3:
⚫ Previous node max total AATs

⚫ New node gate delay

⚫ Wire delay
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?

⚫ Step 4:
⚫ Compute ATs at each node x, y, z, w, and f

⚫ ATs at a=0

⚫ ATs at b=0

⚫ ATs at c=0.6

⚫ ATs at x=1.1

⚫ ATs at y=3.2

⚫ ATs at z=3.4

⚫ ATs at w=5.65

⚫ ATs at f=5.85
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?
⚫ Step 5:
⚫ Compute RATs at each node.
 Module 1-Mapping algorithms into architectures

Critical path and worst case timing analysis

⚫ Example: Find the worst path and check if it meets a cycle time of
T=5.5ms?
⚫ Step 6:
⚫ Compute RATs at each node.

⚫ RATs at w=[Expected RAT (5.5)-gate delay(0)]-wire delay(0.2)=5.3

⚫ RATs at z=(5.3-2)-0.25=3.05
⚫ RATs at y=(5.3-2)-0.2=3.1
⚫ RATs at x=(3.05-2)-0.3=0.75
⚫ RATs at c=(3.05-2)-0.1=0.95
⚫ RATs at b=(0.75-1)-0.1=-0.35
⚫ RATs at a=(3.1-2)-0.15=0.95
⚫ RATs at s=-0.35
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Critical path and worst case timing analysis

Now, Slack (v)=RAT(v)-AAT(v)
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Critical path and worst case timing analysis

Now, worst path
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Finite State Machines (FSM)

⚫ FSM:
⚫ It is a abstract model to represent the sequential circuits.

⚫ To control the behavior of the system and data flow paths

⚫ Combinational Circuits:
⚫ The output depends on the present inputs

⚫ Sequential Circuits
⚫ The outputs depends on the present inputs and the present states.

(memory elements)

⚫ All the synchronous sequential circuits are known as finite state

machines. Synchronous counters, registers, etc.
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Depending on how the output is generated, there are two types of

FSMs

⚫ Melay model/machine

⚫ Moore model/machine
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Melay machine: The output is a function of present inputs and

present state of the internal memory elements.

 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Melay machine: The output is a function of present inputs and

present state of the internal memory elements.

 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Moore machine: The output is a function of present state of the

internal memory elements.

 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Moore machine: The output is a function of present state of the

internal memory elements.

 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Irrespective of the machine, the FSM can be represented in three

different ways.
⚫ State transition diagram

⚫ Pictorial representation

⚫ State table

⚫ Tabular representation

⚫ State equations

⚫ Algebraic representation
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Irrespective of the machine, the FSM can be represented in three

different ways.
⚫ State diagram
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Irrespective of the machine, the FSM can be represented in three

different ways.
⚫ State diagram (Melay)
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Irrespective of the machine, the FSM can be represented in three

different ways.
⚫ State diagram (Moore) State Table
 Module 1-Mapping algorithms into architectures
Finite State Machines (FSM)
⚫ FSM:
⚫ Example:

⚫ Melay
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Finite State Machines (FSM)

⚫ FSM:
⚫ Example:
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Example:

⚫ Moore
 Module 1-Mapping algorithms into architectures

Finite State Machines (FSM)

⚫ FSM:
⚫ Example:

⚫ Moore
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Hazards
⚫ Hazard:
⚫ A hazard is a momentary unwanted switching transient at a logic

function’s output (Glitch)

⚫ Hazards occur due to unequal propagation delays along different

paths in a combinational circuit

⚫ We can take steps to try and eliminate hazards

⚫ There are two types of hazards

⚫ Static

⚫ Dynamic
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Hazard:
⚫ Static Hazard: It takes place when the change in input causes the

output to change momentarily before stabilizing to its correct

value
⚫ Static-1 hazard: Static-1 Hazards occur in SOP (SUM-OF-

PRODUCT) circuit.
⚫ If the output is currently at logic state 1 and after the input

changes its state, the output momentarily changes to 0 before

settling on 1, then it is a Static-1 hazard.

⚫ In response to an input change & for some combination of

PROPAGATION DELAY a logic circuit may go to zero (0)
when it should remain constant at one (1) this transient is
called a STATIC-1 Hazards as shown.
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Hazard:
⚫ Static Hazard: It takes place when the change in input causes the

output to change momentarily before stabilizing to its correct

value
⚫ Static-1 hazard:

⚫
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Hazard:
⚫ Static Hazard: It takes place when the change in input causes the

output to change momentarily before stabilizing to its correct

value
⚫ Static-0 hazard: Static-0 Hazards occur in the POS (PRODUCT-

OF-SUM) circuit.
⚫ If the output is currently at logic state 0 and after the input

changes its state, the output momentarily changes to 1 before

settling on 0, then it is a Static-0 hazard.

⚫ In response to an input change & for some combination of

PROPAGATION DELAY a logic circuit may go to one (1)
when it should remain constant at zero (0) this transient is
called a STATIC-1 Hazards as shown
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Hazard:
⚫ Static Hazard: It takes place when the change in input causes the

output to change momentarily before stabilizing to its correct

value
⚫ Static-0 hazard:

⚫
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Hazard:
⚫ Dynamic Hazard: It takes place when the input changes and a

circuit output should change from 0 to 1 or 1 to 0, but temporarily

flips between values
⚫ Dynamic hazard:

⚫
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Example:
⚫ Consider the circuit with delays where only one input changes
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Elimination:
⚫ Once detected, a static-1 hazard can be easily removed by

introducing some more terms (logic gates) to the function (circuit)

⚫ When the circuits are implemented as 2-level SOP (2-level POS),

one can detect and remove hazards by inspecting the K-map and
adding redundant product (sum) terms

⚫ If adjacent min terms are not covered by the same product term
then a hazard exists.
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Elimination:
⚫ Once detected, a static-1 hazard can be easily removed by

introducing some more terms (logic gates) to the function (circuit)

⚫ When the circuits are implemented as 2-level SOP (2-level POS),

one can detect and remove hazards by inspecting the K-map and
adding redundant product (sum) terms
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Elimination:
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Elimination:
⚫ Example: Design the hazard free realization of the following

circuit
 Module 1-Mapping algorithms into architectures

Hazards
⚫ Static Hazard Elimination:
⚫ Example: Design the static 0 hazard free realization of the

Y=(A+C).(A’+B)