CC2340R2, CC2340R5

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CC2340R SimpleLink™ Family of 2.4GHz Wireless MCUs

1 Features MCU peripherals
Wireless microcontroller • Up to 26 I/O pads
• Optimized 48MHz Arm® Cortex®-M0+ processor – 2 IO pads SWD, muxed with GPIOs
• Up to 512KB of in-system programmable flash – 2 IO pads LFXT, muxed with GPIOs
• 12KB of ROM for bootloader and drivers – Up to 22 DIOs (analog or digital IOs)
• Up to 64KB of ultra-low leakage SRAM. Full RAM • Up to 3 × 16-bit and 1× 24-bit general-purpose
retention in standby mode timers, quadrature decode mode support
• 2.4GHz RF transceiver compatible with Bluetooth® • 12-bit ADC, 1.2Msps with external reference,
5.3 Low Energy and IEEE 802.15.4 PHY and MAC 267ksps with internal reference, up to 12 external
• Integrated balun ADC inputs
• Supports over-the-air upgrade (OTA) • 1× low power comparator
• Serial wire debug (SWD) • 1× UART
• 1× SPI
Low power consumption • 1× I2C
• MCU consumption: • Real-time clock (RTC)
• Integrated temperature and battery monitor
– 2.6mA active mode, CoreMark®
• Watchdog timer
– 53μA/MHz running CoreMark®
– < 710nA standby mode on CC2340R52 Security enablers
– 165nA shutdown mode, wake-up on pin
• AES 128-bit cryptographic accelerator
• Radio consumption:
• Random number generator from on-chip analog
– 5.3mA RX
noise
– 5.1mA TX at 0dBm
– < 11.0mA TX at +8dBm Development tools and software
Wireless protocol support • LP-EM-CC2340R5 LaunchPad Development Kit
• SimpleLink™ Low Power F3 software
• Bluetooth® 5.3 Low Energy
development kit
• Zigbee®
• SmartRF™ Studio for simple radio configuration
• Thread
• SysConfig system configuration tool
• Proprietary systems
Operating range
High-performance radio
• On-chip buck DC/DC converter
• –102dBm sensitivity for Bluetooth® Low Energy
• 1.71V to 3.8V single supply voltage
125kbps
• Tj: –40°C up to +125°C
• –96.5dBm sensitivity for Bluetooth® Low Energy
1Mbps RoHS-compliant package
• –98dBm sensitivity for IEEE 802.15.4 (2.4GHz)
• 5mm × 5mm RKP QFN40
• Output power up to +8dBm with temperature
• 4mm × 4mm RGE QFN24
compensation
• 2.2mm × 2.6mm YBG WCSP (Preview)
Regulatory compliance
• Suitable for systems targeting compliance with
these standards:
– EN 300 328 (Europe)
– FCC CFR47 Part 15
– ARIB STD-T66 (Japan)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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2 Applications • Retail automation & payment – electronic point of

sale
• Medical – Electronic shelf label
– Home healthcare – blood glucose monitors, • Grid infrastructure
blood pressure monitor, CPAP machine, – Smart meters – water meter, gas meter,
electronic thermometer electricity meter, and heat cost allocators
– Patient monitoring and diagnostics – medical – Grid communications – wireless
sensor patches communications – Long-range sensor
– Personal care and fitness – electric toothbrush, applications
wearable fitness & activity monitor – Other alternative energy – energy harvesting
• Building automation • Communication equipment
– Building security systems – motion detector, – Wired networking
electronic smart lock, door and window sensor, – wireless LAN or Wi-Fi access points, edge
garage door system, gateway router
– HVAC – thermostat, wireless environmental • Personal electronics
sensor – Connected peripherals – consumer wireless
– Fire safety system – smoke and heat detector module, pointing devices, keyboards and
– Video surveillance – IP network camera keypads
• Lighting – Gaming – electronic and robotic toys
– LED luminaire – Wearables (non-medical) – smart trackers,
– Lighting control – daylight sensor, lighting smart clothing
sensor, wireless control
• Factory automation and control
3 Description
The CC2340R SimpleLink™ family of devices are 2.4GHz wireless microcontrollers (MCUs), targeting
Bluetooth® 5.3 Low Energy, Zigbee, Thread, and Proprietary 2.4GHz applications. These devices are optimized
for low-power wireless communication with Over the Air Download (OAD) support in Building automation
(wireless sensors, lighting control, beacons), asset tracking, medical, retail EPOS (electronic point of sale),
ESL (electronic shelf), and Personal electronics (toys, HID, stylus pens) markets. Highlighted features of this
device include:
• Support for Bluetooth 5 features: high-speed mode (2Mbps PHY), long-range (LE Coded 125kbps and
500kbps PHYs), privacy 1.2.1 and channel selection algorithm #2, as well as backward compatibility and
support for key features from the Bluetooth 4.2 and earlier Low Energy specifications.
• Fully qualified Bluetooth 5.3 software protocol stack included with the SimpleLink™ Low Power F3 software
development kit (SDK)
• Zigbee® protocol stack support in the SimpleLink™ Low Power F3 software development kit (SDK)
• Thread protocol stack support in SIMPLELINK TI OPENTHREAD SDK (1)
• Ultra-low standby current less than 0.71μA with RTC operational and full RAM retention that enables
significant battery life extension, especially for applications with longer sleep intervals.
• Integrated balun for reduced bill-of-material (BOM) board layout
• Excellent radio sensitivity and robustness (selectivity and blocking) performance for Bluetooth Low Energy
(–102dBm for 125kbps LE Coded PHY, with integrated balun)
The CC2340R family is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee, Sub-1GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment with a single-core software development kit (SDK) and rich tool set. A one-time integration of the
SimpleLink™ platform enables you to add any combination of the portfolio’s devices into your design, allowing
100 percent code reuse when your design requirements change. For more information, visit the SimpleLink™
MCU platform.

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Device Information
TEMPERATURE
PART NUMBER(2) FLASH RAM PACKAGE STATUS
RANGE
CC2340R53E0RKPR 512KB 64KB –40°C–125°C QFN40 Released
CC2340R53E0YBGR(1) 512KB 64KB –40°C–125°C WCSP Preview
CC2340R53N0RKPR 512KB 64KB –40°C–85°C QFN40 Released
CC2340R52E0RKPR 512KB 36KB –40°C–125°C QFN40 Released
CC2340R52E0RGER 512KB 36KB –40°C–125°C QFN24 Released
CC2340R52N0RKPR 512KB 36KB –40°C–85°C QFN40 Released
CC2340R52N0RGER 512KB 36KB –40°C–85°C QFN24 Released
CC2340R22E0RKPR 256KB 36KB –40°C–125°C QFN40 Released
CC2340R22N0RKPR 256KB 36KB –40°C–85°C QFN40 Released
CC2340R21E0RGER(1) 256KB 28KB –40°C–125°C QFN24 Preview

CC2340R21N0RGER 256KB 28KB –40°C–85°C QFN24 Released

(1) Available in a future release

(2) For more information, see Section 12.

4 Functional Block Diagram

48 MHz 48 MHz
DC/DC POR
HFXT HFOSC

Arm Cortex M0+ Processor 32.768 kHz 32.768 kHz

LFXT Global LDO BOR
LFOSC

2.4GHz Radio Transceiver

48 MHz
Digital PLL

Radio Digital

PA
B

LNA
RF RAM A 2.4 GHz
L 50 Ω
ADC U
SWD Modem Accelerators N
ADC
System Buses

µDMA (8 channel)
System Buses

12-bit ADC
RTC LGPT Timers 1x UART
Upto 512kB Flash 1.2 Msps
PWR & CLK Mgmt.

SYSTIM Low Power

WDT 1x SPI
Upto 64kB SRAM System Timer Comparator

Temperature Thermal
12kB System ROM 1x I2C
Sensor Shutdown

Battery
Monitor

AES-128
IOMUX | up to 26 GPIOs

Figure 4-1. CC2340R Family Block Diagram

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Table of Contents
1 Features............................................................................1 7.20 Timing and Switching Characteristics..................... 30
2 Applications..................................................................... 2 7.21 Peripheral Characteristics.......................................31
3 Description.......................................................................2 7.22 Typical Characteristics............................................ 39
4 Functional Block Diagram.............................................. 3 8 Detailed Description......................................................48
5 Device Comparison......................................................... 5 8.1 Overview................................................................... 48
6 Pin Configurations and Functions.................................6 8.2 System CPU............................................................. 48
6.1 Pin Diagrams.............................................................. 6 8.3 Radio (RF Core)........................................................48
6.2 Signal Descriptions................................................... 13 8.4 Memory..................................................................... 49
6.3 Connections for Unused Pins and Modules..............17 8.5 Cryptography............................................................ 50
7 Specifications................................................................ 18 8.6 Timers....................................................................... 50
7.1 Absolute Maximum Ratings...................................... 18 8.7 Serial Peripherals and I/O.........................................51
7.2 ESD Ratings............................................................. 18 8.8 Battery and Temperature Monitor............................. 52
7.3 Recommended Operating Conditions.......................18 8.9 µDMA........................................................................ 52
7.4 DCDC........................................................................18 8.10 Debug..................................................................... 52
7.5 Global LDO (GLDO)..................................................19 8.11 Power Management................................................ 53
7.6 Power Supply and Modules...................................... 19 8.12 Clock Systems........................................................ 54
7.7 Battery Monitor..........................................................19 8.13 Network Processor..................................................54
7.8 Temperature Sensor................................................. 19 9 Application, Implementation, and Layout................... 55
7.9 Power Consumption - Power Modes........................ 20 9.1 Reference Designs................................................... 55
7.10 Power Consumption - Radio Modes....................... 21 9.2 Junction Temperature Calculation.............................56
7.11 Nonvolatile (Flash) Memory Characteristics........... 21 10 Device and Documentation Support..........................57
7.12 Thermal Resistance Characteristics....................... 21 10.1 Device Nomenclature..............................................57
7.13 RF Frequency Bands.............................................. 22 10.2 Tools and Software................................................. 57
7.14 Bluetooth Low Energy - Receive (RX).................... 23 10.3 Documentation Support.......................................... 59
7.15 Bluetooth Low Energy - Transmit (TX)....................26 10.4 Support Resources................................................. 59
7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 10.5 Trademarks............................................................. 59
GHz (OQPSK DSSS1:8, 250 kbps) - RX.................... 27 10.6 Electrostatic Discharge Caution..............................60
7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 10.7 Glossary..................................................................60
GHz (OQPSK DSSS1:8, 250 kbps) - TX.....................28 11 Revision History.......................................................... 60
7.18 Proprietary Radio Modes........................................ 29 12 Mechanical, Packaging, and Orderable
7.19 2.4 GHz RX/TX CW................................................ 30 Information.................................................................... 62

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5 Device Comparison
RADIO SUPPORT PACKAGE SIZE

2.2 X 2.6 mm WCSP (24)

4 X 4 mm VQFN (24)

5 X 5 mm VQFN (40)
RAM + Cache
Device FLASH (KB) GPIO

Bluetooth® LE
(KB)
2.4GHz Prop.

ZigBee

Thread
CC2340R53 ✓ ✓ ✓ ✓ 512 64 12-26 ✓ ✓
CC2340R52 ✓ ✓ ✓ ✓ 512 36 12-26 ✓ ✓
CC2340R22 ✓ ✓ ✓ ✓ 256 36 26 ✓
CC2340R21 ✓ ✓ ✓ 256 28 12 ✓

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6 Pin Configurations and Functions

6.1 Pin Diagrams
6.1.1 Pin Diagram—RKP Package (Top View)

33 DIO7_A0
32 DIO6_A1
40 RFGND

34 VDDR
38 VDDS

31 VDDS
36 X48N
35 X48P
39 ANT

37 NC
VDDR 1 30 DCDC
DIO8 2 29 DIO5_A2
DIO9 3 28 VDDD
DIO10 4 27 DIO4_X32N
DIO11 5 26 DIO3_X32P
DIO12 6 25 RSTN
DIO13 7 24 DIO2_A3
VDDS 8 23 DIO1_A4
DIO14 9 22 DIO0_A5
DIO15 10 21 DIO25_A6
DIO17_SWDCK 12
DIO18 13
DIO19 14
DIO20_A11 15
DIO21_A10 16
VDDS 17
DIO22_A9 18
DIO23_A8 19
DIO24_A7 20
DIO16_SWDIO 11

Figure 6-1. RKP (5mm × 5mm) Pinout, 0.4mm Pitch (Top View)

The following I/O pins marked in Figure 6-1 in bold have high-drive capabilities:
• Pin 6, DIO12
• Pin 11, DIO16_SWDIO
• Pin 12, DIO17_SWDCK
• Pin 13, DIO18
• Pin 14, DIO19
• Pin 20, DIO24_A7
The following I/O pins marked in Figure 6-1 in italics have analog capabilities:
• Pin 15, DIO20_A11
• Pin 16, DIO21_A10
• Pin 18, DIO22_A9
• Pin 19, DIO23_A8
• Pin 20, DIO24_A7
• Pin 21, DIO25_A6
• Pin 22, DIO0_A5
• Pin 23, DIO1_A4
• Pin 24, DIO2_A3
• Pin 29, DIO5_A2
• Pin 32, DIO6, A1
• Pin 33, DIO7_A0

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6.1.2 Pin Diagram – RGE Package (Top View)

19 DIO6_A1
20 VDDR
24 VDDS

22 X48N
21 X48P
23 GND
ANT 1 18 VDDS
VDDR 2 17 DCDC
DIO8 3 16 VDDD
DIO11 4 15 DIO4_X32N
DIO12 5 14 DIO3_X32P
DIO13 6 13 RSTN

DIO21_A10 10

DIO24_A7 12
VDDS 11
7
8
9
DIO16_SWDIO
DIO17_SWDCK
DIO20_A11

Figure 6-2. RGE (4mm × 4mm) Pinout, 0.5mm Pitch (Top View)

The following I/O pins marked in Figure 6-2 in bold have high-drive capabilities:
• Pin 5, DIO12
• Pin 7, DIO16_SWDIO
• Pin 8, DIO17_SWDCK
• Pin 12, DIO24_A7
The following I/O pins marked in Figure 6-2 in italics have analog capabilities:
• Pin 9, DIO20_A11
• Pin 10, DIO21_A10
• Pin 12, DIO24_A7
• Pin 19, DIO6_A1

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6.1.3 Pin Diagram—YBG Package (Top View)

Figure 6-3. Preview—YBG (2.2mm × 2.6mm) Pinout, 0.4mm Pitch (Top View)

The following I/O pins marked in Figure 6-2 in bold have high-drive capabilities:
• Pin B2, DIO12
• Pin A1, DIO16_SWDIO
• Pin A2, DIO17_SWDCK
• Pin C4, DIO24_A7
The following I/O pins marked in Figure 6-2 in italics have analog capabilities:
• Pin A3, DIO20_A11
• Pin A4, DIO21_A10
• Pin C4, DIO24_A7
• Pin D3, DIO6_A1
Table 6-1. Pin Attributes (RKP, RGE, YBG, Packages)
RKP PIN RGE PIN YBG PIN
SIGNAL NAME PIN NAME MUX ENCODING SIGNAL TYPE
NUMBER NUMBER NUMBER
39 1 F2 ANT ANT RF
30 17 E5 DCDC DCDC PWR

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Table 6-1. Pin Attributes (RKP, RGE, YBG, Packages) (continued)

RKP PIN RGE PIN YBG PIN
SIGNAL NAME PIN NAME MUX ENCODING SIGNAL TYPE
NUMBER NUMBER NUMBER
2 3 C2 DIO8 GPIO8 0 I/O
SPI0SCLK 1 I/O
UART0RTS 2 I/O
T1C0N 3 I/O
I2C0SDA 4 I/O
T0C0N 5 I/O
DTB3 7 I/O
3 DIO9 GPIO9 0 I/O
T3C0 1 I/O
LRFD3 3 I/O
22 DIO0_A5 GPIO0 0 I/O
SPI0CSN 1 I/O
I2C0SDA 2 I/O
T3C2 3 I/O
ANA5 6 ANALOG
4 DIO10 GPIO10 0 I/O
LPCO 1 I/O
T2PE 2 I/O
T3C0N 3 I/O
5 4 B1 DIO11 GPIO11 0 I/O
SPI0CSN 1 I/O
T1C2N 2 I/O
T0C0 3 I/O
LRFD0 4 I/O
SPI0POCI 5 I/O
DTB9 7 I/O
6 5 B2 DIO12 GPIO12 0 I/O
SPI0POCI 1 I/O
SPI0PICO 2 I/O
UART0RXD 3 I/O
T1C1 4 I/O
I2C0SDA 5 I/O
DTB13 7 I/O
7 6 DIO13 GPIO13 0 I/O
SPI0POCI 1 I/O
SPI0PICO 2 I/O
UART0TXD 3 I/O
T0C0N 4 I/O
T1F 5 I/O
DTB4 7 I/O

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Table 6-1. Pin Attributes (RKP, RGE, YBG, Packages) (continued)

RKP PIN RGE PIN YBG PIN
SIGNAL NAME PIN NAME MUX ENCODING SIGNAL TYPE
NUMBER NUMBER NUMBER
9 DIO14 GPIO14 0 I/O
T3C2 1 I/O
T1C2N 2 I/O
LRFD5 3 I/O
T1F 4 I/O
10 DIO15 GPIO15 0 I/O
UART0RXD 1 I/O
T2C0N 2 I/O
CKMIN 3 I/O
11 7 A1 DIO16_SWDIO GPIO16 0 I/O
SPI0PICO 1 I/O
UART0RXD 2 I/O
I2C0SDA 3 I/O
T1C2 4 I/O
T1C0N 5 I/O
DTB10 7 I/O
12 8 A2 DIO17_SWDCK GPIO17 0 I/O
SPI0SCLK 1 I/O
UART0TXD 2 I/O
I2C0SCL 3 I/O
T1C1N 4 I/O
T0C2 5 I/O
DTB11 7 I/O
13 B3 DIO18 GPIO18 0 I/O
T3C0 1 I/O
LPCO 2 I/O
UART0TXD 3 I/O
SPI0SCLK 4 I/O
DTB12 7 I/O
14 DIO19 GPIO19 0 I/O
T3C1 1 I/O
T2PE 2 I/O
SPI0PICO 4 I/O
DTB0 7 I/O
23 DIO1_A4 GPIO1 0 I/O
T3C1 1 I/O
LRFD7 2 I/O
T1F 3 I/O
UART0RTS 4 I/O
ANA4 6 ANALOG
DTB2 7 I/O

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Table 6-1. Pin Attributes (RKP, RGE, YBG, Packages) (continued)

RKP PIN RGE PIN YBG PIN
SIGNAL NAME PIN NAME MUX ENCODING SIGNAL TYPE
NUMBER NUMBER NUMBER
15 9 A3 DIO20_A11 GPIO20 0 I/O
LPCO 1 I/O
UART0TXD 2 I/O
UART0RXD 3 I/O
T1C0 4 I/O
SPI0POCI 5 I/O
ANA11 6 ANALOG
DTB14 7 I/O
16 10 A4 DIO21_A10 GPIO21 0 I/O
UART0CTS 1 I/O
T1C1N 2 I/O
T0C1 3 I/O
SPI0POCI 4 I/O
LRFD1 5 I/O
ANA10 6 ANALOG
DTB15 7 I/O
18 DIO22_A9 GPIO22 0 I/O
T2C0N 1 I/O
UART0RXD 2 I/O
T3C1N 3 I/O
ANA9 6 ANALOG
DTB1 7 I/O
19 DIO23_A8 GPIO23 0 I/O
T2C1 1 I/O
T3C2N 3 I/O
ANA8 6 ANALOG
20 12 C4 DIO24_A7 GPIO24 0 I/O
SPI0SCLK 1 I/O
T1C0 2 I/O
T3C0 3 I/O
T0PE 4 I/O
I2C0SCL 5 I/O
ANA7 6 ANALOG
DTB5 7 I/O
21 DIO25_16 GPIO25 0 I/O
SPI0POCI 1 I/O
I2C0SCL 2 I/O
T2C2N 3 I/O
ANA6 6 ANALOG
24 DIO2_A3 GPIO2 0 I/O
T0PE 1 I/O
T2C1N 2 I/O
UART0CTS 3 I/O
ANA3 6 ANALOG

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Table 6-1. Pin Attributes (RKP, RGE, YBG, Packages) (continued)

RKP PIN RGE PIN YBG PIN
SIGNAL NAME PIN NAME MUX ENCODING SIGNAL TYPE
NUMBER NUMBER NUMBER
26 14 C5 DIO3_X32P GPIO3 0 I/O
LFCI 1 I/O
T0C1N 2 I/O
LRFD0 3 I/O
T3C1 4 I/O
T1C2 5 I/O
LFXT_P 6 I/O
DTB7 7 I/O
27 15 B5 DIO4_X32N GPIO4 0 I/O
T0C2N 1 I/O
UART0TXD 2 I/O
LRFD1 3 I/O
SPI0PICO 4 I/O
T0C2 5 I/O
LFXT_N 6 I/O
DTB8 7 I/O
29 DIO5_A2 GPIO5 0 I/O
T2C2 1 I/O
LRFD6 3 I/O
ANA2 6 ANALOG
32 19 D3 DIO6_A1 GPIO6 0 I/O
SPI0CSN 1 I/O
I2C0SCL 2 I/O
T1C2 3 I/O
LRFD2 4 I/O
UART0TXD 5 I/O
ANA1 6 ANALOG
DTB6 7 I/O
33 DIO7_A0 GPIO7 0 I/O
T3C1 1 I/O
LRFD4 3 I/O
ANA0 6 ANALOG
23 C1, C3, D4, F5 GND GND GND
37 NC NC NC
40 E2 RFGND RFGND GND
25 13 A5 RSTN RSTN I/O
28 16 D5 VDDD VDDD PWR
1, 34 2, 20 D1, D2 VDDR VDDR PWR
17, 31, 38, 8 11, 18, 24 B4, E3, E4 VDDS VDDS PWR
36 22 F3 X48N X48N I/O
35 21 F4 X48P X48P I/O

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6.2 Signal Descriptions

Table 6-2. Analog Input Signal Descriptions
SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
ANA0 ANALOG I ADC reference (negative 33
terminal) or ADC channel 0 input
ANA1 ANALOG I ADC reference (positive terminal) 32 19 D3
or ADC channel 1 input
ANA2 ANALOG I ADC channel 2 input 29
ANA3 ANALOG I ADC channel 3 input 24
ANA4 ANALOG I ADC channel 4 input 23
ANA5 ANALOG I ADC channel 5 input 22
ANA6 ANALOG I ADC channel 6 input 21
ANA7 ANALOG I Low power comparator input 20 12 C4
(positive terminal) / ADC channel
7 input
ANA8 ANALOG I Low power comparator input 19
(positive or negative terminal) /
ADC channel 8 input
ANA9 ANALOG I ADC channel 9 input 18
ANA10 ANALOG I Low power comparator input 16 10 A4
(positive terminal) / ADC channel
10 input
ANA11 ANALOG I ADC channel 11 input 15 9 A3

Table 6-3. Clock Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
CKMIN I/O I HFOSC tracking loop input 10
LFCI I/O I Low frequency clock input (LFXT 26 14 C5
bypass clock from pin)
LFXT_N I/O I 32kHz crystal oscillator pin 2 27 15 B5
LFXT_P I/O I 32kHz crystal oscillator pin 1 26 14 C5
X48N I/O I 48MHz crystal oscillator pin 2 36 22 F3
X48P I/O I 48MHz crystal oscillator pin 1 35 21 F4

Table 6-4. DTB Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
DTB0 I/O O Digital test bus output 0 14
DTB1 I/O O Digital test bus output 1 18
DTB2 I/O O Digital test bus output 2 23
DTB3 I/O O Digital test bus output 3 2 3 C2
DTB4 I/O O Digital test bus output 4 7 6
DTB5 I/O O Digital test bus output 5 20 12 C4
DTB6 I/O O Digital test bus output6 32 19 D3
DTB7 I/O O Digital test bus output 7 26 14 C5
DTB8 I/O O Digital test bus output 8 27 15 B5
DTB9 I/O O Digital test bus output 9 5 4 B1
DTB10 I/O O Digital test bus output 10 11 7 A1

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Table 6-4. DTB Signal Descriptions (continued)

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
DTB11 I/O O Digital test bus output 11 12 8 A2
DTB12 I/O O Digital test bus output 12 13 B3
DTB13 I/O O Digital test bus output 13 6 5 B2
DTB14 I/O O Digital test bus output 14 15 9 A3
DTB15 I/O O Digital test bus output 15 16 10 A4

Table 6-5. GPIO Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
GPIO0 I/O I/O General-purpose input or output 22
GPIO1 I/O I/O General-purpose input or output 23
GPIO2 I/O I/O General-purpose input or output 24
GPIO3 I/O I/O General-purpose input or output 26 14 C5
GPIO4 I/O I/O General-purpose input or output 27 15 B5
GPIO5 I/O I/O General-purpose input or output 29
GPIO6 I/O I/O General-purpose input or output 32 19 D3
GPIO7 I/O I/O General-purpose input or output 33
GPIO8 I/O I/O General-purpose input or output 2 3 C2
GPIO9 I/O I/O General-purpose input or output 3
GPIO10 I/O I/O General-purpose input or output 4
GPIO11 I/O I/O General-purpose input or output 5 4 B1
GPIO12 I/O I/O General-purpose input or output 6 5 B2
GPIO13 I/O I/O General-purpose input or output 7 6
GPIO14 I/O I/O General-purpose input or output 9
GPIO15 I/O I/O General-purpose input or output 10
GPIO16 I/O I/O General-purpose input or output 11 7 A1
GPIO17 I/O I/O General-purpose input or output 12 8 A2
GPIO18 I/O I/O General-purpose input or output 13 B3
GPIO19 I/O I/O General-purpose input or output 14
GPIO20 I/O I/O General-purpose input or output 15 9 A3
GPIO21 I/O I/O General-purpose input or output 16 10 A4
GPIO22 I/O I/O General-purpose input or output 18
GPIO23 I/O I/O General-purpose input or output 19
GPIO24 I/O I/O General-purpose input or output 20 12 C4
GPIO25 I/O I/O General-purpose input or output 21

Table 6-6. Device Grounds

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
GND GND N/A Ground 23 C1, C3, D4, F5
RFGND GND N/A RF ground reference 40 E2

Table 6-7. I2C Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
I2C0SCL I/O I/O I2C clock 12, 20, 21, 32 12, 19, 8 A2, C4, D3

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Table 6-7. I2C Signal Descriptions (continued)

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
I2C0SDA I/O I/O I2C data 11, 2, 22, 6 3, 5, 7 A1, B2, C2

Table 6-8. Low Power Comparator Output Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
LPCO I/O O Low power comparator output 13, 15, 4 9 A3, B3

Table 6-9. No Connect

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
NC NC N/A No connect 37

Table 6-10. Device Power

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
DCDC (1) PWR N/A Switch node of the internal 30 17 E5
DC/DC converter
VDDD (1) PWR N/A Internal 1.28V regulator 28 16 D5
decoupling capacitor
VDDR PWR N/A Internal supply, must be powered 1, 34 2, 20 D1, D2
from the internal DC/DC
converter or the internal LDO
VDDS PWR N/A 1.71V to 3.8V supply 17, 31, 38, 8 11, 18, 24 B4, E3, E4

(1) Do not supply external circuitry from this pin.

Table 6-11. Reset Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
RSTN I/O I Global main device reset (active 25 13 A5
low)

Table 6-12. Radio Digital Output Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
LRFD0 I/O O Radio Core Output 0 26, 5 14, 4 B1, C5
LRFD1 I/O O Radio Core Output 1 16, 27 10, 15 A4, B5
LRFD2 I/O O Radio Core Output 2 32 19 D3
LRFD3 I/O O Radio Core Digital Output 3 3
LRFD4 I/O O Radio Core Output 4 33
LRFD5 I/O O Radio Core Output 5 9
LRFD6 I/O O Radio Core Output 6 29
LRFD7 I/O O Radio Core Output 7 23

Table 6-13. RF Port

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
ANT RF I/O 50Ω RF port 39 1 F2

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Table 6-14. SPI Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
SPI0CSN I/O I/O SPI chip select 22, 32, 5 19, 4 B1, D3
SPI0PICO I/O I/O SPI peripheral in controller out 11, 14, 27, 6, 7 15, 5, 6, 7 A1, B2, B5
SPI0POCI I/O I/O SPI peripheral out controller in 15, 16, 21, 5, 6, 10, 4, 5, 6, 9 A3, A4, B1, B2
7
SPI0SCLK I/O I/O SPI clock 12, 13, 2, 20 12, 3, 8 A2, B3, C2, C4

Table 6-15. Timers Capture or Compare Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
T0C0 I/O I/O Capture or compare 0 from timer 5 4 B1
0
T0C1 I/O I/O Capture or compare 1 from timer 16 10 A4
0
T0C2 I/O I/O Capture or compare 2 from timer 12, 27 15, 8 A2, B5
0
T1C0 I/O I/O Capture or compare 0 from timer 15, 20 12, 9 A3, C4
1
T1C1 I/O I/O Capture or compare 1 from timer 6 5 B2
1
T1C2 I/O I/O Capture or compare 2 from timer 11, 26, 32 14, 19, 7 A1, C5, D3
1
T2C1 I/O I/O Capture or compare 1 from timer 19
2
T2C2 I/O I/O Capture or compare 2 from timer 29
2
T3C0 I/O I/O Capture or compare 0 from timer 13, 20, 3 12 B3, C4
3
T3C1 (1) I/O I/O Capture or compare 1 from timer 14, 23, 26, 33 14 C5
3
T3C2 I/O I/O Capture or compare 2 from timer 22, 9
3

(1) Timer 3 not available on CC2340R21.

Table 6-16. Timers Complementary Output Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
T0C0N I/O O Complementary compare or 2, 7 3, 6 C2
PWM output 0 from timer 0
T0C1N I/O O Complementary compare or 26 14 C5
PWM output 1 from timer 0
T0C2N I/O O Complementary compare or 27 15 B5
PWM output 2 from timer 0
T1C0N I/O O Complementary compare or 11, 2 3, 7 A1, C2
PWM output 0 from timer 1
T1C1N I/O O Complementary compare or 12, 16 10, 8 A2, A4
PWM output 1 from timer 1
T1C2N I/O O Complementary compare or 5, 9 4 B1
PWM output 2 from timer 0
T2C0N I/O O Complementary compare or 10, 18
PWM output 0 from timer 2
T2C1N I/O O Complementary compare or 24
PWM output 1 from timer 2

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Table 6-16. Timers Complementary Output Signal Descriptions (continued)

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
T2C2N I/O O Complementary compare or 21
PWM output 2 from timer 2
T3C0N I/O O Complementary compare or 4
PWM output 0 from timer 3
T3C1N I/O O Complementary compare or 18
PWM output 1 from timer 3
T3C2N I/O O Complementary compare or 19
PWM output 2 from timer 3

Table 6-17. Timers Fault Input Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
T1F I/O I Fault input for timer 1 23, 7, 9 6

Table 6-18. Timers Prescaler Event Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
T0PE I/O O Prescaler event output from timer 20, 24 12 C4
0
T2PE I/O O Prescaler event output from timer 14, 4
2

Table 6-19. UART Signal Descriptions

SIGNAL
SIGNAL NAME PIN TYPE DESCRIPTION RKP PIN RGE PIN YBG PIN
DIRECTION
UART0CTS I/O I UART clear-to-send input (active 16, 24 10 A4
low)
UART0RTS I/O O UART request-to-send (active 2, 23 3 C2
low)
UART0RXD I/O I UART receive data 10, 11, 15, 18, 6 5, 7, 9 A1, A3, B2
UART0TXD I/O O UART transmit data 12, 13, 15, 27, 15, 19, 6, 8, 9 A2, A3, B3, B5,
32, 7 D3

6.3 Connections for Unused Pins and Modules

Table 6-20. Connections for Unused Pins
PREFERRED
FUNCTION SIGNAL NAME ACCEPTABLE PRACTICE(1)
PRACTICE(1)
GPIO (digital) DIOn NC, GND, or VDDS NC
DIO16_SWDIO NC, GND, or VDDS GND or VDDS
SWD
DIO17_SWDCK NC, GND, or VDDS GND or VDDS
GPIO (digital or analog) DIOn_Am NC, GND, or VDDS NC
DIO3_X32P
32.768-kHz crystal NC or GND NC
DIO4_X32N
DCDC NC NC
DC/DC converter(2)
VDDS VDDS VDDS

(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected and
the 10μF DCDC capacitor must be kept on the VDDR net.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDDS Supply voltage –0.3 4.1 V
Voltage on any digital pin(3) –0.3 VDDS + 0.3, max 4.1 V
Voltage on crystal oscillator pins X48P and X48N –0.3 1.24 V
Vin_adc Voltage on ADC input 0 VDDS V
Input level, RF pins 5 dBm
Tstg Storage temperature –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) Including analog capable DIOs.

7.2 ESD Ratings

VALUE UNIT
QFN packages
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±1000 V
VESD Electrostatic discharge
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) All pins ±500 V
WCSP packages
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins TBD V
VESD Electrostatic discharge
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) All pins TBD V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating ambient temperature(1) (2) –40 125 °C
CC2340xxxExxxxx devices (125 °C parts)
Operating junction temperature(1) (2) –40 125 °C
Operating ambient temperature(1) (2) –40 85 °C
CC2340xxxNxxxxx devices (85 °C parts)
Operating junction temperature(1) (2) –40 85 °C
Operating supply voltage (VDDS) 1.71 3.8 V
Rising supply voltage slew rate 0 100 mV/µs
Falling supply voltage slew rate(3) 0 1 mV/µs

(1) Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime.
(2) For thermal resistance details, refer to Thermal Resistance Characteristics table in this document.
(3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 10-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.

7.4 DCDC
When measured on the CC2340R5 reference design with Tc = 25 °C and DCDC enabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDDS supply voltage for DCDC operation (1) (2) 2.2 3.0 3.8 V

(1) When the supply voltage drops below the DCDC operation min voltage, the device automatically transitions to use GLDO regulator
on-chip.
(2) A 10uH and 10uF load capacitor are required on the VDDR voltage rail. They should be placed close to the DCDC output pin.

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7.5 Global LDO (GLDO)

When measured on the CC2340R5 reference design with Tc = 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDDS supply voltage for GLDO operation (1) 1.71 3.0 3.8 V

(1) A 10 µF capacitor is recommended at VDDR pin.

7.6 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDDS_BOD
Brownout rising threshold (1) 1.68 V
Brownout falling threshold (1) 1.67 V
POR
power-on reset power-up level 1.5 V
power-on reset power-down level 1.45 V

(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RSTN pin.

7.7 Battery Monitor

Measured on the CC2340R5 reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 22 mV
Range 1.7 3.8 V
Accuracy VDDS = 3.0 V 30 mV

7.8 Temperature Sensor

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC2340xxxExxxxx devices (125 °C devices)
Accuracy -40 °C to 125 °C -15/+9(1) °C
CC2340xxxNxxxxx devices (85 °C devices)
Accuracy -40 °C to 85 °C ±10(1) °C

(1) Raw output from register.

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7.9 Power Consumption - Power Modes

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, DCDC enabled, GLDO disabled, unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Core Current Consumption with DCDC
Icore Active MCU running CoreMark from Flash at 48 MHz 2.6 mA
Icore Active MCU running CoreMark from Flash at 48MHz 53 µA / MHz
Icore Idle Supply Systems and RAM powered, flash disabled, DMA disabled 0.8 mA
Icore Idle Supply Systems and RAM powered, flash disabled, DMA enabled 0.8 mA
Icore Idle Supply Systems and RAM powered, flash enabled, DMA disabled 1.1 mA
Icore Idle Supply Systems and RAM powered, flash enabled, DMA enabled 1.2 mA
RTC running, full RAM retention
Icore Standby 0.71 µA
LFOSC, DCDC recharge current setting (ipeak = 1)
RTC running, full RAM retention
Icore Standby LFXT, DCDC recharge current setting (ipeak = 1) 0.74 µA

Core Current consumption with GLDO

Icore Active MCU running CoreMark from Flash at 48 MHz 4.1 mA
Icore Idle Supply Systems and RAM powered, flash disabled, DMA disabled 1.2 mA
Icore Idle Supply Systems and RAM powered, flash disabled, DMA enabled 1.3 mA
Icore Idle Supply Systems and RAM powered, flash enabled, DMA disabled 1.5 mA
Icore Idle Supply Systems and RAM powered, flash enabled, DMA enabled 1.7 mA
RTC running, full RAM retention
Icore Standby 1.1 µA
LFOSC, default GLDO recharge current setting
RTC running, full RAM retention
Icore Standby 1.15 µA
LFXT default GLDO recharge current setting
Reset, Shutdown Current Consumption
Icore Reset Reset. RSTN pin asserted or VDDS below power-on-reset threshold 165 nA
Shutdown measured in steady state. No clocks running, no retention, IO
Icore Shutdown 165 nA
wakeup enabled
Peripheral Current Consumption
Iperi RF Delta current, clock enabled, RF subsystem idle 40 µA
Iperi Timers Delta current with clock enabled, module is idle, one LGPT timer 2.4 µA
Iperi I2C Delta current with clock enabled, module is idle 10.6 µA
Iperi SPI Delta current with clock enabled, module is idle 3.4 µA
Iperi UART Delta current with clock enabled, module is idle 24.5 µA
CRYPTO
Iperi Delta current with clock enabled, module is idle 3.8 µA
(AES)

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7.10 Power Consumption - Radio Modes

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V with DCDC enabled unless otherwise
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IRX Radio receive current 2440 MHz, 1 Mbps, GFSK, system bus off (1) 5.3 mA
IRX Radio receive current 2440 MHz, 1 Mbps, GFSK, DCDC OFF, system bus off (1) 9 mA
-8 dBm output power setting
ITX Radio transmit current 4.5 mA
2440 MHz system bus off (1)
Radio transmit current 0 dBm output power setting
ITX 5.1 mA
2440 MHz system bus off (1)
Radio transmit current 0 dBm output power setting
ITX 9.0 mA
2440 MHz DCDC OFF, system bus off (1)
+4 dBm output power setting
ITX Radio transmit current 7.9 mA
2440 MHz system bus off (1)
Radio transmit current +6 dBm output power setting
ITX 8.9 mA
2440 MHz system bus off (1)
Radio transmit current +8 dBm output power setting
ITX 10.7 mA
2440 MHz system bus off (1)
Radio transmit current +8 dBm output power setting
ITX 19 mA
2440 MHz DCDC OFF, system bus off (1)

(1) System bus off refers to device idle mode, DMA disabled, flash disabled

7.11 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 2 KB
Supported flash erase cycles before failure, full bank(1) (2) 30 k Cycles
Supported flash erase cycles before failure, single sector(3) 60 k Cycles
Maximum number of write operations per row before sector Write
83
erase(4) Operations
CC2340xxxExxxxx devices (125 °C devices)
Flash retention 105 °C 11.4 Years
Flash retention 125 °C 10 Years
CC2340xxxNxxxxx devices (85°C devices)
Flash retention 85 °C 11.4 Years
Flash sector erase current Average delta current 1.2 mA
Flash sector erase time(5) 0 erase cycles 2.2 ms
Flash write current Average delta current, full sector at a time 1.7 mA
Flash write time(5) full sector (2kB) at a time, 0 erase cycles 8.3 ms

(1) A full bank erase is counted as a single erase cycle on each sector
(2) Aborting flash during erase or program modes is not a safe operation.
(3) Up to 16 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(4) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(5) This number is dependent on Flash aging and increases over time and erase cycles

7.12 Thermal Resistance Characteristics

PACKAGE
THERMAL RKP RGE
THERMAL METRIC UNIT (1)
METRIC (VQFN) (VQFN)
40 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 31.8 40.1 ℃/W
RθJC(top) Junction-to-case (top) thermal resistance 23.1 30.5 ℃/W
RθJB Junction-to-board thermal resistance 12.7 17.2 ℃/W

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7.12 Thermal Resistance Characteristics (continued)

PACKAGE
THERMAL RKP RGE
THERMAL METRIC UNIT (1)
METRIC (VQFN) (VQFN)
40 PINS 24 PINS
ψJT Junction-to-top characterization parameter 0.3 0.4 ℃/W
ψJB Junction-to-board characterization parameter 12.7 17.1 ℃/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 3.4 ℃/W

(1) °C/W = degrees Celsius per watt.

7.13 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted).
PARAMETER MIN TYP MAX UNIT
Frequency bands 2360 2510 MHz

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7.14 Bluetooth Low Energy - Receive (RX)

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
125 kbps (LE Coded)
Receiver sensitivity BER = 10–3 –102 dBm
Receiver saturation BER = 10–3 5 dBm
Difference between the incoming carrier frequency and (1)
Frequency error tolerance > (–250/ 250) kHz
the internally generated carrier frequency
Difference between incoming data rate and the internally
Data rate error tolerance > (–90 / 90) (1) ppm
generated data rate (37-byte packets)
Difference between incoming data rate and the internally
Data rate error tolerance > (–90 / 90) (1) ppm
generated data rate (255-byte packets)
Wanted signal at –79 dBm, modulated interferer in
Co-channel rejection(2) –6 dB
channel, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±1
Selectivity, ±1 MHz(2) 9 / 5 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(2) 44 / 31 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±3
Selectivity, ±3 MHz(2) 47 / 42 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(2) 49 / 45 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ≥ ±6
Selectivity, ±6 MHz(2) 52 / 48 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ≥ ±7
Selectivity, ±7 MHz 54 / 49 (3) dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at image
Selectivity, Image frequency(2) 31 dB
frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co- channel
Selectivity, Image frequency ±1
–1 MHz. Wanted signal at –79 dBm, modulated interferer 5 / 42 (3) dB
MHz(2)
at ±1 MHz from image frequency, BER = 10–3
500 kbps (LE Coded)
Receiver sensitivity BER = 10–3 –99 dBm
Receiver saturation BER = 10–3 5 dBm
Difference between the incoming carrier frequency and (1)
Frequency error tolerance > (–250 / 250) kHz
the internally generated carrier frequency
Difference between incoming data rate and the internally
Data rate error tolerance > (–90/ 90) (1) ppm
generated data rate (37-byte packets)
Difference between incoming data rate and the internally
Data rate error tolerance > (–90 / 90) (1) ppm
generated data rate (255-byte packets)
Wanted signal at –72 dBm, modulated interferer in
Co-channel rejection(2) –4.5 dB
channel, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±1
Selectivity, ±1 MHz(2) 9 / 5 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(2) 42 / 31 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±3
Selectivity, ±3 MHz(2) 45 / 41 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(2) 46 / 42 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ≥ ±6
Selectivity, ±6 MHz(2) 50 / 45 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ≥ ±7
Selectivity, ±7 MHz 51 / 46 (3) dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at image
Selectivity, Image frequency(2) 31 dB
frequency, BER = 10–3

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7.14 Bluetooth Low Energy - Receive (RX) (continued)

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Note that Image frequency + 1 MHz is the Co- channel
Selectivity, Image frequency ±1
–1 MHz. Wanted signal at –72 dBm, modulated interferer 5 / 41 (3) dB
MHz(2)
at ±1 MHz from image frequency, BER = 10–3
1 Mbps (LE 1M)
Receiver sensitivity BER = 10–3 –96.5 dBm
Receiver saturation BER = 10–3 5 dBm
Difference between the incoming carrier frequency and
Frequency error tolerance > (–250/250) (1) kHz
the internally generated carrier frequency
Difference between incoming data rate and the internally
Data rate error tolerance > (–90 / 90) (1) ppm
generated data rate (37-byte packets)
Wanted signal at –67 dBm, modulated interferer in
Co-channel rejection(2) –6 dB
channel, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±1
Selectivity, ±1 MHz(2) 7 / 5 (3) dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(2) 39 / 28 (3) dB
MHz,BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±3
Selectivity, ±3 MHz(2) 38 / 38 (3) dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(2) 47 / 35 (3) dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ≥ ±5
Selectivity, ±5 MHz or more(2) 40 dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at image
Selectivity, image frequency(2) 28 dB
frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co- channel
Selectivity, image frequency
–1 MHz. Wanted signal at –67 dBm, modulated interferer 5 / 38 (3) dB
±1 MHz(2)
at ±1 MHz from image frequency, BER = 10–3
Out-of-band blocking(4) 30 MHz to 2000 MHz –10 dBm
Out-of-band blocking 2003 MHz to 2399 MHz –10 dBm
Out-of-band blocking 2484 MHz to 2997 MHz –10 dBm
Out-of-band blocking 3000 MHz to 12.75 GHz (excluding VCO frequency) –2 dBm
Wanted signal at 2402 MHz, –64 dBm. Two interferers
Intermodulation at 2405 and 2408 MHz respectively, at the given power –37 dBm
level
Spurious emissions,
Measurement in a 50-Ω single-ended load. < –59 dBm
30 to 1000 MHz(5)
Spurious emissions,
Measurement in a 50-Ω single-ended load. < –47 dBm
1 to 12.75 GHz(5)
RSSI dynamic range (6) 70 dB
RSSI accuracy ±4 dB
RSSI resolution 1 dB
2 Mbps (LE 2M)
Receiver sensitivity Measured at SMA connector, BER = 10–3 –92 dBm
Receiver saturation Measured at SMA connector, BER = 10–3 2 dBm
Difference between the incoming carrier frequency and (1)
Frequency error tolerance > (–250 / 250) kHz
the internally generated carrier frequency
Difference between incoming data rate and the internally
Data rate error tolerance > (–90/ 90) (1) ppm
generated data rate (37-byte packets)
Wanted signal at –67 dBm, modulated interferer in
Co-channel rejection(2) –8 dB
channel,BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(2) 9 / 5 (3) dB
MHz, Image frequency is at –2 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(2) 40 / 32 (3) dB
MHz, BER = 10–3

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7.14 Bluetooth Low Energy - Receive (RX) (continued)

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Wanted signal at –67 dBm, modulated interferer at ±6
Selectivity, ±6 MHz(2) 46 / 40 (3) dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at image
Selectivity, image frequency(2) 5 dB
frequency, BER = 10–3
Note that Image frequency + 2 MHz is the Co-channel.
Selectivity, image frequency
Wanted signal at –67 dBm, modulated interferer at ±2 –8 / 32 (3) dB
±2 MHz(2)
MHz from image frequency, BER = 10–3
Out-of-band blocking(4) 30 MHz to 2000 MHz –10 dBm
Out-of-band blocking 2003 MHz to 2399 MHz –10 dBm
Out-of-band blocking 2484 MHz to 2997 MHz –12 dBm
Out-of-band blocking 3000 MHz to 12.75 GHz (excluding VCO frequency) –10 dBm
Wanted signal at 2402 MHz, –64 dBm. Two interferers
Intermodulation at 2408 and 2414 MHz respectively, at the given power –38 dBm
level

(1) Actual performance exceeding Bluetooth specification

(2) Numbers given as I/C dB
(3) X / Y, where X is +N MHz and Y is –N MHz
(4) Excluding one exception at Fwanted / 2, per Bluetooth Specification
(5) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
(6) The device will saturate at -30dB.

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7.15 Bluetooth Low Energy - Transmit (TX)

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Max output power Delivered to a single-ended 50-Ω load through integrated balun 8 dBm
Output power
Delivered to a single-ended 50-Ω load through integrated balun 28 dB
programmable range

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7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless
otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements
are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Receiver sensitivity PER = 1% –98 dBm
Receiver saturation PER = 1% >3 dBm
Wanted signal at –82 dBm, modulated interferer at ±5 MHz,
Adjacent channel rejection 36 dB
PER = 1%
Wanted signal at –82 dBm, modulated interferer at ±10 MHz,
Alternate channel rejection 55 dB
PER = 1%
Wanted signal at –82 dBm, undesired signal is IEEE
Channel rejection, ±15 MHz or more 802.15.4 modulated channel, stepped through all channels 59 dB
2405 to 2480 MHz, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
57 dB
5 MHz from upper band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
63 dB
10 MHz from upper band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
63 dB
20 MHz from upper band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
66 dB
50 MHz from upper band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
60 dB
–5 MHz from lower band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
60 dB
–10 MHz from lower band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
63 dB
–20 MHz from lower band edge CW jammer, PER = 1%
Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the sensitivity level),
65 dB
–50 MHz from lower band edge CW jammer, PER = 1%
Spurious emissions, 30 MHz to 1000
Measurement in a 50-Ω single-ended load(1) –64 dBm
MHz
Spurious emissions, 1 GHz to 12.75
Measurement in a 50-Ω single-ended load(1) –49 dBm
GHz
Difference between the incoming carrier frequency and the
Frequency error tolerance > 80 ppm
internally generated carrier frequency
Difference between incoming symbol rate and the internally
Symbol rate error tolerance > 80 ppm
generated symbol rate
RSSI dynamic range 90 dB
RSSI accuracy ±4 dB

(1) Suitable for systems targeting compliance with EN 300 328, EN 300 440 class 2 (Europe), FCC CFR47, Part 15 (US) and ARIB
STD-T-66 (Japan)

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7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless
otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements
are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
(1)
Max output power Delivered to a single-ended 50-Ω load through integrated balun 8 dBm
Output power
Delivered to a single-ended 50-Ω load through integrated balun 29 dB
programmable range
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector magnitude +8 dBm setting 2 %

(1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at the upper 802.15.4 channel(s).

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7.18 Proprietary Radio Modes

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DCDC enabled unless
otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements
are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2 Mbps GFSK (HID), 320 kHz deviation
Receiver sensitivity PER = 30.8%, Payload 37 bytes -89 dBm

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7.19 2.4 GHz RX/TX CW

When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands < –36 dBm
f < 1 GHz, restricted bands ETSI < –54 dBm
Spurious emissions(1) f < 1 GHz, restricted bands FCC < –55 dBm
f > 1 GHz, including harmonics +8 dBm setting
< –30 dBm
(ETSI)
Second harmonic < –42 dBm
Harmonics (1)
Third harmonic < –42 dBm

(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

7.20 Timing and Switching Characteristics

7.20.1 Reset Timing
PARAMETER MIN TYP MAX UNIT
RSTN low duration 1 µs

7.20.2 Wakeup Timing

Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include any software overhead (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GLDO default charge current setting,
MCU, Reset/Shutdown to Active(1) 350-450 µs
VDDR capacitor fully charged (2)
MCU, Standby to Active (ready to execute
MCU, Standby to Active code from flash). DCDC ON, default 33-43 (3) µs
recharge current configuration
MCU, Standby to Active (ready to execute
MCU, Standby to Active code from flash). GLDO ON, default 33-50 (3) µs
recharge current configuration
MCU, Idle to Active Flash enabled in idle mode 3 µs
MCU, Idle to Active Flash disabled in idle mode 14 µs

(1) Wakeup time includes device ROM bootcode execution time. The wakeup time is dependent on remaining charge on VDDR capacitor
when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again.
(2) This is the best case reset/shutdown to active time (including ROM bootcode operation), for the specified GLDO charge current setting
considering the VDDR capacitor is fully charged and is not discharged during the reset and shutdown events; that is, when the device
is in reset / shutdown modes for only a very short period of time
(3) Depending on VDDR capacitor voltage level.

7.20.3 Clock Specifications

7.20.3.1 48 MHz Crystal Oscillator (HFXT)

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(4)
PARAMETER MIN TYP MAX UNIT
Crystal frequency 48 MHz
Equivalent series resistance
ESR 20 60 Ω
6 pF < CL ≤ 9 pF
Equivalent series resistance
ESR 80 Ω
5 pF < CL ≤ 6 pF
CL Crystal load capacitance(1) 5 7(2) 9 pF

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7.20.3.1 48 MHz Crystal Oscillator (HFXT) (continued)

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(4)
PARAMETER MIN TYP MAX UNIT
Start-up
Until clock is qualified 200 µs
time (3)

(1) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations.
(2) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the SysConfig.
(3) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(4) Tai-Saw TZ3908AAAO43 has been validated for CC2340R5 design.

7.20.3.2 48 MHz RC Oscillator (HFOSC)

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Frequency 48 MHz
Uncalibrated frequency accuracy ±3 %
Calibrated frequency accuracy (1) ±0.25 %

(1) Accuracy relative to the calibration source (HFXT)

7.20.3.3 32 kHz Crystal Oscillator (LFXT)

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Crystal frequency 32.768 kHz
Supported crystal load capacitance 6 12 pF
ESR 30 100 kΩ

7.20.3.4 32 kHz RC Oscillator (LFOSC)

Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Calibrated frequency 32.768 (1) kHz

(1) When using LFOSC as source for the low frequency system clock (LFCLK), the accuracy of the LFCLK-derived Real Time Clock
(RTC) can be improved by measuring LFOSC relative to HFXT and compensating for the RTC tick speed. This functionality is available
through the TI-provided Power driver.

7.21 Peripheral Characteristics

7.21.1 UART
7.21.1.1 UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
UART rate 3 MBaud

7.21.2 SPI
7.21.2.1 SPI Characteristics
Using TI SPI driver, over operating free-air temperature range (unless otherwise noted).
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
Controller Mode and Peripheral Mode (1)
12 MHz
fSCLK 2.7V ≤ VDDS < 3.8V
SPI clock frequency
1/tsclk Controller Mode and Peripheral Mode (1)
8 MHz
VDDS < 2.7V
DCSCK SCK Duty Cycle 45 50 55 %

(1) Assume interfacing with ideal SPI controller and SPI peripheral devices

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7.21.2.2 SPI Controller Mode

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tSCLK_H/ (tSPI/2) - (tSPI/2) +
SCLK High or Low time tSPI/2 ns
L 1 1
tCS.LEAD CS lead-time, CS active to clock 1 SCLK
CS lag time, Last clock to CS
tCS.LAG 1 SCLK
inactive
CS access time, CS active to
tCS.ACC 1 SCLK
PICO data out
CS disable time, CS inactive to
tCS.DIS 1 SCLK
PICO high impedance
tVALID.C
PICO output data valid time(1) SCLK edge to PICO valid,CL = 20 pF 13 ns
O

tHD.CO PICO output data hold time(2) CL = 20 pF 0 ns

(1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(2) Specifies how long data on the output is valid after the output changing SCLK clock edge

7.21.2.3 SPI Timing Diagrams - Controller Mode

CS
(inverted)

tCS, LEAD

CS

1 / fSPI
tCS, LAG

SCLK
(SPO = 0)
tSCLK_H/L tSCLK_H/L

SCLK
(SPO = 1)
tSU,CI
tHD,CI

POCI

tHD,CO
tCS, ACC tVALID,CO tCS, DIS

PICO

Controller Mode, SPH = 0

Figure 7-1. SPI Timing Diagram - Controller Mode, SPH = 0

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CS
(inverted)
tCS, LEAD

CS

1 / fSPI
tCS, LAG

SCLK
(SPO = 0)

tSCLK_H/L tSCLK_H/L

SCLK
(SPO = 1)
tSU,CI
tCS, ACC tHD,CI

POCI

tHD,CO
tVALID,CO tCS, DIS

PICO

Controller Mode, SPH = 1

Figure 7-2. SPI Timing Diagram - Controller Mode, SPH = 1

7.21.2.4 SPI Peripheral Mode

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tCS.LEAD CS lead-time, CS active to clock 1 SCLK
CS lag time, Last clock to CS
tCS.LAG 1 SCLK
inactive
CS access time, CS active to
tCS.ACC VDDS = 3.3V 35 ns
POCI data out
CS access time, CS active to
tCS.ACC VDDS = 1.8V 50 ns
POCI data out
CS disable time, CS inactive to
tCS.DIS VDDS = 3.3V 35 ns
POCI high impedance
CS disable time, CS inactive to
tCS.DIS VDDS = 1.8V 50 ns
POCI high impedance
tSU.PI PICO input data setup time 13 ns
tHD.PI PICO input data hold time 0 ns
tVALID.P
POCI output data valid time(1) SCLK edge to POCI valid,CL = 20pF, 3.3V 35 ns
O

tVALID.P
POCI output data valid time(1) SCLK edge to POCI valid,CL = 20pF, 1.8V 50 ns
O

tHD.PO POCI output data hold time(2) CL = 20pF 0 ns

(1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(2) Specifies how long data on the output is valid after the output changing SCLK clock edge

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7.21.2.5 SPI Timing Diagrams - Peripheral Mode

CS
(inverted)

tCS, LEAD

CS

1 / fSPI
tCS, LAG

SCLK
(SPO = 0)

tSCLK_H/L tSCLK_H/L

SCLK
(SPO = 1)
tSU,PI
tHD,PI

PICO

tHD,PO
tCS, ACC tVALID,PO tCS, DIS

POCI

Peripheral Mode, SPH = 0

Figure 7-3. SPI Timing Diagram - Peripheral Mode, SPH = 0

CS
(inverted)

tCS, LEAD

CS

1 / fSPI tCS, LAG

SCLK
(SPO = 0)

tSCLK_H/L tSCLK_H/L
SCLK
(SPO = 1)
tSU,PI
tHD,PI

PICO

tHD,PO
tCS, ACC tVALID,PO tCS, DIS

POCI

Peripheral Mode, SPH = 1

Figure 7-4. SPI Timing Diagram - Peripheral Mode, SPH = 1

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7.21.3 I2C
7.21.3.1 I2C
Over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL clock frequency 0 400 kHz
tHD,STA Hold time (repeated) START fSCL = 100kHz 4.0 µs
tHD,STA Hold time (repeated) START fSCL > 100kHz 0.6 µs
Setup time for a repeated
tSU,STA fSCL = 100kHz 4.7 µs
START
Setup time for a repeated
tSU,STA fSCL > 100kHz 0.6 µs
START
tHD,DAT Data hold time 0 µs
tSU,DAT Data setup time fSCL = 100kHz 250 ns
tSU,DAT Data setup time fSCL > 100kHz 100 ns
tSU,STO Setup time for STOP fSCL = 100kHz 4.0 µs
tSU,STO Setup time for STOP fSCL > 100kHz 0.6 µs
Bus free time between STOP
tBUF fSCL = 100kHz 4.7 µs
and START conditions
Bus free time between STOP
tBUF fSCL > 100kHz 1.3 µs
and START conditions
Pulse duration of spikes
tSP suppressed by input deglitch 50 ns
filter

7.21.3.2 I2C Timing Diagram

tHD,STA tSU,STA tHD,STA tBUF

SDA

ttLOWt ttHIGHt tSP

SCL

tHD,DAT
tSU,DAT tSU,STO

Figure 7-5. I2C Timing Diagram

7.21.4 GPIO
7.21.4.1 GPIO DC Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 39 66 109 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 10 21 40 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 0.91 1.11 1.27 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.59 0.75 0.91 V
IH = 1, difference between 0 → 1
GPIO input hysteresis 0.26 0.35 0.44 V
and 1 → 0 points
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 10 mA load high-drive GPIOs only, max drive setting 2.47 V
GPIO VOL at 10 mA load high-drive GPIOs only, max drive setting 0.25 V
GPIO VOH at 2 mA load standard drive GPIOs 2.52 V

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7.21.4.1 GPIO DC Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO VOL at 2 mA load standard drive GPIOs 0.20 V
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 170 262 393 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 60 110 172 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.76 1.98 2.27 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.26 1.52 1.79 V
IH = 1, difference between 0 → 1
GPIO input hysteresis 0.40 0.47 0.54 V
and 1 → 0 points
TA = 25 °C
Lowest GPIO input voltage reliably interpreted as a
VIH 0.8*VDDS V
High
Highest GPIO input voltage reliably interpreted as a
VIL 0.2*VDDS V
Low

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7.21.5 ADC
7.21.5.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25°C, VDDS = 3.0V, unless otherwise noted.(2)
Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC Power Supply and Input Range Conditions
V(Ax) Analog input voltage range All ADC analog input pins Ax 0 VDDS V

I(ADC) RES = 0x0 (12Bit mode), Fs = 1.2MSPS, Internal reference

480
single- Operating supply current OFF (ADCREF_EN = 0), VeREF+ = VDDS
μA
ended into VDDS terminal RES = 0x0 (12Bit mode), Fs = 266ksps, Internal reference ON
mode 365
(ADCREF_EN = 0), ADCREF = 2.5V
Input capacitance into a
CI GPIO 5 7 pF
single terminal
RI GPIO Input MUX ON-resistance 0.5 1 kΩ
ADC Switching Characteristics
ADC sampling frequency
FS ADC ADCREF_EN = 1, RES = 0x0 (12-bit), VDDS = 1.71V to
when using the internal ADC 267 (1) ksps
REF VDDSmax
reference voltage
ADC sampling frequency
FS ADC ADCREF_EN = 1, RES = 0x1 (10-bit), VDDS = 1.71V to
when using the internal ADC 308 (1) ksps
REF VDDSmax
reference voltage
ADC sampling frequency
FS ADC ADCREF_EN = 1, RES = 0x2 (8-bit), VDDS = 1.71V to
when using the internal ADC 400 (1) ksps
REF VDDSmax
reference voltage
ADC sampling frequency
FS EXTR ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x0 (12-bit), VDDS
when using the external ADC 1.2 (1) Msps
EF = 1.71V to VDDSmax
reference voltage
ADC sampling frequency
FS EXTR ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x1 (10-bit), VDDS
when using the external ADC 1.33 (1) Msps
EF = 1.71V to VDDSmax
reference voltage
ADC sampling frequency
FS EXTR ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x2 (8-bit), VDDS
when using the external ADC 1.6 (1) Msps
EF = 1.71V to VDDSmax
reference voltage
NCONVER
Clock cycles for conversion RES = 0x0 (12-bit) 14 cycles
T

NCONVER
Clock cycles for conversion RES = 0x1 (10-bit) 12 cycles
T

NCONVER
Clock cycles for conversion RES = 0x2 (8-bit) 9 cycles
T

RES = 0x0 (12-bit), RS = 25 Ω, Cpext = 10 pF. +/- 0.5 LSB

tSample Sampling time 250 ns
settling
Sample time required
tVSUPPLY/
when Vsupply/3 channel is 20 µs
3(sample)
selected
ADC Linearity Parameters
Integral linearity error (INL)
EI 12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8 +/- 2 LSB
for single-ended inputs
Differential linearity error
ED 12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8 +/- 1 LSB
(DNL)
12-bit Mode, External reference, VR+ = VeREF+ =
EO Offset error 1.98 LSB
VDDS, VDDS=1.71-->3.8
EO Offset error 12-bit Mode, Internal reference, VR+ = ADCREF = 2.5V 1.02 LSB
EG Gain error External Reference, VR+ = VeREF+ = VDDS , VDD= 1.71-->3.8 +/- 2 LSB
EG Gain error Internal reference, VR+ = ADCREF = 2.5V +/- 40 LSB
ADC Dynamic Parameters
ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
ENOB Effective number of bits 8 bit
0x2 (8-bit)
ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
ENOB Effective number of bits 9.9 bit
0x1 (10-bit)

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7.21.5.1 Analog-to-Digital Converter (ADC) Characteristics (continued)

Tc = 25°C, VDDS = 3.0V, unless otherwise noted.(2)
Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
ENOB Effective number of bits 11.2 bit
0x0 (12-bit)
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x2
ENOB Effective number of bits 8 bit
(8-bit)
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V} , RES = 0x1 9.6
ENOB Effective number of bits bit
(10-bit)
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0
ENOB Effective number of bits 10.4 bit
(12-bit)
ENOB Effective number of bits VDDS reference, RES = 0x0 (12-bit) 11.2 bit
Signal-to-noise and distortion ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES = 69.18
SINAD dB
ratio 0x0 (12-bit)
Signal-to-noise and distortion ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0 64.37
SINAD dB
ratio (12-bit)
Signal-to-noise and distortion 69.18
SINAD VDDS reference, RES = 0x0 (12-bit) dB
ratio
ADC External Reference
Positive external reference ADCREF_EN=0, ADC reference sourced from external
EXTREF 1.4 VDDS V
voltage input reference pin (VeREF+)
Negative external reference ADCREF_EN=0, ADC reference sourced from external
EXTREF 0 V
voltage input reference pin (VeREF-)
ADC Temperature Diode, Supply Monitor
Temp_di
ADC input channel: Temp diode voltage, Error calculated
ode
Temperature Error in temperature range: -30C to +40C, with single point +/- 3 C
Accurac
calibration (2)
y
ADC
Internal
Input: Vsupply voltage divider
VSUPPLY / accuracy for supply ADC input channel: Vsupply monitor +/- 1 %
3 monitoring
Accurac
y
ADC
Internal Vsupply voltage divider current
ADC input channel Vsupply monitor. Vsupply=VDDS=3.3V 10 µA
Input: consumption
IVsupply / 3
ADC Internal and VDDS Reference
VDDSR Positive ADC reference
ADC reference sourced from VDDS VDDS V
EF voltage
ADCREF_EN = 1, ADCREF_VSEL = 0, VDDS = 1.71V -
1.4 V
ADCRE Internal ADC Reference VDDSmax
F Voltage ADCREF_EN = 1, ADCREF_VSEL = 1, VDDS = 2.7V -
2.5 V
VDDSmax
Operating supply current into
ADCREF_EN = 1, VDDA = 1.7V to VDDAmax, ADCREF_VSEL
IADCREF VDDA terminal with internal 80 µA
= {0,1}
reference ON
Internal ADC Reference
tON ADCREF_EN = 1 2 µs
Voltage power on-time

(1) Measured with 48MHz HFOSC

(2) Using IEEE Std 1241-2010 for terminology and test methods

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7.21.6 Comparators
7.21.6.1 Ultra-Low Power Comparator
Tc = 25°C, VDDS = 3.0V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Clock frequency 32 KHz
Voltage Divider Accuracy Input voltage range is between VDDS/4 and VDDS. 98%
Offset Measured at VDDS / 2 (Errors seen when using two external inputs) ±27.3 mV
Decision time Step from –50mV to 50mV 1 3 Clock Cycle
COMP_LP disable → enable, VIN+, VIN- from pins,
Comparator enable time 70 µs
Overdrive ≥ 20mV
Including using VDDS/2 as internal reference at VIN– comparator
Current consumption 370 nA
terminal

7.22 Typical Characteristics

All measurements in this section are done with Tc = 25°C and VDDS = 3.0V, unless otherwise noted. See
Recommended Operating Conditions for device limits. Values exceeding these limits are for reference only.
7.22.1 MCU Current

4.6 11
4.4 10
4.2
9
4
8
3.8
7
Current (mA)

3.6
Current (µA)

3.4 6
3.2 5
3
4
2.8
3
2.6
2.4 2
2.2 1
2 0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 -40 -20 0 20 40 60 80 100 120
Voltage (V) Te mperature (°C)
Figure 7-6. Active Mode (MCU) Current vs. Supply Figure 7-7. Standby Mode (MCU) Current vs.
Voltage (VDDS) (Running CoreMark) Temperature ( RAM and partial register retention,
RTC)

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7.22.2 RX Current

6.4 10
6.3 9.5
6.2
9
6.1
6 8.5
5.9 8
Current [mA]

Current (mA)
5.8
7.5
5.7
5.6 7
5.5 6.5
5.4 6
5.3
5.5
5.2
5.1 5
5 4.5
4.9 4
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Te mperature (°C)
Voltage (V)
Figure 7-8. RX Current vs. Temperature (BLE Figure 7-9. RX Current vs. Supply Voltage (VDDS)
1Mbps, 2.44GHz) (BLE 1Mbps, 2.44GHz)

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7.22.3 TX Current

6.5
13.4
6.3 13
6.1 12.6

5.9 12.2

Current [mA]
11.8
Current (mA)

5.7
11.4
5.5
11
5.3
10.6
5.1 10.2
4.9 9.8
4.7 9.4
9
4.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
Te mperature (°C)
Te mperature (°C)

Figure 7-10. TX Current vs. Temperature (BLE Figure 7-11. TX Current vs. Temperature (BLE
1Mbps, 2.44GHz, 0dBm) 1Mbps, 2.44GHz, +8dBm)
19.5
18.5
17.5
16.5
15.5
Current (mA)

14.5
13.5
12.5
11.5
10.5
9.5
8.5
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Voltage (V)

Figure 7-12. TX Current vs. Supply Voltage, VDDS Figure 7-13. TX Current vs. Supply Voltage, VDDS
(BLE 1Mbps, 2.44GHz, 0dBm) (BLE 1Mbps, 2.44GHz, +8dBm)

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Table 7-1 shows typical TX current and output power for different output power settings.
Table 7-1. Typical TX Current and Output Power
2.4 GHz, VDDS = 3.0 V, DCDC=On, Temperature = 25 °C (Measured on LP-EM-CC2340R5)
txPowerTable TX Power Setting [dBm] (SmartRF
Typical Output Power [dBm] Typical Current Consumption [mA]
Index Studio)
13 8 7.7 10.7
12 7 7.1 9.5
11 6 6.3 8.9
10 5 5.5 8.3
9 4 4.5 7.9
8 3 3.7 7.5
7 2 2.4 7.1
6 1 1.0 5.4
5 0 0.4 5.1
4 -4 -3.1 4.8
3 -8 -7.3 4.5
2 -12 -10.9 4.2
1 -16 -15.1 4.0
0 -20 -19.0 3.8

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7.22.4 RX Performance

-91 -92
-92 -93
-93 -94
-94 -95
Sensitivity (dBm)

Power (dBm)
-95 -96
-96 -97
-97 -98
-98 -99
-99 -100
-100 -101
-101 -102
2360 2380 2400 2420 2440 2460 2480 2500 2400 2408 2416 2424 2432 2440 2448 2456 2464 2472 2480
Frequency (MHz) Frequency (MHz)

Figure 7-14. Sensitivity vs. Frequency (BLE 1Mbps) Figure 7-15. Sensitivity vs. Frequency (IEEE
802.15.4 PHY )
-93
-94
-95

Sensitivity (dBm) -96

-97
-98
-99
-100
-101
-102
-103
-40 -20 0 20 40 60 80 100 120
Te mperature (°C)

Figure 7-16. Sensitivity vs. Temperature (BLE Figure 7-17. Sensitivity vs. Temperature (IEEE
1Mbps, 2.44GHz) 802.15.4 PHY, 2.44GHz)
-91 -92
-92 -93

-93 -94

-94 -95
Sensitivity (dBm)
Sensitivity (dBm)

-95 -96

-96 -97

-97 -98

-98 -99

-99 -100

-100 -101

-101 -102
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 1.71 2.01 2.31 2.61 2.91 3.21 3.51 3.8
Voltage (V) Voltage (V)

Figure 7-18. Sensitivity vs. Supply Voltage (VDDS) Figure 7-19. Sensitivity vs. Supply Voltage (VDDS)
(BLE 1Mbps, 2.44GHz) (IEEE 802.15.4 PHY, 2.44GHz)

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-91
-92
-93
-94

Sensitivity (dBm)
-95
-96
-97
-98
-99
-100
-101
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Voltage (V)

Figure 7-20. Sensitivity vs. Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz, DCDC Off)

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7.22.5 TX Performance

2 10

1.5 9.5

1 9
Output Power (dBm)

Output Power (dBm)

0.5 8.5

0 8

-0.5 7.5

-1 7

-1.5 6.5

-2 6
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Te mperature (°C) Te mperature (°C)
Figure 7-21. Output Power vs. Temperature (BLE Figure 7-22. Output Power vs. Temperature (BLE
1Mbps, 2.44GHz, 0dBm) 1Mbps, 2.44GHz, +8dBm)
2 10

1.5 9.5

1 Output Power (dBm) 9

0.5 8.5
Power (dBm)

0 8

-0.5 7.5

-1 7

-1.5 6.5

-2 6
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Voltage (V) Voltage (V)
Figure 7-23. Output Power vs. Supply Voltage Figure 7-24. Output Power vs. Supply Voltage
(VDDS) (BLE 1Mbps, 2.44GHz, 0dBm) (VDDS) (BLE 1Mbps, 2.44GHz, +8dBm)
2 10

1.5 9.5

1 9
Output Power (dBm)

0.5
Power (dBm)

8.5

0 8

-0.5 7.5

-1 7

-1.5 6.5

-2 6
2360 2380 2400 2420 2440 2460 2480 2500 2360 2380 2400 2420 2440 2460 2480 2500
Frequency (MHz) Frequency (MHz)
Figure 7-25. Output Power vs. Frequency (BLE Figure 7-26. Output Power vs. Frequency (BLE
1Mbps, 0dBm) 1Mbps, +8dBm)

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7.22.6 ADC Performance

12.4

12

11.6
ENOB [bit]

11.2

10.8

10.4

10

20
25
0.01

0.02

0.05

0.1

0.2
0.3
0.5

2
3
5
7
10
Frequency [kHz]
Figure 7-28. ENOB vs. Sampling Frequency (Vin=
Figure 7-27. ENOB vs. Input Frequency (Internal
3V Sine Wave, Internal Reference, Fin=Fs/10)
Reference)
11.5
11.4
11.3
11.2
11.1
11
10.9
ENOB (bit)

10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
1

2
3
5

10

20
30
50

100

200

500

1000
1200
0.1

0.2

0.5

Frequency (kHz)

Figure 7-29. ENOB vs. Input Frequency (External Figure 7-30. ENOB vs. Sampling Frequency (Vin =
Reference = 3.0V) 3V Sine Wave, External Reference = 3.0V, Fin=Fs/10
0.6
0.5
0.4
0.3
0.2
DNL (LSB)

0.1
0
-0.1
-0.2
-0.3
-0.4
0 512 1024 1536 2048 2560 3072 3584 4095
ADC Code
Figure 7-31. INL vs. ADC Code (Vin= 3V Sine Wave, Figure 7-32. DNL vs. ADC Code (Vin= 3V Sine
Internal Reference, 200ksps) Wave, Internal Reference, 200ksps)

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1.02 1.004
1.016
1.012
1.003
1.008
1.004
Voltage (V)

Voltage (V)
1 1.002
0.996
0.992
1.001
0.988
0.984
0.98 1
-40 -25 -10 5 20 35 50 65 80 95 110 125 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Te mperature (°C) Voltage (V)

Figure 7-33. ADC Accuracy vs. Temperature (Vin= Figure 7-34. ADC Accuracy vs. Supply Voltage
1V, Internal Reference, 200ksps) (Vin= 1V, Internal Reference, 200ksps)

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8 Detailed Description
8.1 Overview
Section 4 shows the core modules of the CC2340R device.
8.2 System CPU
The CC2340R SimpleLink™ Wireless MCU contains an Arm® Cortex®-M0+ system CPU, which runs the
application, the protocol stacks, and the radio. The Cortex-M0+ processor is built on a highly area and power
optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor offers
multiple benefits to developers including:
• Ultra-low power, energy efficient operation
• Deterministic, high-performance interrupt handling for time-critical applications
• Upward compatibility with the Cortex-M processors family
The Cortex-M0+ processor provides the excellent performance expected of a modern 32-bit architecture core,
with higher code density than other 8-bit and 16-bit microcontrollers. Its features include the following:
• ARMv6-M architecture optimized for small-footprint embedded applications
• Subset of Arm Thumb/Thumb-2 mixed 16- and 32-bit instructions delivers the high performance expected of
a 32-bit Arm
• Single-cycle multiply instruction
• VTOR supporting offset of the vector table base address
• Serial Wire debug with HW break-point comparators
• Ultra-low-power consumption with integrated sleep modes
• SysTick timer
• 48MHz operation
• 0.99DMIPS/MHz
Additionally, the CC2340R devices are compatible with all ARM tools and software.
8.3 Radio (RF Core)
The low-power RF Core (LRF) implements a high performance and highly flexible RF sub system containing
RF and baseband circuitry in addition to a software defined digital radio (LRFD). LRFD provides a high-level,
command-based API to the main CPU and handles all of the timing critical and low-level details of many
different radio PHYs. Several signals are also available to control external circuitry such as RF switches or range
extenders autonomously.
The software-defined modem is not programmable by customers but is instead loaded with precompiled images
provided in the radio driver in the SimpleLink™ Low Power F3 software development kit (SDK) for the CC23xx
devices. This mechanism allows the radio platform to be updated for support of future versions of standards with
over-the-air (OTA) updates while still using the same silicon. LRFD stores the code images in the RF SRAM and
does not make use of any ROM memory, thus image loading from NV memory only occurs once after boot and
also, no patching is required when exiting power modes.

8.3.1 Bluetooth 5.3 Low Energy

The RF Core offers full support for Bluetooth 5.3 Low Energy, including the high-speed 2Mbps physical layer and
the 500kbps and 125kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.3 stack or through
a high-level Bluetooth API.
The new high-speed mode allows data transfers up to 2Mbps, twice the speed of Bluetooth 4.2 and five times
the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers
significant improvements in energy efficiency and wireless coexistence with reduced radio communication time.

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Bluetooth 5.3 also enables unparalleled flexibility for adjustment of speed and range based on application
needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible
at 2Mbps, enabling the development of applications using voice, audio, imaging, and data logging that were
not previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster
responses, richer engagement, and longer battery life. Bluetooth 5.3 enables fast, reliable firmware updates.
8.3.2 802.15.4 (Thread and Zigbee)
Through a dedicated IEEE radio API, the RF Core supports the 2.4GHz IEEE 802.15.4-2011 physical layer
(2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread and Zigbee protocols. TI also provides
royalty-free protocol stacks for Thread and Zigbee, enabling a robust end-to end solution.
8.4 Memory
Up to 512KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-system
programmable and erasable. A special flash memory sector must contain a Customer Configuration section
(CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done
through the ccfg.c source file that is included in all TI provided examples.
Up to 64KB ultra-low leakage system static RAM (SRAM) can be used for both storage of data and execution of
code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode
power consumption numbers. System SRAM is always initialized to zeroes upon code execution during boot.
The ROM includes device bootcode firmware handling initial device trimming operations, security configurations,
and device lifecycle management. The ROM also contains a serial (SPI and UART) bootloader that can be used
for the initial programming of the device.

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8.5 Cryptography
The CC2340R device comes with AES-128 cryptography hardware accelerator, reducing code footprint and
execution time for cryptographic operations. It also has the benefit of being lower power and improves availability
and responsiveness of the system because the cryptography operations run in a background hardware thread.
The AES hardware accelerators supports the following block cipher modes and message authentication codes:
• AES ECB encrypt
• AES CBC encrypt
• AES CTR encrypt/decrypt
• AES CBC-MAC
• AES GCM
• AEC CCM (uses a combination of CTR + CBC-MAC hardware via software drivers)
The AES hardware accelerator can be fed with plaintext/ciphertext from either CPU or using DMA. Sustained
throughput of one 16 byte ECB block per 23 cycles is possible corresponding to > 30Mbps.
The CC2340R device supports Random Number Generation (RNG) using on-chip analog noise as the
non-deterministic noise source for the purpose of generating a seed for a cryptographically secure counter
deterministic random bit generator (CTR-DRBG) that in turn is used to generate random numbers for keys,
initialization vectors (IVs), and other random number requirements. Hardware acceleration of AES CTR-DRBG is
supported.
The CC2340R device includes a complete SHA 256 library in ROM, reducing the code footprint of the
application. Uses cases may include generating digests for use in digital signature algorithms, data integrity
checks, and password storage.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform.
8.6 Timers
A large selection of timers are available as part of the CC2340R device. These timers are:

• Real-Time Clock (RTC)

The RTC is a 67-bit, 2-channel timer running on the LFCLK system clock. The RTC is active in STANDBY
and ACTIVE power states. When the device enters the RESET or SHUTDOWN state the RTC is reset.
The RTC accumulates time elapsed since reset on each LFCLK. The RTC counter is incremented by LFINC
at a rate of 32.768kHz. LFINC indicates the period of LFCLK in μs, with an additional granularity of 16
fractional bits.
The counter can be read from two 32-bit registers. RTC.TIME8U has a range of approximately 9.5 hours with
an LSB representing 8 microseconds. RTC.TIME524M has a range of approximately 71.4 years with an LSB
representing 524 milliseconds.
There is hardware synchronization between the system timer (SYSTIM) and the RTC so that the multichannel
and higher resolution SYSTIM remains in synchronization with the RTC’s time base.
The RTC has two channels: one compare channel and one capture channel and is capable of waking the
device out of the standby power state. The RTC compare channel is typically used only by system software
and only during the standby power state.
• System Timer (SYSTIM)
The SYSTIM is a 34-bit, 5-channel wrap-around timer with a per-channel selectable 32b slice with either
a 1μs resolution and 1h11m35s range or 250ns resolution and 17m54s range. All channels support both
capture and single-shot compare (posting an event) operation. One channel is reserved for system software,
three channels are reserved for radio software and one channel is freely available to user applications.
For software convenience, a hardware synchronization mechanism automatically ensures that the RTC and
SYSTIM share a common time base (albeit with different resolutions/spans). Another software convenience

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feature is that SYSTIM qualifies any submitted compare values so that the timer channel will immediately
trigger if the submitted event is in the immediate past (4.294s with 1μs resolution and 1.049s with 250ns
resolution).
• General Purpose Timers (LGPT)
The CC2340R device provides up to four LGPTs with 3 × 16 bit timers and 1× 24 bit timer, all running up to
48MHz. The LGPTs support a wide range of features such as:
– Three capture/compare channels
– One-shot or periodic counting
– Pulse width modulation (PWM)
– Time counting between edges and edge counting
– Input filter implemented on each of the channels for all timers
– IR generation feature available on Timer-0 and Timer-1
– Dead band feature available on Timer-1
The timer capture/compare and PWM signals are connected to IOs through the IO controller module (IOC)
and the internal timer event connections to CPU, DMA, and other peripherals are through the event fabric,
which allows the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. Two
LGPTs (2× 16-bit timers) support quadrature decoder mode to enable buffered decoding of quadrature-
encoded sensor signals. The LGPTs are available in device Active and Idle power modes.
Table 8-1. Timer Comparison
Feature Timer 0 Timer 1 Timer 2 Timer 3

Counter Width 16-bit 16-bit 16-bit 24-bit

Quadrature Decoder Yes No Yes No

Park Mode on Fault No Yes No No

Programmable Dead- No Yes No No

Band Insertion

• Table 8-2. Timer Availability

Part Number Timer 0 Timer 1 Timer 2 Timer 3

CC2340R21 Yes Yes No No

CC2340R22 Yes Yes Yes Yes

CC2340R52 Yes Yes Yes Yes

CC2340R53 Yes Yes Yes Yes

• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. Upon
counter expiry, the watchdog timer resets the device when periodic monitoring of the system components
and tasks fails to verify proper functionality. The watchdog timer runs on a 32kHz clock rate and operates in
device active, idle, and standby modes and cannot be stopped once enabled.
8.7 Serial Peripherals and I/O
The CC2340R device provides 1xUART, 1xSPI, and 1xI2C serial peripherals.
The SPI module supports both SPI controller and peripheral up to 12MHz with configurable phase and polarity.
The UART module implements universal asynchronous receiver and transmitter functions. They support flexible
baud-rate generation up to a maximum of 3Mbps and IRDA SIR mode of operation.
The I2C module is used to communicate with devices compatible with the I2C standard. The I2C interface can
handle 100kHz and 400kHz operation and can serve as both controller and target.

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The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a fixed manner over DIOs. All digital I/Os are interrupt and wake-up capable, have
a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull, open-drain, or open-source.
Some GPIOs have high-drive capabilities, which are marked in bold in Pin Configurations and Functions.
For more information, see the CC23xx SimpleLink™ Wireless MCU Technical Reference Manual.
8.8 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2340R device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
8.9 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Channel operation of up to 8 channels, with 6 channels having dedicated peripheral interface and 2 channels
having ability to be triggered via configurable events.
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
8.10 Debug
On-chip debug is supported through the serial wire debug (SWD) interface, which is an ARM bi-directional 2-wire
protocol that communicates with the JTAG Test Access Port (TAP) controller and allows for complete debug
functionality. SWD is fully compatible with Texas Instruments' XDS family of debug probes.

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8.11 Power Management

To minimize power consumption, the CC2340R supports a number of power modes and power management
features (see Table 8-3).
Table 8-3. Power Modes
SOFTWARE CONFIGURABLE POWER MODES (1) RESET PIN
MODE
ACTIVE IDLE STANDBY SHUTDOWN HELD

CPU Active Off Off Off Off

Flash On Available Off Off Off
SRAM On On Retention Off Off
Radio Available Available Off Off Off
Supply System On On Duty Cycled Off Off
CPU register retention Full Full Full (2) No No
SRAM retention Full Full Full Off Off
48 MHz high-speed clock
HFOSC (tracks HFXT) HFOSC (tracks HFXT) Off Off Off
(HFCLK)
32 kHz low-speed clock (LFCLK) LFXT or LFOSC LFXT or LFOSC LFXT or LFOSC Off Off
IOC, BATMON,
Peripherals Available Available Off Off
RTC, LPCOMP
Wake-up on RTC N/A Available Available Off Off
Wake-up on pin edge N/A Available Available Available Off
Wake-up on reset pin On On On On On
Brownout detector (BOD) On On Duty Cycled Off Off
Power-on reset (POR) On On On On On
Watchdog timer (WDT) Available Available Available Off Off

(1) “Available” indicates that the specific IP or feature can be enabled by user application in the corresponding device operating modes.
“On” indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the
corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user
application in the corresponding device operating mode.
(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode

In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power
consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU.
In Idle mode the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active.
Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on state of the DMA and debug
subsystem.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or
comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the
device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up
again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby
mode.
In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with
the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from
shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in
this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in
this mode are the latched I/O state, 3V register bank, and the flash memory contents.

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Note
The power, RF and clock management for the CC2340R device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in
the TI-provided drivers that are part of the CC2340R software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source
code.

8.12 Clock Systems

The CC2340R device has the following internal system clocks.
The 48MHz HFCLK is used as the main system (MCU and peripherals) clock. This is driven by the internal
48MHz RC Oscillator (HFOSC), which can track its accuracy against an external 48MHz crystal (HFXT). Radio
operation requires an external 48MHz crystal.
The 32.768kHz LFCLK is used as the internal low-frequency system clock. It is used for the RTC, the watchdog
timer (if enabled in standby power mode), and to synchronize the radio timer before or after Standby power
mode. LFCLK can be driven by the internal 32.8kHz RC Oscillator (LFOSC), a 32.768kHz watch-type crystal, or
clock input in LFXT bypass mode. When using a crystal or the internal RC oscillator, the device can output the
32kHz LFCLK signal to other devices, thereby reducing the overall system cost.
8.13 Network Processor
Depending on the product configuration, the CC2340R device can function as a wireless network processor
(WNP), a device running the wireless protocol stack with the application running on a separate host MCU, or as
a system-on-chip (SoC), with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.

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9 Application, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Reference Designs

The following reference designs should be followed closely when implementing designs using the CC2340R
devices.
Special attention must be paid to RF component placement, decoupling capacitors, and DCDC regulator
components, as well as ground connections for all of these.

LP-EM-CC2340R5 Design The CC2340R5 LaunchPad Design Files contain detailed schematics and layouts
Files to build application-specific boards using the CC2340R devices in the 5mm x 5mm
RKP package.
LP-EM-CC2340R5- The CC2340R5 RGE 4x4 LaunchPad Design Files contain detailed schematics
RGE-4x4-IS24 Design Files and layouts to build application-specific boards using the CC2340R devices in the
4mm x 4mm RGE package. The CC2340R5x and CC2340R2x devices in RGE
packages are pin-to-pin compatible.
Sub-1 GHz and The antenna kit allows real-life testing to identify the optimal antenna for your
2.4 GHz Antenna Kit for application. The antenna kit includes 16 antennas for frequencies from 169MHz to
LaunchPad™ Development 2.4GHz, including:
Kit and SensorTag • PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868MHz and 915MHz combined with 2.4GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad
Development Kits and SensorTags.

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9.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are two recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T J = ψJT × P + Tcase (1)
2. From board temperature:
T J = ψJB × P + Tboard (2)

P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Thermal Resistance Characteristics.
Example:
In this example, we assume a simple use case where the radio is transmitting continuously at 0dBm output
power. Let us assume we want to maintain a junction temperature equal or less than 85°C and the supply
voltage is 3V. Using Equation 1, the temperature difference between the top of the case and junction
temperature is calculated. To calculate P, look up the current consumption for Tx at 85°C. At 85°C the current
consumption is approximately 5.5mA. This means that P is 5.5mA × 3V = 16.5mW.
The maximum case temperature to maintain and junction temperature of 85°C is then calculated as:

Tcase < T j − 0.4°C W × 23.4mW = 84.99°C (3)

For various application use cases, current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, and so on. Typically, the easiest way to find the peak current consumption, and thus
the peak power dissipation in the device, is to measure as described in the Measuring CC13xx and CC26xx
Current Consumption application report.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.

10.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or
date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, X is in
preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:

X Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.

Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RKP).
For orderable part numbers of devices in the RHB (5-mm x 5-mm) package type, see the Package Option
Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com), or contact your TI
sales representative.
CC2340 R 5 2 E 0 RKP R

PREFIX R = Large Reel

X = Experimental Device PACKAGE
Blank = Qualified Device RKP = 5mm x 5mm QFN
DEVICE RGE = 4mm x 4mm QFN
SimpleLink™ 2.4GHz YBG = 2.2mm x 2.6mm WCSP
Wireless MCU PRODUCT REVISION
TEMPERATURE
CONFIGURATION
E = 125°C Ambient
R = Regular (+8dBm)
N = 85°C Ambient
FLASH SIZE SRAM SIZE
2 = 256KB 1 = 28KB
5 = 512KB 2 = 36KB
3 = 64KB

Figure 10-1. Device Nomenclature

10.2 Tools and Software

The CC2340R device is supported by a variety of software and hardware development tools.
Development Kit

CC2340R5 The CC2340R5 LaunchPad™ Development Kit enables development of high-

LaunchPad™ performance wireless applications that benefit from low-power operation. The kit features
Development Kit the CC2340R53 SimpleLink Wireless MCU, which allows you to quickly evaluate and
prototype 2.4GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee, and

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Thread. The kit works with the LaunchPad ecosystem, enabling additional functionality
like sensors, display, and more.

Software

SimpleLink™ Low The SimpleLink™ Low Power F3 software development kit (SDK) provides a complete
Power F3 software package for the development of wireless applications on the CC2340R family of devices.
development kit The SDK includes a comprehensive software package for the CC2340R device, including
(SDK) the following protocol stacks:
• Bluetooth Low Energy 5.3
• Zigbee 3.x
The SimpleLink Low Power F3 SDK is part of TI’s SimpleLink MCU platform, offering
a single development environment that delivers flexible hardware, software, and tool
options for customers developing wired and wireless applications. For more information
about the SimpleLink MCU Platform, visit https://www.ti.com/simplelink.

Development Tools
Code Composer Code Composer Studio is an integrated development environment (IDE) that supports TI's
Studio™ Integrated Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
Development suite of tools used to develop and debug embedded applications. It includes an optimizing
Environment (IDE) C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling).
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit,
Studio™ Cloud and build CCS projects. After you have successfully built your project, you can download
IDE and run on your connected LaunchPad. Basic debugging, including features like setting
breakpoints and viewing variable values, is now supported with CCS Cloud.

IAR Embedded IAR Embedded Workbench® is a set of development tools for building and debugging
Workbench® for embedded system applications using Assembler, C and C++. It provides a completely
Arm® integrated development environment that includes a project manager, editor, and build
tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™, and Segger J-Link™. IAR is also supported out-of-the-box on
most software examples provided as part of the SimpleLink SDK.

SmartRF™ Studio SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers
of RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing
and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF
device. Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states

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• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches

UniFlash UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash
has a GUI, command line, and scripting interface. UniFlash is available free of charge.

10.2.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering
flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more at ti.com/simplelink.
10.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder (CC2340R5). In the upper right corner, click on Alert me to register and receive
a weekly digest of any product information that has changed. For change details, review the revision history
included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer

TI Resource Explorer Software examples, libraries, executables, and documentation are available for your
device and development board.

Errata

CC2340R Silicon The silicon errata describes the known exceptions to the functional specifications for
Errata each silicon revision of the device and description on how to recognize a device revision.

Application Reports
All application reports for the CC2340R devices are found on the device product folder (CC2340R2 or
CC2340R5).
Technical Reference Manual (TRM)

CC23xx SimpleLink™ Wireless MCU The TRM provides a detailed description of all modules and peripherals
TRM available in the device family.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
SimpleLink™, LaunchPad™, Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas
Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systems GmbH.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Bluetooth® is a registered trademark of Bluetooth SIG.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.

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Wi-Fi® is a registered trademark of Wi-Fi Alliance.

IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2024) to Revision E (September 2024) Page
• Updated the SDK name throughout the data sheet............................................................................................1
• Updated CC2340R53E0RKPR from Preview to Released.................................................................................2
• Updated CC2340R53N0RKPR from Preview to Released................................................................................ 2
• Corrected pin pitch in pin diagram title............................................................................................................... 6
• Corrected pin pitch in diagram title..................................................................................................................... 8
• Updated the description of software and tools................................................................................................. 57

Changes from Revision C (June 2023) to Revision D (June 2024) Page

• Combined all CC2340R family of devices to a single data sheet.......................................................................1
• Added all devices in CC2340R family................................................................................................................ 2
• Changed the comparison table to the CC2340R family of devices.................................................................... 5
• Added preview for YBG package....................................................................................................................... 8
• Removed "Untrimmed brownout rising threshold"............................................................................................ 19
• Updated parameter name of "Trimmed brownout rising threshold"..................................................................19
• Updated parameter name of "Trimmed brownout falling threshold"................................................................. 19
• Changed Temperature Sensor " Accuracy"...................................................................................................... 19
• Changed DCDC "Idle Current - Supply Systems and RAM powered, flash disabled, DMA disabled "............ 20
• Changed DCDC "Idle Current - Supply Systems and RAM powered, flash disabled, DMA enabled"..............20
• Changed DCDC "Idle Current - Supply Systems and RAM powered, flash enabled, DMA disabled"..............20
• Changed DCDC "Idle Current - Supply Systems and RAM powered, flash enabled, DMA enabled".............. 20
• Changed GLDO "Idle Current - Supply Systems and RAM powered, flash disabled, DMA disabled"............. 20
• Changed GLDO "Idle Current - Supply Systems and RAM powered, flash disabled, DMA enabled"..............20
• Changed GLDO "Idle Current - Supply Systems and RAM powered, flash enabled, DMA disabled"..............20
• Changed GLDO "Idle Current - Supply Systems and RAM powered, flash enabled, DMA enabled "............. 20
• Changed "Reset current"..................................................................................................................................20
• Changed "Shutdown Current"...........................................................................................................................20
• Changed "Radio transmit current at -8 dBm"................................................................................................... 21
• Changed "Radio transmit current at 0 dBm, DCDC OFF"................................................................................ 21
• Changed "Radio transmit current at +4 dBm"...................................................................................................21
• Changed "Flash write time".............................................................................................................................. 21
• Change "Frequency error tolerance" for 125kbps BLE PHY............................................................................ 23
• Change "Frequency error tolerance" for 500kbps BLE PHY............................................................................ 23
• Changed "Frequency error tolerance" for 1Mbps BLE PHY.............................................................................23

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• Changed "Data rate error tolerance" for 1Mbps BLE PHY............................................................................... 23

• Updated footnote 1 in Section 8.14 "Bluetooth Low Energy - Receive (RX)"...................................................23
• Changed "Selectivity, +3MHz" for 1Mbps BLE PHY.........................................................................................23
• Changed "Frequency error tolerance" for 2Mbps BLE PHY.............................................................................23
• Changed "Data rate error tolerance" for 2Mbps BLE PHY............................................................................... 23
• Changed "f > 1 GHz, including harmonics"...................................................................................................... 30
• Changed min value of "Crystal load capacitance"............................................................................................30
• Removed "Temperature coefficient"................................................................................................................. 31
• Changed "SPI clock frequency"........................................................................................................................31
• Added footnote (1)............................................................................................................................................31
• Changed "CS access time, CS active to POCI data out – VDDS=3.3V"..........................................................33
• Changed "CS access time, CS active to POCI data out – VDDS=1.8V"..........................................................33
• Changed "CS disable time, CS inactive to POCI high impedance – VDDS=3.3V".......................................... 33
• Changed "CS disable time, CS inactive to POCI high impedance – VDDS=1.8V".......................................... 33
• Changed "PICO input data setup time"............................................................................................................ 33
• Changed "POCI output data valid time" at 3.3V............................................................................................... 33
• Removed "(4)" from test conditions.................................................................................................................. 33
• Changed "POCI output data valid time" at 1.8V............................................................................................... 33
• Removed "(4)" from test conditions.................................................................................................................. 33
• Added "Data setup time" at f_SCL = 100kHz................................................................................................... 35
• Changed "Data setup time" at f_SCL > 100kHz...............................................................................................35
• Changed "GPIO pullup current" at 1.8V........................................................................................................... 35
• Changed "GPIO pulldown current" at 1.8V.......................................................................................................35
• Changed "GPIO low-to-high input transition, with hysteresis" at 1.8V............................................................. 35
• Changed "GPIO high-to-low input transition, with hysteresis" at 1.8V............................................................. 35
• Changed "GPIO input hysteresis" at 1.8V........................................................................................................ 35
• Changed "GPIO VOH at 10 mA load" at 3.0V.................................................................................................. 35
• Changed "GPIO VOL at 10 mA load" at 3.0V...................................................................................................35
• Changed "GPIO VOH at 2 mA load" at 3.0V....................................................................................................35
• Changed "GPIO VOL at 2 mA load" at 3.0V.....................................................................................................35
• Changed "GPIO pullup current" at 3.8V........................................................................................................... 35
• Changed "GPIO pulldown current" at 3.8V.......................................................................................................35
• Changed "GPIO low-to-high input transition, with hysteresis" at 3.8V............................................................. 35
• Changed "GPIO high-to-low input transition, with hysteresis" at 3.8V............................................................. 35
• Changed "GPIO input hysteresis" at 3.8V........................................................................................................ 35
• Added "Temperature Error" of Temp diode inside ADC....................................................................................37
• Changed "Ultra-low power comparator current consumption"..........................................................................39
• Added performance plots................................................................................................................................. 39
• Corrected timer features...................................................................................................................................50
• Updated descriptions........................................................................................................................................ 53

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 61

Product Folder Links: CC2340R2 CC2340R5
CC2340R2, CC2340R5
SWRS272E – APRIL 2023 – REVISED SEPTEMBER 2024 www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

62 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: CC2340R2 CC2340R5

 PACKAGE OUTLINE
YBG0028-C01 SCALE 5.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.5 MAX
C

SEATING PLANE
0.20 0.05 C
0.14

1.6 TYP

SYMM

E
D: Max = 2.622 mm, Min = 2.582 mm

D SYMM E: Max = 2.206 mm, Min = 2.166 mm

2
TYP C

B
0.4 TYP
A

1 2 3 4 5
0.27
28X
0.23
0.4 TYP
0.015 C A B

4230507/A 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YBG0028-C01 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP
28X ( 0.23)
1 2 3 4 5

A
(0.4) TYP

C
SYMM

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 30X

0.05 MAX 0.05 MIN METAL UNDER

( 0.23) SOLDER MASK
METAL

EXPOSED ( 0.23)
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL METAL OPENING
SOLDER MASK
NON-SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE

4230507/A 02/2024

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YBG0028-C01 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

28X ( 0.25)
1 2 3 4 5 (R0.05) TYP

A
(0.4) TYP

C
SYMM

METAL
TYP E

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 30X

4230507/A 02/2024

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CC2340R21N0RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2340 Samples
R21
CC2340R22E0RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 CC2340 Samples
R22
CC2340R22N0RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2340 Samples
R22
CC2340R52E0RGER ACTIVE VQFN RGE 24 3000 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 125 CC2340 Samples
R52
CC2340R52E0RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 CC2340 Samples
R52
CC2340R52N0RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2340 Samples
R52
CC2340R52N0RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2340 Samples
R52

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2024

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CC2340R5 :

• Automotive : CC2340R5-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Oct-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2340R21N0RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
CC2340R22E0RKPR VQFN RKP 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
CC2340R22N0RKPR VQFN RKP 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
CC2340R52E0RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
CC2340R52E0RKPR VQFN RKP 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
CC2340R52N0RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
CC2340R52N0RKPR VQFN RKP 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Oct-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC2340R21N0RGER VQFN RGE 24 3000 367.0 367.0 35.0
CC2340R22E0RKPR VQFN RKP 40 3000 367.0 367.0 35.0
CC2340R22N0RKPR VQFN RKP 40 3000 367.0 367.0 35.0
CC2340R52E0RGER VQFN RGE 24 3000 367.0 367.0 35.0
CC2340R52E0RKPR VQFN RKP 40 3000 367.0 367.0 35.0
CC2340R52N0RGER VQFN RGE 24 3000 367.0 367.0 35.0
CC2340R52N0RKPR VQFN RKP 40 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RKP 40 VQFN - 1 mm max height
5 x 5, 0.4 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229305/A

www.ti.com
 PACKAGE OUTLINE
RKP0040B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

B 5.1 A
4.9

PIN 1 INDEX AREA

5.1
4.9

C
1 MAX

SEATING PLANE

0.05 0.08 C
0.00
3.6
3.4
(0.1) TYP
11 20

36X 0.4
10
21

41 SYMM
4X
3.6

1
30 40X 0.25
0.15
0.1 C A B
PIN1 ID 40 31 0.05 C
(OPTIONAL)
SYMM
40X 0.5
0.3
4219083/A 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RKP0040B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
2X (4.8)
( 3.5)
SYMM

40X (0.6) 40 31

40X (0.2)

1
30

36X (0.4)

SYMM 2X
(4.8)
2X (0.6)

2X (0.9)

10 21

(R 0.05) TYP
11 20
(Ø 0.2) VIA
TYP
2X (0.9283) 2X (0.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL SOLDER MASK

SOLDERMASK
EXPOSED METAL EXPOSED SOLDER MASK
OPENING
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219083/A 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RKP0040B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

2X (4.8)

9X
SYMM ( 1)

40X (0.6) 40 31

40X (0.2)

1
30

36X (0.4)

SYMM 2X
(4.8)

2X
(1.2)

10 21

(R 0.05) TYP
11 20

2X (1.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
74% PRINTED COVERAGE BY AREA
SCALE: 15X

4219083/A 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4204104/H
 PACKAGE OUTLINE
RGE0024B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A
3.9

0.5
0.3

PIN 1 INDEX AREA

4.1
3.9
0.3
0.2

DETAIL
OPTIONAL TERMINAL
TYPICAL

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C

2X 2.5
2.45 0.1 (0.2) TYP
7 12
EXPOSED
SEE TERMINAL
THERMAL PAD
DETAIL
6 13

2X 25 SYMM
2.5

1 18
0.3
20X 0.5 24X
0.2
24 19 0.1 C A B
SYMM
PIN 1 ID
(OPTIONAL) 0.05
0.5
24X
0.3

4219013/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGE0024B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 2.45)
SYMM

24 19
24X (0.6)

1
18

24X (0.25)

(R0.05)
TYP 25 SYMM

(3.8)

20X (0.5)
13
6

( 0.2) TYP
VIA
7 12
(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219013/A 05/2017
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGE0024B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)
(0.64) TYP
24 19

24X (0.6)

1
25
18

24X (0.25)

(R0.05) TYP (0.64)

TYP
SYMM

(3.8)

20X (0.5)
13
6

METAL
TYP

7 12
SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4219013/A 05/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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