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CIA 1-Dpco Answer

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24 views

CIA 1-Dpco Answer

Uploaded by

knightneptune05
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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2-Marks

1. Define a Combinational and Sequential circuit.

2. What is priority encoder?

3. Distinguish between a Demultiplexer and Decoder.

4. Define half adder and half subtractor.


5. What is multiplexer?

6. Differentiate between a flip-flop and latch

7. What is ring counter?

8. Compare Moore and Melay models.

9. What is race around condition in JK flip-flop?


10. Distinguish between synchronous and asynchronous sequential circuit.

11. What is the function of arithmetic and logic unit?

12. Define computer architecture.

13. What is meant by CPU?

14. Mention the instructions supported by IAS computer.

15. What is spilling registers?


16. What is the role of MAR and MDR?

17. List the types of operations supported by MIPS instruction set architecture.

12-Marks

1. Simplify the following Boolean function F using k-map method:


i) F(A,B,C,D) = Σ (1,4,5,6,12,14,15)
ii) F(A,B,C,D) = Σ (0,1,2,4,5,7,11,15)
iii) F(A,B,C,D) = Σ (2,3,10,11,12,13,14,15)

2. Express the following function in sum of min-terms and product of max-terms F(x,y,z) = x+yz.
3. Simplify the following Boolean function F together with don’t care condition using Karnaugh map
method.
i) F(A,B,C,D) = Σ (0,6,8,13,14), d(A,B,C,D) = Σ (2,4,10)
ii) F(A,B,C,D) = Σ (0,2,4,5,8,14,15), d(A,B,C,D) = Σ (7,10,13)
iii) F(A,B,C,D) = Σ (4,6,7,8,12,15), d(A,B,C,D) = Σ (2,3,5,10,11,14)
4. Analyze the given logic diagram.

5. i) Implement the following Boolean function with NAND gates.


F(x,y,z) = Σ (1,2,3,4,5,7)
ii) Implement the following Boolean function with NOR-NOR logic.
F(A,B,C) =  M (0,2,4,5,6)

6. Simplify F(A,B,C,D) = Σ (0,1,2,5,8,9,10) in sum of products and product of sums using k-map.
7. Design a full adder and implement with two half adders and an OR gate.
8. What is BCD adder? Design an adder to perform arithmetic addition of two decimal digits in BCD.
9. Design 2-bit Magnitude comparator using gates.
10. Implement the following multiple output combinational logic circuit using a 4 line to 16 line decoder
f1 = Σ (1,2,4,7,8,11,12,13), f2 = Σ (2,3,9,11), f3 = Σ (10,12,13,14,), f4 = Σ (2,4,8)

11. Realize F(w,x,y,z) = Σ (1,4,6,7,8,9,10,11,15) using 4 to 1 MUX.

12. Implement full subtractor using DEMUX.


13. Describe the operation of JK flip-flop
14. A sequential circuit with 2 D flip-flops A & B and input X and output Y is specified by the following
next state and output equations: A(t+1) = AX+BX, B(t+1) = A’X, Y = (A+B)X’
i). Draw the logic diagram.
ii). Derive the state table.
iii). Derive the state diagram.
15. For a four bit even parity bit generator, input comes serially. The four bits of the input sequence are
to be examined by the circuit and circuit produces a parity bit which is to be added in the original
sequence. The circuit should get ready for receiving another four bits after producing a parity bit for
the last sequence. Draw the state diagram and write down the state transition table.

16. A sequential circuit with 2 D flip-flops A & B and 2 inputs x and y and output z is specified by the
following input equations:
A(t+1) = x’y+xA, B(t+1) = x’B+xA, z = B
Draw the logic diagram of the circuit. Derive the state table and state diagram and state whether it is
a Melay or Moore machine.
17. Design a sequential circuit with JK flip-flops to satisfy the following state equations: A(t+1) =
A’B’CD+A’B’C+ACD+AC’D’, B(t+1) = A’C+CD’+A’BC’, C(t+1) = B, D(t+1) =D’.
18. Draw a six stage ring counter and explain its operation. Mention about the use of presetting the
counter.
19. Design a 3-bit asynchronous ripple counter using T-flipflop and explain its operation.
20. Illustrate a four bit parallel in serial out shift registers.
21. Explain in detail about SIPO and PIPO shift registers.
22. Describe in detail about 4-bit Johnson counter.
23. Design a MOD-5 synchronous counter using JK flip-flops and implement it.
24. Design a synchronous decade counter using D flip-flop.
25. Illustrate the functional units of digital computer.
26. Describe about the Von Neumann architecture with neat diagram.

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