2.

Deseribe about the functional diagram of 555 timer and its Monostable Operation of 555
timer?

Figure (1) gives the functional diagram for 555 IC timer. Referring to Figure (1), three 5 ka
internal resistors act as voltage divider, providing bias voltage of (2/3) V to the upper comparator
(UC) and (1/3) V« to the lower comparator (LC), where Va is the supply voltage. Since these two
voltages fix the necessary comparator threshold voltage, they also aid in determining the timing
interval. It is possible to vary time electronically too, by applying a modulation voltage to the
control voltage input terminal (pin 5). In applications where no such modulation is intended, it is
recommended by manufacturers that a capacitor (0.01 uF) be connected between control voltage
terminal (pin 5) and ground to by-pass noise or ripple from the supply

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Figure: Functional diagram of 55 timer

In the standby (stable) state, the output Q of the control flip-flop (FF) is HIGH. This makes
the output LOW because of power amplifier which is basically an inverter. A negative going
trigger pulse is applied to pin 2 and should have its dc level greater than the threshold level of t
lower comparator (i.e. V«/3), the output of the lower comparator goes HIGH and sets the FF (Q =
1, Q 0). During the positive excursion, when the threshold voltage at pin 6passes through (2/3)
V, the output of the upper comparator goes HIGH and resets the FF (Q=-0, Q =1).

The reset input (pin 4) provides a mechanism to reset the FF in a manner which overrides
the effect of any instruction coming to FF from lower comparator. This overriding reset is effective
when the reset input is less than about 0.4 V. When this reset is not used, it is returned to Voc. The
transistor Q serves as a buffer to isolate the reset input from the FF and transistor Q. The
transistor Q is driven by an internal reference voltage V obtained from supply voltage Ve

Monostable Operation of 555 timer:

Figure (1) shows a 555 timer connected for monostable operation and its functional diagram
is shown in figure (2). In the standby state, FF holds transistor Q on, thus clamping the external
timing capacitor C to ground. The output remains at ground potential, ie. LOW. As the trigger in
Figure 3(a) passes through V«/3, the FF is set, ie. Q = 0. This makes the transistor Q off and the

short circuit across the timing capacitor C is released. As Qis LOW, output goes HIGH (=V«).
The timing cycle now begins. Since Cis unclamped, voltage across it rises exponentially through R
toward V with a time constant RC as in figure 3(b). After a time period T (calculated later) the
capacitor voltage is just greater than (2/3) V« and the upper comparator resets Q=1, transistor Q
goes on (ie. saturates), thereby discharging the capacitor C rapidly to ground potential. The
output returns to the standlby state or ground potential as shown in figure 3(c)

555

Ovtpvt
-01F
 Figure: Monostable multivibrator
The voltage across the capacitor as in figure 3(b) is given by
ve = V« (1 -eiRC)
(1)
At t T, Ve (2/3) V
Therefore
V=V1-eTi)
T-RC In(1/3)
T-1.1 RC
Or,
(seconds)(2)
It is evident from equation (2) that the timing interval is independent of the supply voltage.
It may also be noted that once triggered, the output remains in the HIGH state until time T
elapses, which depends only upon R and C. Any additional trigger pulse coming during this time
will not change the output state. However, if a negative going reset pulse as in figure 3(d) is
applied to the reset terminal (pin-4) during the timing cycle, transistor Q: goes off,Q1 becomes on
and the external timing capacitor C is immediately discharged. The output now will be as in
Figure 3(e). It may be seen that the output of Q2 is connected directly to the input of Q so as to
turn on Q immediately and thereby avoid the propagation delay through the FF. Now, even if the
reset is released, the output will still remain LOW until a negative going trigger pulse is again
applied at pin 2. Figure (4) shows a graph of the various combinations of R and C necessary to
produce a given time delay.
4+Vea.

SSLA

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Fig. Timer in monostable operation with functional diagram

Sometimes the monostable circuit of figure (1) mistriggers on positive pulse edges, even
with the control pin bypass capacitor. To prevent this, a modified circuit as shown in figure 5 is
used. Here the resistor and capacitor combination of 10 kM and 0.001 uF at the input forms a
differentiator. During the positive going edge of the trigger, diode D becomes forward biased,
thereby limiting the amplitude of the positive spike to 0.7V.

Example:-
In the monostable multivibrator of Figure (1) R = 100 kh and the time delay T = 100 ms.

Calculate the value of C. Verify the value of C obtained from the graphs of Figure (4).

Solution:
From Equation (2), we get

0M

T-I MC]

0-001
Ims 10ms 100ms Is 10S 100s
Time deloy T

Figure: Graph of RC combinations for different time delays

 001 555

o01
Wavelorm at pen z

Figure: Modified monostable circuit

72/92

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C-T/1.1 R =100 x 10-/1.1 x 100 x 10- 0.9 uF

From the graph of figure 4, the value of C is found to be 0.9 F also.