Lecture – Combinational Circuits

Analysis & Design

 Combinational Circuits

▪ Two classes of logic circuits

▪ Combinational
▪ Sequential

▪ Combinational Circuit ▪ Sequential Circuit

▪ Each output depends entirely ▪ Each output depends on both
on the immediate (present) present inputs and state.
inputs.

Combinational Combinational
inputs : : Logic :: outputs inputs : : Logic :: outputs

Memory

Dr. Babar Mansoor Fundamentals of Digital Logic Design 2

 Combinational Circuits

 Output is function of input only i.e. no feedback

Combinational
n inputs • • m outputs
• Circuits •
• •


When input changes, output may change (after a delay)

Dr. Babar Mansoor Fundamentals of Digital Logic Design 3

 Combinational Circuits
 Analysis
● Given a circuit, find out its function
● Function may be expressed as:
♦ Boolean function
♦ Truth table

 Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
♦ Truth table

Dr. Babar Mansoor Fundamentals of Digital Logic Design 4

 Combinational Circuits – Analysis Procedure

▪ Given a combinational circuit, how do you analyze its

function?
What is this circuit?
A A+B
B F1 =
(A+B).(A'+B')

F2 = (A'+B')' = AB
A'+B'
▪ Steps: A B (A+B) (A'+B') F1 F2
0 0 0 1 0 0
1. Label the inputs and outputs.
0 1 1 1 1 0
2. Obtain the functions of 1 0 1 1 1 0
intermediate points and the outputs. 1 1 1 0 0 1
3. Draw the truth table.
4. Deduce the functionality of the circuit  Half adder.

Dr. Babar Mansoor Fundamentals of Digital Logic Design 5

 Combinational Circuits – Analysis Procedure

A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC

Dr. Babar Mansoor Fundamentals of Digital Logic Design 6

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 7

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 8

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 9

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1 0 0 1
B =1 0 1 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 10

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0 0 1 0
1
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 11

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 12

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 13

 Combinational Circuits – Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
Dr. Babar Mansoor Fundamentals of Digital Logic Design 14
 Combinational Circuits – Design Procedure
 Given a problem statement:
● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3”
code

➢ 4-bits ➢ 4-bits
➢ 0-9 values
? ➢ Value+3

Dr. Babar Mansoor Fundamentals of Digital Logic Design 15

 Combinational Circuits – Design Procedure

 BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
Dr. Babar Mansoor Fundamentals of Digital Logic Design 16
 Combinational Circuits – Design Procedure

 BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
Dr. Babar Mansoor Fundamentals of Digital Logic Design 17
 Combinational Circuits – Design Procedure
 Seven Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
Dr. Babar Mansoor Fundamentals of Digital Logic Design 18
 Combinational Circuits - Binary Adder

 Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C

Dr. Babar Mansoor Fundamentals of Digital Logic Design 19

 Combinational Circuits – Binary Adder

 Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
Dr. Babar Mansoor Fundamentals of Digital Logic Design 20
 Combinational Circuits – Binary Adder

 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z

x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

Dr. Babar Mansoor Fundamentals of Digital Logic Design 21

 Combinational Circuits – Binary Adder

 Full Adder
x S
y HA HA

z C

x
S

y
C

Dr. Babar Mansoor Fundamentals of Digital Logic Design 22

 4-bit Ripple Carry Adder (RCA)
x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 23
 4-bit Ripple Carry Adder (RCA)
x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 S C3 C2 C1
3 S2 S1 S0

❖ Carry propagates from 1st stage to the last stage

▪ C4 and S4 depend upon C3
▪ C3 and S3 depend upon C2
▪ C2 and S1 depend upon C1
❖ Takes more time to perform addition due to carry propagation
Dr. Babar Mansoor Fundamentals of Digital Logic Design 24
 8-bit Ripple Carry Adder (RCA)

 Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 25

 Propagation Delay of RCA

❖ To get 𝐶𝑖+1 , 𝐶𝑖 needs to propagate through one AND gate and

one OR gate
❖ For a single stage, carry propagates through two gates
❖ To get 𝐶4 , 𝐶0 needs to propagate through 2x4=8 gates
❖ If AND/OR delay is 10ns, then total delay is 8x10=80ns
❖ RCA has larger propagation delay to get the final carry i.e., it is
a low speed adder
Dr. Babar Mansoor Fundamentals of Digital Logic Design 26
 Carry-Lookahead Adder (CLA)
 Reduced carry propagation delay
❖ Look-ahead carry (more complex mechanism, yet faster)
❖ Carry propagate: Pi = Ai Bi
❖ Carry generate: Gi = Ai Bi
❖ Sum: Si = Pi Ci
❖ Carry: Ci+1 = Gi+PiCi
❖ C0 = Input carry
❖ C1 = G0+P0C0
❖ C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
❖ C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 27

 Carry-Lookahead Adder (CLA)

• Propagation delay of
𝐶3 , 𝐶2 and 𝐶1 are
equal.

• For AND/OR delay of

10ns, each 𝐶𝑖 is
generated after
2x10=20ns

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

Dr. Babar Mansoor Fundamentals of Digital Logic Design 28
 Carry-Lookahead Adder (CLA)

 4-bit carry-look
ahead adder

Fig. 4.12 4-Bit Adder with Carry Look-ahead

Dr. Babar Mansoor Fundamentals of Digital Logic Design 29

 Binary Subtractor

 Use 2’s complement with binary adder

● A – B = A + (-B) = A + B’ + 1

a3 a2 a1 a0 b3 b2 b1 b0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

D3 D2 D1 D0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 30

 Binary Subtractor

A3 A2 A1 A0
B3 B2 B1 B0
1

FA FA FA FA

D3 D2 D1 D0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 31

 Binary Adder/Subtractor

 Remember the truth table of XOR:

M IN F
● M=0 ➔ F = IN
0 0 0
0 1 1 ● M=1 ➔ F = IN’
1 0 1
1 1 0 IN
F
M

 An XOR is a programmable inverter!

Dr. Babar Mansoor Fundamentals of Digital Logic Design 32

 Binary Adder/Subtractor

 M: Control Signal (Mode)

● M=0 ➔ F = A + B
● M=1 ➔ F = A – B A3 A2 A1 A0 B3 B2 B1 B0 M

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 33
 Binary Adder/Subtractor

Dr. Babar Mansoor Fundamentals of Digital Logic Design 34

 Binary Adder/Subtractor
 Overflow
● Unsigned numbers ➔ Carry out of MSB
● Signed Numbers ➔ Carry-in and Carry-out of MSB different

Dr. Babar Mansoor Fundamentals of Digital Logic Design 35

 Binary Multiplier for Unsigned Numbers

Dr. Babar Mansoor Fundamentals of Digital Logic Design 36

 Binary Multiplier for Unsigned Numbers

Dr. Babar Mansoor Fundamentals of Digital Logic Design 37

 Binary Multiplier for Unsigned Numbers

Dr. Babar Mansoor Fundamentals of Digital Logic Design 38

 Binary Multiplier for Unsigned Numbers

 Multiplier: 𝑀 = 𝑚3 𝑚2 𝑚1 𝑚0
 Multiplicand: Q = 𝑞3 𝑞𝑞1 𝑞0
 Product: P = 𝑝7 𝑝6 𝑝5 𝑝4 𝑝3 𝑝2 𝑝1 𝑝0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 39

 Magnitude Comparator
❖ A combinational circuit that compares two unsigned integers

❖ Two Inputs:
 Unsigned integer A (m-bit number)

 Unsigned integer B (m-bit number)

❖ Three outputs: GT: A > B

A[m–1:0] m-bit
m
 A > B (GT output)
Magnitude EQ: A == B
 A == B (EQ output) B[m–1:0]
m Comparator
LT: A < B
 A < B (LT output)

❖ Exactly one of the three outputs must be equal to 1

❖ While the remaining two outputs must be equal to 0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 40
 Magnitude Comparator
 4-bit magnitude comparator (A=B)
❖ Inputs:
 𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0
 𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0
 8 bits in total ➔ 256 possible combinations
 Not simple to design using conventional K-map techniques
❖ The magnitude comparator can be designed at a higher level
❖ Let us implement first the 𝐸𝑄 output (𝐴 is equal to 𝐵)
 𝐸𝑄 = 1 𝐴3 == 𝐵3 , 𝐴2 == 𝐵2 , 𝐴1 == 𝐵1 , and 𝐴0 == 𝐵0
 Define: 𝐸𝑖 = 𝐴𝑖 == 𝐵𝑖 = 𝐴𝑖 𝐵𝑖 + 𝐴′𝑖 𝐵𝑖′ (i.e., XNOR)
 Therefore, 𝐸𝑄 = 𝐴 == 𝐵 = 𝐸3 𝐸2 𝐸1 𝐸0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 41
 Magnitude Comparator
 4-bit magnitude comparator (A=B)

(a) A=B with XNOR (b) A=B with XOR

Dr. Babar Mansoor Fundamentals of Digital Logic Design 42

 Magnitude Comparator
 4-bit magnitude comparator (A>B)
1. If 𝐴3 > 𝐵3 then 𝐺𝑇 = 1, irrespective of the lower bits of 𝐴 and 𝐵
Define: 𝐺3 = 𝐴3 𝐵3′ (𝐴3 == 1 and 𝐵3 == 0)
2. If 𝐴3 == 𝐵3 (𝐸3 == 1), we compare 𝐴2 with 𝐵2
Define: 𝐺2 = 𝐴2 𝐵2′ (𝐴2 == 1 and 𝐵2 == 0)
3. If 𝐴3 == 𝐵3 and 𝐴2 == 𝐵2 , we compare 𝐴1 with 𝐵1
Define: 𝐺1 = 𝐴1 𝐵1′ (𝐴1 == 1 and 𝐵1 == 0)
4. If 𝐴3 == 𝐵3 and 𝐴2 == 𝐵2 and 𝐴1 == 𝐵1 , we compare 𝐴0 with 𝐵0
Define: 𝐺0 = 𝐴0 𝐵0′ (𝐴0 == 1 and 𝐵0 == 0)
Therefore, 𝐺𝑇 = 𝐺3 + 𝐸3 𝐺2 + 𝐸3 𝐸2 𝐺1 + 𝐸3 𝐸2 𝐸1 𝐺0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 43
 Magnitude Comparator
 4-bit magnitude comparator (A<B)

1. If 𝐴3 < 𝐵3 then 𝐿𝑇 = 1, irrespective of the lower bits of 𝐴 and 𝐵

Define: 𝐿3 = 𝐴′3 𝐵3 (𝐴3 == 0 and 𝐵3 == 1)
2. If 𝐴3 = 𝐵3 (𝐸3 == 1), we compare 𝐴2 with 𝐵2
Define: 𝐿2 = 𝐴′2 𝐵2 (𝐴2 == 0 and 𝐵2 == 1)
3. Define: 𝐿1 = 𝐴1′ 𝐵1 (𝐴1 == 0 and 𝐵1 == 1)
4. Define: 𝐿0 = 𝐴′0 𝐵0 (𝐴0 == 0 and 𝐵0 == 1)
Therefore, 𝐿𝑇 = 𝐿3 + 𝐸3 𝐿2 + 𝐸3 𝐸2 𝐿1 + 𝐸3 𝐸2 𝐸1 𝐿0
Knowing 𝐺𝑇 and 𝐸𝑄, we can also derive 𝐿𝑇 = (𝐺𝑇 + 𝐸𝑄)′

Dr. Babar Mansoor Fundamentals of Digital Logic Design 44

 Magnitude Comparator

Dr. Babar Mansoor Fundamentals of Digital Logic Design 45

 Decoders

▪ Codes are frequently used to represent entities, e.g,: your name

is a code to denote yourself (an entity!)
▪ These codes can be identified (or decoded) using a decoder.
Given a code, identify the entity.

• Given a n-bit binary code, there are 2n possible code values

• The decoder has an output for each possible code value

• The n-to-2n decoder has n inputs and 2n outputs

• Depending on the input code, only one output is set to logic 1

• The conversion of input to output is called decoding

Dr. Babar Mansoor Fundamentals of Digital Logic Design 46

 Decoders

1 0 1

Some device

0 1 2 3 4 5 6 7

Dr. Babar Mansoor Fundamentals of Digital Logic Design 47

 Decoders

A decoder can have less

2n Outputs
n Inputs

n to 2n
than 2n outputs if some



Decoder
input codes are unused

Dr. Babar Mansoor Fundamentals of Digital Logic Design 48

 Decoders

▪ Example: If codes 00, 01, 10, 11 are used to identify four light
bulbs, we may use a 2-bit decoder.

2x4
F0 Bulb 0
2-bit X DEC F Bulb 1
1
code Y
F2 Bulb 2
F3 Bulb 3

▪ This is a 24 decoder which selects an output line based on

the 2-bit code supplied.

Dr. Babar Mansoor Fundamentals of Digital Logic Design 49

 Decoders
 2-to-4 Decoder

0 d0  Circuit

4 Outputs
2 Inputs

a1 1 2-to-4 1 d1
a0 0
Decoder 2 d2 𝑎1
3 d3 𝑑0 = 𝑎1′ 𝑎0′
𝑎0
 Truth Table 𝑑1 = 𝑎1′ 𝑎0
𝑑2 = 𝑎1 𝑎0′
Inputs Outputs
a1 a0 d0 d1 d2 d3 𝑑3 = 𝑎1 𝑎0
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0 Each decoded output is a
1 1 0 0 0 1 minterm of 2 variables
Dr. Babar Mansoor Fundamentals of Digital Logic Design 50
 Decoders

 3-to-8 Decoder  Truth Table

Inputs Outputs
0 d0
1 d1 a 2 a 1 a 0 d0 d1 d2 d3 d4 d5 d 6 d7
2 d2 0 0 0 1 0 0 0 0 0 0 0
a2

8 Outputs
2
3 Inputs

0 0 1 0 1 0 0 0 0 0 0
3-to-8 3 d3
a1 1 0 1 0 0 0 1 0 0 0 0 0
4 d4
a0 0 Decoder 0 1 1 0 0 0 1 0 0 0 0
5 d5 1 0 0 0 0 0 0 1 0 0 0
6 d6 1 0 1 0 0 0 0 0 1 0 0
7 d7 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 51

 Decoders
 3-to-8 Decoder 𝑎2
𝑎1
𝑎0 𝑑0 = 𝑎2′ 𝑎1′ 𝑎0′
𝑑1 = 𝑎2′ 𝑎1′ 𝑎0
𝑑2 = 𝑎2′ 𝑎1 𝑎0′
𝑑3 = 𝑎2′ 𝑎1 𝑎0
𝑑4 = 𝑎2 𝑎1′ 𝑎0′
𝑑5 = 𝑎2 𝑎1′ 𝑎0
𝑑6 = 𝑎2 𝑎1 𝑎0′
𝑑7 = 𝑎2 𝑎1 𝑎0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 52

 Decoders
 2-to-4 Decoder with Active High Enable Input
Inputs Outputs 0 d0
a1 1
E a1 a0 d0 d1 d2 d3 2-to-4 1 d1
a0 0
d2
Decoder 2
0 X X 0 0 0 0
3 d3
1 0 0 1 0 0 0

1 0 1 0 1 0 0
E
1 1 0 0 0 1 0
𝑎1
1 1 1 0 0 0 1
𝑎0 𝑑0 = 𝐸𝑎1′ 𝑎0′
𝑑1 = 𝐸𝑎1′ 𝑎0
If E input is zero then all
outputs are zeros, regardless 𝑑2 = 𝐸𝑎1 𝑎0′
of a1 and a0
𝑑3 = 𝐸𝑎1 𝑎0
𝐸
Dr. Babar Mansoor Fundamentals of Digital Logic Design 53
 Decoders
 2-to-4 Decoder with Active Low Enable Input
Inputs Outputs 0 d0
a1 1
E a1 a0 d0 d1 d2 d3 2-to-4 1 d1
a0 0
d2
Decoder 2
1 X X 0 0 0 0
3 d3
0 0 0 1 0 0 0

0 0 1 0 1 0 0
E
0 1 0 0 0 1 0
𝑎1
0 1 1 0 0 0 1
𝑎0 𝑑0 = 𝐸′𝑎1′ 𝑎0′
𝑑1 = 𝐸′𝑎1′ 𝑎0
If E input is 1then all
outputs are zeros, 𝑑2 = 𝐸′𝑎1 𝑎0′
regardless of a1 and a0
𝑑3 = 𝐸′𝑎1 𝑎0
𝐸
Dr. Babar Mansoor Fundamentals of Digital Logic Design 54
 Decoders
 Constructing Larger Decoders with Smaller Ones
• A 3-to-8 decoder can be built using:
Two 2-to-4 decoders with Enable and an inverter
Inputs Outputs
a2
a 2 a 1 a 0 d0 d1 d2 d3 d4 d5 d6 d7 a 0 d0
1 1 Top 1 d1
0 0 0 1 0 0 0 0 0 0 0 a0 0 2-to-4
Decoder
2 d2
0 0 1 0 1 0 0 0 0 0 0
EN 3 d3
0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0 0 d4
1 Bottom
1 0 1 0 0 0 0 0 1 0 0 1 d5
0 2-to-4
1 1 0 0 0 0 0 0 0 1 0 Decoder
2 d6
1 1 1 0 0 0 0 0 0 0 1
EN 3 d7

Dr. Babar Mansoor Fundamentals of Digital Logic Design 55

 Decoders
 4-to-16 Decoder using 2-to-4 Decoders
a1 1 2-to-4 0 d0
1 d1
a0 0 Decoder 2 d2
A 4-to-16 decoder 0
EN 3 d3
with enable can
1 2-to-4 0 d4
be built using five 1 d5
0 Decoder 2 d6
2-to-4 decoders a3 1 0 1 d7
EN 3
2-to-4 1
with enables a2 0
Decoder 2 d8
1 2-to-4 0
EN EN 3 1 d9
0 Decoder 2 d10
EN 2 3 d11
Larger decoders can be
1 2-to-4 0 d12
built hierarchically in a 1 d13
0 Decoder 2 d14
similar way 3
EN 3 d15
Dr. Babar Mansoor Fundamentals of Digital Logic Design 56
 Decoders

 Homework
 Construct a 5-to-32 decoder using 2-to-4 decoders
 Construct 4-to-16 decoder using 3-to-8 decoders
 Construct 5-to-32 decoder using 3-to-8 decoders

Dr. Babar Mansoor Fundamentals of Digital Logic Design 57

 BCD to 7-Segment Decoder
❖ Seven-Segment Display:
 Made of Seven segments: light-emitting diodes (LED)
 Found in electronic devices: such as clocks, calculators, etc.

a
I3 BCD to b
❖ BCD to 7-Segment Decoder I2 c
7-Segment d
I1 e
 Called also a decoder, but not a binary decoder Decoder f
I0
g
 Accepts as input a BCD decimal digit (0 to 9)
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately
Dr. Babar Mansoor Fundamentals of Digital Logic Design 58
 BCD to 7-Segment Decoder
Specification: Truth Table
 Input: 4-bit BCD (I3, I2, I1, I0) BCD input 7-Segment Output
I3 I2 I 1 I 0 a b c d e f g
 Output: 7-bit (a, b, c, d, e, f, g) 0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
 Display should be OFF for Non-BCD 0 0 1 0 1 1 0 1 1 0 1
input codes. 0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
Implementation can use: 0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
 A binary decoder 0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
 Additional gates
1 0 0 1 1 1 1 1 0 1 1
1010 to 1111 0 0 0 0 0 0 0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 59

 BCD to 7-Segment Decoder
a Truth Table
I3 I2 I 1 I 0 a b c d e f g
0
b 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 c 0 0 1 0 1 1 0 1 1 0 1
I3 3 0 0 1 1 1 1 1 1 0 0 1
4-to-10
4 0 1 0 0 0 1 1 0 0 1 1
I2 d
Binary 5 0 1 0 1 1 0 1 1 0 1 1
I1 0 1 1 0 1 0 1 1 1 1 1
I0 Decoder 6 e
0 1 1 1 1 1 1 0 0 0 0
7 1 0 0 0 1 1 1 1 1 1 1
8 1 0 0 1 1 1 1 1 0 1 1

9 f 1010 – 1111 0 0 0 0 0 0 0

𝐼3 (𝐼2 + 𝐼1 ) g

Input > 9
NOR gate is used for 0's
Dr. Babar Mansoor Fundamentals of Digital Logic Design 60
 Implementing Boolean Functions Using Decoders
❖ A decoder generates all the minterms
❖ A Boolean function can be expressed as a sum of minterms
❖ Any function can be implemented using a decoder + OR gate
Note: the function must not be minimized
❖ Example: Full Adder sum = ∑(1, 2, 4, 7), cout = ∑(3, 5, 6, 7)

Inputs Outputs
d0
a b c cout sum
d1
0 0 0 0 0 sum
0 0 1 0 1 d2
a 2
0 1 0 0 1 3-to-8 d3
b 1
0 1 1 1 0 d
1 0 0 0 1 c 0 Decoder 4 cout
d5
1 0 1 1 0
d6
1 1 0 1 0
1 1 1 1 1 d7
Dr. Babar Mansoor Fundamentals of Digital Logic Design 61
 Implementing Boolean Functions Using Decoders

 Implement 𝐹 = 𝐴′ 𝐵 + 𝐴𝐵′ using decoders

 As 𝐹 is a function of two variables, so we need 2-

to-4 decoder

d0
0
A 1 d
2-to-4 1 1
B 0 d2 F
Decoder 2
d3
3

 Homework
 Implement 𝐹 = 𝐴 + 𝐵𝐶 using decoders

Dr. Babar Mansoor Fundamentals of Digital Logic Design 62

 Decoders with Active Low Outputs
Truth Table
0 d0
Inputs Outputs a1 1
2-to-4 1 d1
a0 0
d2
EN a1 a0 d0 d1 d2 d3 Decoder 2
EN 3 d3
1 X X 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1 𝑎1
0 1 0 1 1 0 1
𝑎0 𝑑0 = (𝐸𝑁 ′ 𝑎1′ 𝑎0′ )′
0 1 1 1 1 1 0
𝑑1 = (𝐸𝑁 ′ 𝑎1′ 𝑎0 )′

Some decoders are constructed 𝑑2 = (𝐸𝑁 ′ 𝑎1 𝑎0′ )′

with NAND gates. Their outputs
are inverted. The Enable input is 𝑑3 = (𝐸𝑁 ′ 𝑎1 𝑎0 )′
also active low (Enable if zero) 𝐸𝑁

Dr. Babar Mansoor Fundamentals of Digital Logic Design 63

 Decoders with Active Low Outputs
 Implement 𝐹 = 𝐴′ 𝐵 + 𝐴𝐵′ using active-low output
decoder

d0
0
A 1 d1=(A’B)’
1
2-to-4
B 0 F
Decoder d2=(AB’)’
2

3 d3

Dr. Babar Mansoor Fundamentals of Digital Logic Design 64

 Implementing Boolean Functions with Decoders

▪ Example: Implement the following function using a 38

decoder and an appropriate logic gate
f(Q,X,P) =  m(0,1,4,6,7) =  M(2,3,5)
▪ We may implement the function in several ways:
▪ Using a decoder with active-high outputs with an OR gate:
f(Q,X,P) = m0 + m1 + m4 + m6 + m7
▪ Using a decoder with active-low outputs with a NAND gate:
f(Q,X,P) = (m0'  m1'  m4'  m6'  m7' )'
▪ Using a decoder with active-high outputs with a NOR gate:
f(Q,X,P) = (m2 + m3 + m5 )' [ = M2  M3  M5 ]
▪ Using a decoder with active-low outputs with an AND gate:
f(Q,X,P) = m2'  m3'  m5'

Dr. Babar Mansoor Fundamentals of Digital Logic Design 65

 Implementing Boolean Functions with Decoders

f(Q,X,P) = Sm(0,1,4,6,7) =  M(2,3,5)

0 0
3x8 1 3x8 1
Dec 2 Dec 2
Q 3 f(Q,X,P) Q 3 f(Q,X,P)
4 4
X X
5 5
P 6 P 6 (m0'·m1'·m4'·m6'·m7)'
7 7 =m0+m1+m4+m6+m7

(a) Active-high decoder with OR gate. (b) Active-low decoder with NAND gate.

0 0
3x8 1 3x8 1
Dec 2 f(Q,X,P) Dec 2
f(Q,X,P)
Q 3 Q 3
4 4
X X
5 (m2+m3+m5)' 5 m2'·m3'·m5'
P 6 = m2'·m3'·m5' P 6 = M2·M3·M5
7 = M2·M3·M5 7

(c) Active-high decoder with NOR gate. (d) Active-low decoder with AND gate.

Dr. Babar Mansoor Fundamentals of Digital Logic Design 66

 Encoders
❖ An encoder performs the opposite operation of a decoder

❖ It converts a 2n input to an n-bit output code

❖ The output indicates which input is active (logic 1)

❖ Typically, one input should be 1 and all others must be 0's

❖ The conversion of input to output is called encoding

An encoder can have less

n Outputs
2n Inputs
2n to n
than 2n inputs if some input



Encoder
lines are unused

Dr. Babar Mansoor Fundamentals of Digital Logic Design 67

 Encoders
❖ 8-to-3 Binary Encoder
❖ 8 inputs, 3 outputs, only one input is 1, all others are 0's
❖ Encoder generates the output binary code for the active
input
❖ Output is not specified if more than one input is 1
Inputs Outputs
d0 0
d7 d6 d5 d4 d3 d2 d1 d0 a 2 a 1 a 0
d1 1
0 0 0 0 0 0 0 1 0 0 0
d2 2
3 Outputs

8-to-3 2 a2
8 Inputs

0 0 0 0 0 0 1 0 0 0 1
d3 3
a1 0 0 0 0 0 1 0 0 0 1 0
d4 4 Binary 1
0 a0 0 0 0 0 1 0 0 0 0 1 1
d5 5 Encoder 0 0 0 1 0 0 0 0 1 0 0
d6 6 0 0 1 0 0 0 0 0 1 0 1
d7 7 0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 68

 Encoders
Inputs Outputs d0 0
d1 1
d7 d6 d5 d4 d3 d2 d1 d0 a 2 a 1 a 0 d2 2 8-to-3 2 a2
0 0 0 0 0 0 0 1 0 0 0 d3 3
Binary 1 a1
0 0 0 0 0 0 1 0 0 0 1 d4 4
0 a0
0 0 0 0 0 1 0 0 0 1 0
d5 5
Encoder
d6 6
0 0 0 0 1 0 0 0 0 1 1
d7 7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1 d4
d5
0 1 0 0 0 0 0 0 1 1 0 a2
d6
1 0 0 0 0 0 0 0 1 1 1 d7
d2
a2 = d4 + d5 + d6 + d7 8-to-3 binary d3
d6 a1
encoder d7
a1 = d2 + d3 + d6 + d7 implemented d1
using three d3
a0
d5
a0 = d1 + d3 + d5 + d7 4-input OR gates d7
Dr. Babar Mansoor Fundamentals of Digital Logic Design 69
 Binary Encoder Limitations

❖ Exactly one input must be 1 at a time (all others must be 0's)

❖ If more than one inputs are 1 then the output will be incorrect
❖ For example, if d3 = d6 = 1
Then a2 a1 a0 = 111 (incorrect)
❖ Two problems to resolve:
1. If two inputs are 1 at the same time, what should be the
output?
2. If all inputs are 0's, what should be the output?
❖ Output a2 a1 a0 = 000 if d0 = 1 or all inputs are 0's
How to resolve this ambiguity?

Dr. Babar Mansoor Fundamentals of Digital Logic Design 70

 Priority Encoder
❖ Eliminates the two problems of the binary encoder
❖ Inputs are ranked from highest priority to lowest priority
❖ If more than one inputs are active (logic 1) then priority is used
Output encodes the active input with higher priority
❖ If all inputs are zeros, then the V (Valid) output is zero
Indicates that all inputs are zeros Inputs Outputs
d3 d2 d1 d0 a 1 a 0 V
d3 3 = highest priority
Condensed 0 0 0 0 X X 0
1 a1
d2 2 4-to-2 Priority Truth Table 0 0 0 1 0 0 1
0 a0
d1 1 Encoder All 16 cases 0 0 1 X 0 1 1
d0 0 = lowest priority V are listed 0 1 X X 1 0 1
1 X X X 1 1 1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 71

 Implementing 4-to-2 Priority Encoder
𝑑1 𝑑0
K-Map of 𝑎1 𝑑1 𝑑0
K-Map of 𝑎0
Inputs Outputs
𝑑3 𝑑2 00 01 11 10 𝑑3 𝑑2 00 01 11 10
d3 d2 d1 d0 a 1 a 0 V
00 X 00 X 1 1
0 0 0 0 X X 0
0 0 0 1 0 0 1 01 1 1 1 1 01
0 0 1 X 0 1 1
11 1 1 1 1 11 1 1 1 1
0 1 X X 1 0 1
1 X X X 1 1 1 10 1 1 1 1 10 1 1 1 1

d3
a1
d2
Output Expressions:
𝑎1 = 𝑑3 + 𝑑2 a0
𝑎0 = 𝑑3 + 𝑑1 𝑑2′ d1

𝑉 = 𝑑3 + 𝑑2 + 𝑑1 + 𝑑0 V
d0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 72
 Multiplexers
❖ Selecting data is an essential function in digital systems

❖ Functional blocks that perform selection are called multiplexers

❖ A Multiplexer (or Mux) is a combinational circuit that has:

 Multiple data inputs (typically 2n) to select from

d0
d1

2n Inputs
 An n-bit select input S used for control
d2

Mux
. Y
 One output Y .
.
❖ The n-bit select input directs one of the data d2n–1
n
inputs to the output
S

Dr. Babar Mansoor Fundamentals of Digital Logic Design 73

 Multiplexers
 2-to-1 Multiplexer

if (S == 0) Y = d0 ; Inputs Output

else Y = d1; d0 0 S d0 d1 Y

Mux
Y 0 0 X 0 = d0

d1 1 0 1 X 1 = d0
Logic expression: 1 X 0 0 = d1

𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆 S 1 X 1 1 = d1

Dr. Babar Mansoor Fundamentals of Digital Logic Design 74

 Multiplexers
 2-to-1 Multiplexer

d0 0

Mux
𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆
d1 1

S
d0

Y
d1

Logic circuit for 2-to-1 Mux

Dr. Babar Mansoor Fundamentals of Digital Logic Design 75
 Multiplexers
 4-to-1 Multiplexer

if (S1S0 == 00) Y = d0 ;
else if (S1S0 == 01) Y = d1; Inputs Output
else if (S1S0 == 10) Y = d2; S1 S0 d0 d1 d2 d3 Y
0 0 0 X X X 0 = d0
else Y = d3; 0 0 1 X X X 1 = d0
d0 0
0 1 X 0 X X 0 = d1
d1 1

Mux
𝑌 0 1 X 1 X X 1 = d1
d2 2
1 0 X X 0 X 0 = d2
d3 3 1 0 X X 1 X 1 = d2
1 1 X X X 0 0 = d3
S1 S0 1 1 X X X 1 1 = d3
Logic expression:
𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆2

Dr. Babar Mansoor Fundamentals of Digital Logic Design 76

 Multiplexers

 4-to-1 Multiplexer

d0

d1
d0 0
d1 1 d2 Y
Mux

𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0

d2 2
+ 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆0 d3
d3 3

S1S0 S1
S0

Logic circuit for 4-to-1 Mux

Dr. Babar Mansoor Fundamentals of Digital Logic Design 77

 Building Larger Multiplexers

▪ Larger multiplexers can be constructed from smaller ones.

▪ An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):
d0 0
d0 0 d1
S2 S1 S0 Y 1

Mux
d1 1 0 0 0 d0 d2 2
d2 2 0 0 1 d1
8-to-1 Mux

0 1 0 d2 d3 3
d3 3 0
Y 0 1 1 d3

Mux
d4 4 1 0 0 d4 S1S0 Y
1
d5 5 1 0 1 d5
1 1 0 d6 d4 0
d6 6 1 1 1 d7 S2
d5 1

Mux
d7 7
d6 2
S2S1S0 d7 3

S1S0
Dr. Babar Mansoor Fundamentals of Digital Logic Design 78
 Building Larger Multiplexers

 4-to-1 Mux using 2-to-1 Muxes

d0 0

Mux
d0 0 d1 1
0
d1 1

Mux
Mux

𝑌 S0 Y
d2 2 1
d2 0
d3

Mux
3
S1
d3 1
S1S0
S0

Dr. Babar Mansoor Fundamentals of Digital Logic Design 79

 Building Larger Multiplexers

 Homework
 Construct an 8-to-1 Mux using 2-to-1 Muxes
 Construct 16-to-1 Mux using 8-to-1 Muxes
 Construct 16-to-1 Mux using 4-to-1 Muxes
 Construct 16-to-1 Mux using 2-to-1 Muxes

Dr. Babar Mansoor Fundamentals of Digital Logic Design 80

 Multiplexers with Vector Inputs/Outputs
The inputs and output of a multiplexer can be m-bit vectors

A [m–1:0] 0
A [m–1:0] 0 m
m B [m–1:0] 1
Mux

Mux
Y [m–1: 0] m Y [m–1: 0]
B [m–1:0] m C [m–1:0] 2 m
1 m
m D [m–1:0] 3
m
S
S1S0

2-to-1 Multiplexer with m bits 4-to-1 Multiplexer with m bits

Inputs and output are m-bit vectors Inputs and output are m-bit vectors
Using m copies of a 2-to-1 Mux Using m copies of a 4-to-1 Mux

Dr. Babar Mansoor Fundamentals of Digital Logic Design 81

 Implementing Boolean Function with Multiplexers
❖ A Multiplexer can be used to implement any logic function
❖ The function must be expressed using its minterms
❖ Example: Implement F(a, b, c) = ∑(1, 2, 6, 7) using a Mux
❖ Solution:
Inputs Output
0 0
a b c F
1 1
The inputs are 0 0 0 0
1 2

8-to-1 Mux
used as select 0 0 1 1
0 1 0 1
0 3
lines to a Mux. F
0 1 1 0 0 4
An 8-to-1 1 0 0 0 0 5
Mux is used 1 0 1 0 1 6
1 1 0 1 1 7 0
because there 2
1
1 1 1 1
are 3 variables
S2 S1 S0 = a b c
Dr. Babar Mansoor Fundamentals of Digital Logic Design 82
 Implementing Boolean Function with Multiplexers
❖ Re-implement F(a, b, c) = ∑(1, 2, 6, 7) using a 4-to-1 Mux
❖ We will use the two select lines for variables a and b
❖ Variable c and its complement are used as inputs to the Mux

Inputs Output Comment

a b c F F
0 0 0 0
F=c c 0
0 0 1 1

4-to-1 Mux
0 1 0 1
F = c' c' 1
0 1 1 0
F
1 0 0 0
F=0 0 2
1 0 1 0
0
1 1 0 1 1 3 1
F=1
1 1 1 1

S1 S0 = a b
Dr. Babar Mansoor Fundamentals of Digital Logic Design 83