Digitally-Assisted Peak Detector for Periodic Signal

Asif Wahid and Armin Tajalli

Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah
Email: [email protected]

Abstract—A high-precision digitally-assisted peak detector

(PD) circuit is presented. While conventional analog PD circuits
suffer from Process, Voltage, and Temperature (PVT) variation,
as well as noise and device mismatch, resolution of the proposed
PD is only limited by quantization noise of the digital tracking
circuit. At startup, a binary search algorithm is employed to
quickly find the signal amplitude. After an initial phase, the
proposed digitally assisted PD switches to tracking mode in order
to follow the peak of the input signal. Designed for periodic
systems, such as Voltage Controlled Oscillators (VCOs) and
Amplitude Modulation (AM) detectors, the proposed digitally
assisted PD exhibits a total of 2 mVpkpk error. The proposed
PD shows very low sensitivity to noise of the analog circuitry
due to digital averaging. Moreover, calibration mechanisms have Fig. 1. The proposed peak detection algorithm, divided into startup (initial
been proposed to detect and remove the offset of comparator peak estimation) and mission mode (tracking phase).
circuits. In 0.18µm technology, the implemented peak detector
consumes 438.5nW power in the analog section and the digital
calibration part consumes 28.52µW. between noise and non-linearity. Peak detectors are generally
Index Terms—Analog FET circuits, peak detector, digitally- employed to measure the signal level and control the gain
assisted analog circuit, high-precision circuits, calibration. of VGAs [5]. Different algorithms and methodologies have
been developed to implement peak-detectors which include
I. I NTRODUCTION very sophisticated techniques such as wavelet transform based
With the advancement of process technology of the field- systems [6], [7], and Hilbert transforms [8]. The main features
effect transistor (FETs), it has become extremely important of existing peak detection algorithm depend on choice of
to optimize area and performance of integrated circuit blocks. multiple parameters such as threshold value [9], and window
Design of analog integrated circuits involves tight trade-offs length. The main motivation behind this work is to reduce the
among speed, noise, area and performance. The performance complexity of the detection algorithm, add flexibility to the
parameters of an analog/digital integrated block also depend system, and improve the energy efficiency.
on the architecture that has been incorporated in the design. In this article, a peak detection algorithm is proposed which
Improving the architecture of different analog circuit blocks involves lesser complexity with an improved detection scheme.
is an active field of research in circuit design community. The flow diagram for the algorithm is presented in Figure 1.
Depending upon the application, the same circuit block can The proposed algorithm is applicable to any periodic signal.
have different specification requirement which means the Initially, the PD generates an analog value as an estimate
design criteria is application specific. for peak amplitude. Following an initial guess, this system
Peak Detectors (PD) have various application in signal successively improves precision of the peak value using a
processing and communication system [1], [2]. Examples are binary search algorithm. The PD block samples the input
control systems, and Amplitude Modulation (AM) detectors, signal at specific time points and compares it with the latest
among others [3]. To mitigate the existing imprecision factors estimated value. After each comparison, the estimated value
existing in conventional fully analog peak detectors [4], a will be increased or decreased depending on polarity of the
digitally-assisted PD will be introduced. Proper calibration and error signal. The process continues until the estimated peak
tuning algorithms are being employed to minimize different value falls within a certain range of actual peak amplitude.
sources of error. As illustrated in Fig. 1, after detecting the amplitude, the
system continues following (tracking) the peak value using
II. P EAK D ETECTION A LGORITHM a bang-bang approach. As the process of estimation transpires
In various signal processing applications, a data process- in digital domain, the time-constant (window length) can be
ing block is required which can read a sinusoidal or semi- programmed and refined.
sinusoidal signal, and efficiently detect the peak value or This approach for implementing the PD circuit is very simi-
amplitude of that sinusoidal signal. In many communication lar to Successive-Approximate Register (SAR) data converters
systems, a Variable Gain Amplifier (VGA) is used to control [10]. The main difference here is that the architecture and
the dynamic range of system and create a proper balance consumption of the system has been accurately optimized as

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 Fig. 2. Modified analog rectifier circuit proposed here. The circuit can produce
precise peak estimations for: (i) high input swing values, when only M8a is Fig. 4. The proposed peak detector block architecture.
on, or (ii) for small input voltage levels, where both M8a and M8b are on.

design will be:

W W W
2×( )M 6 = 2 × ( )M 7 = ( )M 8 . (2)
L L L
Therefore, depending on signal swing, the optimal design
should be changed, or programmed. Fig. 3 shows the response
of the analog PD shown in Fig. 2. The proposed PD has been
designed for high input swing signals. As depicted in Fig.
3, the circuit shows a very good precision when signal level
is high, however the precision degrades when input swing is
very low.

Digitally Assisted PD. In the proposed algorithm, a digital

integrator replaces the analog low-pass filter, that results in
considerable area reduction. Fig. 4 illustrates the proposed
Fig. 3. Transfer function of the analog rectifier proposed in Fig. 2. The gray
dashed line shows an ideal peak detector transfer function. digitally-assisted, or successive-approximation PD. A compact
resistor ladder based digital-to-analog converter (DAC) is used
to convert the estimated digital peak value to analog. The
the system needs to only detect the peak value. Moreover, estimated peak value is compared to the input signal. A strong-
this design includes specific start-up calibration algorithms as Arm topology has been utilized to implement the comparator
a means to remove offset and timing error source, which are circuit [11], [12]. Based on error signals produced by the com-
not necessarily important in SAR data converters. parator (Up and Down signals), a Finite-State Machine (FSM)
gradually corrects the estimated value. The time-constant of
III. P ROPOSED P EAK D ETECTOR A RCHITECTURE the integrator in the FSM is digitally programmable.
The precision of the proposed SAR PD depends on resolu-
Analog PD. The existing analog peak detectors rely on inher- tion of the DAC, and also the input offset of the comparator. To
ent non-linearity of semiconductor devices, that can vary with minimize the effect of INL/DNL, a resistor ladder based DAC
PVT. Moreover, generally a large capacitance is required to has been used. As shown in Fig. 4, an analog low-pass filter
determine the bandwidth of the peak detector (i.e. the window can be used in order to take the average of the toggling DAC
length), which results in large Silicon area. Fig. 2 depicts an output (bang-bang noise), and produce a finer DAC resolution.
analog rectifier with a unity gain feedback topology. By proper Also, as will be explained later, the offset of comparator can
sizing of M6/M7 (the core peak detector circuit), and M8, a be estimated and stored in the digital FSM system in order to
good precision in detection level can be achieved. When the remove its effect. In the following, the design constraints for
signal swing is large, then: different building blocks are detailed.
W W W A. Comparator
( )M 6 = ( )M 7 = ( )M 8 . (1)
L L L A single-bid analog-to-digital converter (ADC) has been
However, when the signal level is small and both M6 and M7 used to compare the input signal, Vsin , and the estimated
are on for the entire input voltage levels, then a more optimal peak value, Vpeak,est . The outcome of this comparison will

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 Fig. 5. StrongArm topology used to implement the comparator. Fig. 7. Error of detected peak value for a signal amplitude of 1.2V, versus
the sampling clock phase error (angular mismatch).

filter out the bang-bang amplitude noise and produce a signal

which is more precise compared to the DAC output.
IV. C ALIBRATION A LGORITHMS
The overall error terms contributing to the precision of the
proposed SAR PD are:
2 2 VLSB,DAC 2
Verror ≈ Vos,comp +( ) + (α∆t)2 (3)
2
where, Vos,comp represents the input referred offset of the
Fig. 6. Clocking scheme for comparator and DAC. comparator, and ∆t is the timing error term [13]. The
timing error term becomes zero when the sampling clock
happens exactly at the peak of signal. Fig . 7 shows the
be accumulated in the FSM block in order to properly update error caused by the phase mismatch, or equivalently timing
the estimation. The estimated value is converted back to analog skew, ∆θ = 2πf∆t. The error is as low as the DAC Least-
domain using a DAC. The input signal, Vsin , is periodic of Significant Bit (LSB) resolution, when ∆θ = 0. However, it
which the peak amplitude is required. The circuit diagram of gradually increases by ∆θ. As expected, the error term is very
the StrongArm comparator is shown in Fig. 5. To avoid any small for small ∆θ values, as it is proportional to sin(∆θ).
race issue, the output of DAC is updated in a clock phase After the calibration, the overall error term will be less than
opposite to the comparison phase, which is depicted in Fig. 6. VLSB,DAC + 0.5αVLSB,PI .
As the offset of such a comparator can be high, a dedicated
offset cancellation technique has been developed for this A. Offset Corrections:
circuit. The detected offset is stored in the digital domain,
and virtually added on top of the estimated peak value. In Figure 6 shows the sampling clock scheme for the compara-
this way, there is no need to add any analog offset correction tor and DAC so that the DAC can change its output after the
branch to the strongArm, which prevents affecting the speed comparator decisions are available (both samples are taken at
and the noise performance of the circuit. the rising edges). The timing of the DAC and the sampler
should be selected carefully to avoid race condition. After
B. DAC receiving the comparator decision, the DAC output will be
To produce the estimated peak value, Vpeak,est , a resistor increased or decreased depending upon the estimated analog
ladder DAC has been employed. To reduce the DAC area, value for the peak. In this algorithm, both offset of the
the output voltage swing of the DAC has been limited to the comparator and the sampling phase of the clock are important
expected range of the peak voltage. The DAC is controlled in order to make a precise decision. Therefore, both of these
using thermometer coding in order to keep it monotonic. two parameters need to be calibrated before starting the PD
operation.
C. FSM Several offset cancellation technique have been reported in
The FSM circuit used for the peak-detector includes a literature [14] which can be employed to compensate for the
programmable digital counter (integrator). During the start- offset value. However, here a modified approach is introduced
up phase, the estimation is achieved using a binary search to minimize the hardware overhead. Figure 8 shows two pos-
algorithm. Following the initial phase, the FSM continues sible cases depending upon the polarity of comparator offset
tracking the peak value using a bang-bang approach. A simple voltage. If the average of the two consecutive samples taken
R-C filter has been utilized at the output of DAC in order to on phase 0◦ and 180◦ is positive, i.e. (h1 + h2 )/2 > 0, then

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 Fig. 8. Mechanism for offset detection, and polarity checking.
Fig. 10. The proposed peak detector output.

by the DAC, follow a bang-bang pattern, as expected. The

bang-bang amplitude noise depends on the resolution of the
DAC (here, an 8-bit DAC is utilized). The filter after the
DAC takes the average of the binary signal levels in order to
remove the high frequency bang-bang noise, and produce an
output with finer resolution. The PD circuit is implemented
Fig. 9. Phase correction algorithm for accurate sampling moment. in 0.18µm technology and the power consumption without
the digital calibration part is 438.5nW. This methodology can
be implemented in various applications like power system
the comparator has positive offset. Otherwise, if the average emulator as the emulator generates sinusoidal signal.
is negative, i.e. (h01 + h02 )/2 < 0, then the offset voltage is
negative. The estimated offset voltage will be stored and R EFERENCES
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