Karnatak Law Society’s

Gogte Institute of Technology, Udyambag, Belagavi

Department of Electronics and Communication Engineering

Roll No. ________ USN:______________

Karnatak Law Society’s

GOGTE INSTITUTE OF TECHNOLOGY
UDYAMBAG, BELAGAVI-590008

Laboratory Record
Academic year 2024 - 2025

Name: _________________________________Semester:_____ Div:_____

Program (Branch): B.E (Electronics and Communication Engineering)

Title of the Lab Course: Applied Electronic Circuits Laboratory

Lab Course Code: 22EC32

Marks Scored (Maximum 10 marks): ___________

Signature of Student Signature of faculty member

| AEC Lab 22EC32
 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Index Sheet
Marks
Expt. scored Faculty
Date Title of the Experiment
No. Signature
(max. 10)
0 Introduction to signal generator,
measuring devices and other electronic
components.
1- A Mesh analysis for DC circuits.

1- B Node analysis for DC circuits.

2- A Verification of Thevenin’s Theorem.

2- B Verification of Maximum Power

Transfer Theorem.
3- A Diode Clipping circuits

3- B Diode Clamping circuits

4-A Transistor biasing using fixed bias

circuit.
4-B Transistor biasing using voltage
divider bias circuit.
5 A. Bypassed BJT RC coupled
amplifier
B. Un-bypassed BJT RC coupled
amplifier.
6 FET amplifier

7 MOSFET Characteristics

8 MOSFET Amplifier using simulation

tool

Average (Out of 10 marks)

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

DEPARTMENT VISION
The Electronics and Communication Engineering department
shall impart quality technical education and entrepreneurship
skills to develop creative individuals to face changing global
scenario.

DEPARTMENT MISSION
To augment the national talent pool, with Electronics and
Communication Engineers having all-encompassing technical
knowledge, principled practices and nationalistic outlook.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Course Outcome (COs)

Learning
At the end of the course, the student will be able to PO(s) PSO(s)
Level

Apply the knowledge network theorems for a given electrical 1,2,3,5,12 1

1. Ap
networks

2. Analyze the performance of transistor circuit parameters. An 1,2,3,5,12 1

3. Design /analyze the transistor amplifier circuits for the An 1,2,3,5,9,12 1

desired operating characteristics.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 1 Date:

Title: Mesh analysis and Node Analysis

Objective: To conduct an experiment to verify mesh analysis and node analysis.

Experimental Requirements:
Requirement Specification Quantity
Resistors 1KΩ, 2.2KΩ, 1 each
3.3KΩ
Regulated Power Supply 0-30V, 1A 2
Connecting wires, patch chords, BNCs
Multimeter 0-20V 1 each

Theory:
Mesh Current Analysis is a technique used to find the currents circulating around a loop or mesh
with in any closed path of a circuit. While Kirchhoff´s Laws give us the basic method for
analysing any complex electrical circuit, there are different ways of improving upon this method
by using Mesh Current Analysis or Nodal Voltage Analysis that results in a lessening of the
math’s involved and when large networks are involved this reduction in maths can be a big
advantage.

Mesh Current Analysis Circuit:

One simple method of reducing the amount of math’s involved is to analyse the circuit using
Kirchhoff’s Current Law equations to determine the currents, I1 and I2 flowing in the two resistors.
Then there is no need to calculate the current I3 as its just the sum of I1 and I2. So Kirchhoff’s
second voltage law simply becomes:

 Equation No 1 : 10 = 50I1 + 40I2

 Equation No 2 : 20 = 40I1 + 60I2

Circuit Diagram:
| AEC Lab 22EC32
 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

CIRCUIT DIAGRAM: MESH ANALYSIS

Procedure:

1. Measure all the resistors using multimeter and note the same.
2. Connect the circuit as per the circuit diagram.
3. Theoretically calculate the mesh currents by applying mesh analysis.
3. Measure the mesh currents and tabulate.
4. Compare the theoretically obtained mesh current values with practically measured values.

NODE ANALYSIS

Theory:
Nodal Voltage Analysis finds the unknown voltage drops around a circuit between different nodes
that provide a common connection for two or more circuit components.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

So by adding together all these nodal voltages the net result will be equal to zero. Then, if there are
“n” nodes in the circuit there will be “n-1” independent nodal equations and these alone are
sufficient to describe and hence solve the circuit.

At each node point write down Kirchhoff’s first law equation, that is: “the currents entering a
node are exactly equal in value to the currents leaving the node” then express each current in
terms of the voltage across the branch. For “n” nodes, one node will be used as the reference node
and all the other voltages will be referenced or measured with respect to this common node

Circuit Diagram:

CIRCUIT DIAGRAM: NODE ANALYSIS

PROCEDURE
1. Measure all the resistors using multimeter and note the same.
2. Connect the circuit as per the circuit diagram.
3. Theoretically calculate the mesh currents by applying node analysis.
3. Measure the node voltages.
4. Compare the theoretically obtained values with practically measured values.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Calculations:- Mesh Analysis

Node Analysis:

Observations:
MESH ANALYSIS

R1 R2 R3 I1 I2
Theoretical Value
Measured Value

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

NODE ANALYSIS
R1 R2 R3 R4 R5 V1 V2 I1 I2 I3
Theoretical Value
Measured Value

Result and Conclusion:

Applications of the experiment:

Outcome of the experiment:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Evaluation:

Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 2 Date:

Title: Thevenin’s theorem and Maximum power transfer theorem

Objective: To conduct an experiment to verify Thevenin’s theorem and Maximum power transfer
theorem.

Experimental Requirements:
Requirement Specification Quantity
Resistors 1KΩ, 2.2KΩ, 3.3KΩ,3.9 1 each
KΩ 10KΩ
Regulated Power Supply 0-30V, 1A 2
Decade resistance box 1
Multimeter 0-20V 1 each
Connecting wires, patch chords,
BNCs

Theory:
Thevenin’s Theorem

Thevenin theorem is an analytical method used to change a complex circuit into a simple
equivalent circuit consisting of a single resistance in series with a source voltage. Thevenin’s
Theorem states that “Any linear circuit containing several voltages and resistances can be replaced
by just one single voltage in series with a single resistance connected across the load“. In other
words, it is possible to simplify any electrical circuit, no matter how complex, to an equivalent
two-terminal circuit with just a single constant voltage source in series with a resistance (or
impedance) connected to a load as shown below. Thevenins Theorem is especially useful in the
circuit analysis of power or battery systems and other interconnected resistive circuits where it will
have an effect on the adjoining part of the circuit.

Figure 2 (a): Thevenins Theorem Equivalent Circuit

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

As far as the load resistor RL is concerned, any complex “one-port” network consisting of multiple
resistive circuit elements and energy sources can be replaced by one single equivalent resistance
Rs and one single equivalent voltage Vs. Rs is the source resistance value looking back into the
circuit and Vs is the open circuit voltage at the terminals.

Maximum Power Transfer

Maximum power is transferred when the value of that load resistance is equal to the equivalent
resistance of the supplying network. The Maximum Power Transfer Theorem is another useful
circuit analysis method to ensure that the maximum amount of power will be dissipated in the load
resistance when the value of the load resistance is exactly equal to the resistance of the power
source. The relationship between the load impedance and the internal impedance of the energy
source will give the power in the load.

Figure 2(b): Thevenins Equivalent Circuit

In our Thevenin equivalent circuit above, the maximum power transfer theorem states “the
maximum amount of power will be dissipated in the load resistance if it is equal in value to the
Thevenin or Norton source resistance of the network supplying the power”. In other words, the
load resistance resulting in greatest power dissipation must be equal in value to the equivalent
Thevenin source resistance, then RL = RS but if the load resistance is lower or higher in value than
the Thevenin source resistance of the network, its dissipated power will be less than maximum.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Circuit Diagram:

Figure 2(c): Thevenin’s Theorem

Procedure:
A. Thevenin’s Theorem
1. Measure all the resistors using mustimeter and note the same.
2. Connect the circuit as per the circuit diagram.
3. Theoretically calculate Vth and Rth by applying Thevenin's Theorem.
4. Measure the output voltage across RL and tabulate.
5. Measure open circuit voltage Vth by disconnecting RL from the circuit
6. Using mustimeter measure Rth by replacing voltage source by short.
7. Connect the Thevenin's equivalent circuit with the values obtained in step 5 and 6, connect RL
and Measure output voltage across the RL.
8. Compare the theoretically obtained values with practically measured values.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Circuit Diagram: Thevenin’s Equivalent circuit

Figure: Thevenin’s Equivalent circuit

Procedure:
B. Maximum power transfer theorem
1. Measure all the resistors using multimeter and note the same.
2. Connect the circuit as per the circuit diagram.
3. Theoretically calculate Vth and Rth by applying Thevenin's Theorem.
4. Measure the output voltage across RL and tabulate.
5. Measure open circuit voltage Vth by disconnecting RL from the circuit
6. Using multimeter measure Rth by replacing voltage source by short.
7. Connect the Thevenin's equivalent circuit with the values obtained in step 5 and 6, connect
decade resistance box as RL and measure Vo across RL
8. Calculate power consumed by RL by using the equation
P =Vo2/ RL
9. Plot a graph of RL versus P.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Calculations:
A. Thevenin’s Theorem
Vth = V, Rth = KΩ

B. Maximum Power transfer theorem

Observations:
Output voltage of the circuit (Fig:2.c) = V
Output voltage of Thevenin’s equivalent circuit = V

R1 R2 R3 RL VTH RTH
Theoretical Value
Measured Value

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Tabulation:

RL Vo P=Vo2 /RL

Result and Conclusion:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Applications of the experiment performed:

Outcome of the experiment:

Evaluation:
Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 3 Date:

Title: Study of Diode Clipping and Clamping circuits

Objective 3.a: To demonstrate the working of diode clipping circuits for the given
specification. Observe the changes in the output and transfer characteristics in by changing the
levels of the reference voltages.
Objective 3.b: To design and demonstrate clamper circuits for the given specifications. Observe
the variations in the clamping levels by changing the RC time constant and also DC reference
voltage.
Experimental Requirements:
Requirement Specification Quantity
Diode 1N4001 2
Resistor 100kΩ,10kΩ, ½ W 1
Capacitor 1µF, 63V 1
Signal Generator 0-20MHz, 15V 1
CRO - 1
DC Voltage Source 0-30V 2
Patch cords - 10

Theory:
The Diode Clipper, also known as a Diode Limiter, is a wave shaping circuit that takes an input
waveform and clips or cuts off its top half, bottom half or both halves together.
Positive Diode Clipping Circuits

In this diode clipping circuit, the diode is forward biased (anode more positive than cathode)
during the positive half cycle of the sinusoidal input waveform. For the diode to become forward
biased, it must have the input voltage magnitude greater than +0.7 volts (0.3 volts for a germanium
diode).

When this happens the diodes begins to conduct and holds the voltage across itself constant at
0.7V until the sinusoidal waveform falls below this value. Thus the output voltage which is taken
across the diode can never exceed 0.7 volts during the positive half cycle.

During the negative half cycle, the diode is reverse biased (cathode more positive than anode)
blocking current flow through itself and as a result has no effect on the negative half of the

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

sinusoidal voltage which passes to the load unaltered. Thus the diode limits the positive half of the
input waveform and is known as a positive clipper circuit.

Negative Diode Clipping Circuit

Here the reverse is true. The diode is forward biased during the negative half cycle of the
sinusoidal waveform and limits or clips it to –0.7 volts while allowing the positive half cycle to
pass unaltered when reverse biased. As the diode limits the negative, half cycle of the input
voltage it is therefore called a negative clipper circuit.

Biased Diode Clipping Circuits

To produce diode-clipping circuits for voltage waveforms at different levels, a bias voltage, VBIAS
is added in series with the diode to produce a combination clipper as shown. The voltage across
the series combination must be greater than VBIAS + 0.7V before the diode becomes sufficiently
forward biased to conduct. For example, if the VBIAS level is set at 4.0 volts, then the sinusoidal
voltage at the diode’s anode terminal must be greater than 4.0 + 0.7 = 4.7 volts for it to become
forward biased. Any anode voltage levels above this bias point are clipped off.

Positive Bias Diode

Likewise, by reversing the diode and the battery bias voltage, when a diode conducts the negative
half cycle of the output waveform is held to a level –VBIAS – 0.7V as shown.

This voltage divider biasing configuration is the most widely used transistor biasing method. The
emitter diode of the transistor is forward biased by the voltage value developed across resistor RB2.
In addition, voltage divider network biasing makes the transistor circuit independent of changes in
beta as the biasing voltages set at the transistors base, emitter, and collector terminals are not
dependant on external circuit values.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Negative Bias Diode

A variable diode clipping or diode limiting level can be achieved by varying the bias voltage of the
diodes. If both the positive and the negative half cycles are to be clipped, then two biased clipping
diodes are used. However, for both positive and negative diode clipping, the bias voltage need not
be the same. The positive bias voltage could be at one level, for example 4 volts, and the negative
bias voltage at another, for example 6 volts as shown.

Reference- https://www.electronics-tutorials.ws/diode/diode-clipping-circuits.html

Circuit Diagram:
Circuit Diagram: FOR ALL THE CIRCUITS, R=10kΩ,Vi=8V(p-p),V=2V
1. Unbiased Series Positive clipper 2. Unbiased Series Negative clipper

3. Biased Series Positive clipper 4. Biased Series Negative clipper

5.Biased Parallel Positive clipper 6.Double ended clipper

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Procedure: Clipping Circuits

1. Connect the circuit as per the circuit diagram.
2. Apply a sinusoidal signal of 8V (p-p) and 1 kHz from signal generator.
3. Observe the clipping levels on CRO and note the output voltage.
4. Observe transfer characteristics for all the circuits on CRO and note the same in the
observation book.
5. Plot all the output voltage waveforms on graph sheet with proper scale.
Procedure: Clamping Circuits
1. Connect the circuit as per the circuit diagram with C=10μF,R=100KΩ,diode 1N4001.
2. Apply sine wave of 1KHz,6V (p-p) from signal generator.
3. Observe the output on CRO ( in DC mode) and measure the output voltage (p-p)
4. Observe the output by changing R to 10Ω retain the value of C

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Calculations:
A. Clipper circuit

B. Clamper circuit

Observations:
1) Clipper circuit

2) Clamper circuit

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Result and Conclusion:

Applications of the experiment performed:

Outcome of the experiment:

Outcome of the experiment:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Evaluation:

Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 4 Date:

Title: Study of Transistor Biasing Circuits

Objective: To design/analyse a fixed bias and voltage divider bias circuit, and observe stability
by changing β of the given transistor in CE configuration.

Experimental Requirements:

Requirement Specification Quantity

Transistor SL-100 (with different β 2
values)

Resistors From design values -

CRO 1
Signal Generator 0-20MHz, 15V 1
DC Voltage Source 0-30 V 2
patch chords 10

Theory:
Transistor Biasing is the process of setting a transistors DC operating voltage or the transistor so
that any AC input signal can amplify current conditions to the correct level correctly. One of the
most frequently used biasing circuits for a transistor circuit is with the self-biasing of the emitter-
bias circuit were one or more biasing resistors are used to set up the initial DC values for the three
transistor currents, ( IB ), ( IC ) and ( IE ).

The two most common forms of bipolar transistor biasing are: Beta Dependent and Beta
Independent. Transistor bias voltages are largely dependent on transistor beta, ( β ) so the biasing
set up for one transistor may not necessarily be the same for another transistor as their beta values
may be different. Transistor biasing can be achieved either by using a single feedback resistor or
by using a simple voltage divider network to provide the required biasing voltage.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Fixed Base Bias

Figure 3(a): Fixed Base Biasing a Transistor

The circuit shown is called as a “fixed base bias circuit”, because the transistors base current, IB
remains constant for given values of Vcc, and therefore the transistors operating point must also
remain fixed. This two-resistor biasing network is used to establish the initial operating region of
the transistor using a fixed current bias.

Voltage Divider Bias

Figure 3(b): Fixed Base Biasing a Transistor

Here the common emitter transistor configuration is biased using a voltage divider network to
increase stability. The name of this biasing configuration comes from the fact that the two resistors
RB1 and RB2 form a voltage or potential divider network across the supply with their centre point
junction connected the transistors base terminal as shown.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

This voltage divider biasing configuration is the most widely used transistor biasing method. The
emitter diode of the transistor is forward biased by the voltage value developed across resistor RB2.
In addition, voltage divider network biasing makes the transistor circuit independent of changes in
beta as the biasing voltages set at the transistors base, emitter, and collector terminals are not
dependant on external circuit values.

Circuit Diagram:
1) Fixed Bias Circuit
Given VCC = 10V, IC = 4mA, VCE = 6V, VBE = 0.6V, β (obtained from transistor)

Fig 3(c): Fixed bias circuit diagram

2) Voltage Divider Bias Circuit
Given VCC = 16V, R1= 84KΩ, R2=10KΩ, RC =10KΩ, RE=1KΩ, VBE = 0.6V, β (obtained from
transistor)

Fig. 3(d): Voltage divider bias circuit diagram

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Procedure:
1. Assemble the Fixed bias circuit on breadboard with design values of resistors and β
(Fig. 3(a)).
2. Apply VCC and measure Ic, VCE, and VBE and record the readings in the table.
3. Without changing bias resistors, change the transistors with other β values and repeat the
Above step.
4. Repeat the above steps using the Voltage divider bias circuit and tabulate all the readings
Calculations:
A. For Fixed Bias Circuit

B. For Voltage Divider Bias Circuit

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Observations:
1) For Fixed Bias Circuit
Readings for DC condition of Fixed bias circuit
β value VBE (V) VCE (V) IC (mA)

2) Voltage Divider Bias Circuit

Readings for DC condition of Voltage divider bias circuit
β value VBE (V) VCE (V) IC (mA)

Result and Conclusion:

Applications of the experiment performed:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Outcome of the experiment:

Evaluation:
Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 5 Date:

Title: BJT RC Coupled Amplifier

Objective: To design un-bypassed and bypassed RC coupled amplifier and to determine the
bandwidth.

Experimental Requirements:
Sl. No. Components/Equipment’s
Specification/Range Quantity
1. Transistor SL100 1

2. Resistor 84KΩ, 10KΩ, 10KΩ, 1KΩ 1

3. Capacitor 0.34μF, 0.34μF, 3.3μF 1

4. DRB 1

5. CRO 1

6. Signal generator 0-20MHz, 15V 1

7. DC Voltage Source 0-30V 2

8. Patch Chords 10

Pin Configuration:

Theory:

The constructional details of a two-stage RC coupled transistor amplifier circuit are as follows.
The two stage amplifier circuit has two transistors; connected in CE configuration and a common
power supply VCC is used. The potential divider network R1 and R2 and the resistor Re form the
biasing and stabilization network. The emitter by-pass capacitor Ce offers a low reactance path to
the signal. The resistor RL is used as a load impedance. The input capacitor Cin present at the initial
stage of the amplifier couples AC signal to the base of the transistor. The capacitor CC is the
coupling capacitor that connects two stages and prevents DC interference between the stages and

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

controls the shift of operating point. The figure below shows the circuit diagram of RC coupled
amplifier.

Operation of RC Coupled Amplifier

When an AC input signal is applied to the base of first transistor, it gets amplified and appears at
the collector load RL which is then passed through the coupling capacitor CC to the next stage. This
becomes the input of the next stage, whose amplified output again appears across its collector load.
Thus the signal is amplified in stage by stage action. The important point that has to be noted here
is that the total gain is less than the product of the gains of individual stages. This is because when
a second stage is made to follow the first stage, the effective load resistance of the first stage is
reduced due to the shunting effect of the input resistance of the second stage. Hence, in a
multistage amplifier, only the gain of the last stage remains unchanged. As we consider a two
stage amplifier here, the output phase is same as input. Because the phase reversal is done two
times by the two stage CE configured amplifier circuit.
Circuit Diagram:
1) RC Coupled Amplifier without bypass capacitor

Fig. 4 (a) RC coupled amplifier without bypass capacitor

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

2) RC coupled amplifier with bypass capacitor

Fig. 4 (b) RC coupled amplifier with bypass capacitor

Procedure:
1. Rig up the circuit as per circuit diagram for un-bypassed RC coupled amplifier circuit
(Fig.4 (a)).
2. Provide VCC=16Vand set the input voltage sufficient to get the sinusoidal output.
3. Vary input frequency for wide range (100Hz to 1000 kHz) and note down Vo (p-p) and
determine the gain and also calculate decibel gain.
4. Repeat the same procedure for RC coupled amplifier with bypass capacitor (Fig. 4(b)).
5. Plot the frequency response curve (Fig. 4(c)) for both un-bypassed and bypassed RC coupled
amplifier.
6. From each curve obtain lower and upper cutoff frequencies (f1 and f2 respectively) and find the
bandwidth of the amplifier.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Calculations:
(From Frequency Response curve)
a) For RC Coupled Amplifier without bypass capacitor
f 1=
f 2=
Bandwidth= (f2- f1) =

b) For RC coupled amplifier with bypass capacitor

f 1=
f 2=
Bandwidth= (f2- f1) =
Observations:
1. RC coupled amplifier without bypass capacitor
Input voltage (p-p) Vin = ______ V
Frequency Output Voltage Voltage Gain (Gm) Voltage Gain (in dB)
Vo (p-p in V) (Vo/Vin) 20 log (Vo/ Vin)

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

2. RC coupled amplifier with bypass capacitor

Input voltage (p-p) Vin = ______ V
Frequency Output Voltage Voltage Gain (Gm) = Voltage Gain (in dB)
Vo (p-p in V) (Vo/Vin) 20 log (Vo/ Vin)

Result and Conclusion:

Applications of the experiment performed:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Outcome of the experiment:

Evaluation:

Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 6 Date:

Title: FET Amplifier

Objective: To obtain the frequency response of the FET amplifier with bypass capacitor to
determine the bandwidth.
Experimental Requirements:

Sl. No. Components/Equipment’s Specification/Range Quantity

1 FET BFW 11 1
2 Resistor 560Ω , 1MΩ , 5kΩ 1 each
3 Capacitor 1µF, 10µF 1
4 CRO 1
5 Signal Generator 20MHz, 15V 1
6 DC Voltage Source 0-30V 2
7 Patch Cords 10

Theory:
The common source FET amplifier has one important advantage compared to the common-emitter
BJT amplifier in that the FET has extremely high input impedance and along with a low noise
output makes them ideal for use in amplifier circuits that require very small input voltage signals.

Transistor amplifier circuits such as the common emitter amplifier are made using Bipolar
Transistors, but small signal amplifiers can also be made using Field Effect Transistors. The
design of an amplifier circuit based around a junction field effect transistor (N-channel FET for
this tutorial) or even a metal oxide silicon FET or “MOSFET” is exactly the same principle as that
for the bipolar transistor circuit used for a Class-A amplifier circuit. Firstly, a suitable quiescent
point or “Q-point” needs to be found for the correct biasing of the JFET amplifier circuit with
single amplifier configurations of Common-source (CS), Common-drain (CD) or Source-follower
(SF) and the Common-gate (CG) available for most FET devices.

The amplifier circuit consists of an N-channel JFET, but the device could also be an equivalent N-
channel depletion-mode MOSFET as the circuit diagram would be the same just a change in the
FET, connected in a common source configuration. The JFET gate voltage Vg is biased through
the potential divider network set up by resistors R1 and R2 and is biased to operate within its
saturation region which is equivalent to the active region of the bipolar junction transistor.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate current allowing
the gate to be treated as an open circuit. Then no input characteristics curves are required.

Circuit Diagram:
1) RC Coupled

Fig. 5(a) FET amplifier with bypass capacitor

Procedure:
1. Connections are made as per the circuit diagram Fig. 5(a).
2. Set the p-p input voltage Vin and frequency sufficient to get the sinusoidal output.
3. Vary the input frequency over a wide range and note down the p-p output voltage V0.
4. Calculate the gain and gain in dB for each frequency setting.
5. Tabulate the result and plot frequency response graph
Calculations:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Observations:
FET amplifier with bypass capacitor
Input voltage (p-p) Vi =________
Frequency Output Voltage (p-p) Voltage Gain = Voltage Gain (in dB)
Vo (in V) (Vo/ Vin) 20 log (Vo/ Vin)

Result and Conclusion:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Applications of the experiment performed:

Outcome of the experiment:

Evaluation:
Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome
Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 7 Date:

Title: N CHANNEL MOSFET CHARACTERISTICS

Objective: To plot the transfer and drain characteristics of n-channel MOSFET Using
simulation tool

Theory:

In a MOSFET, current flows from the drain terminal to the source terminal through a
semiconductor channel. A voltage applied to a third terminal denoted, as the gate.MOSFETs
can be an n-channel either type or a p-channel type controls the resistance of the channel, and
therefore its ability to conduct current. In an n- channel, MOSFET a positive voltage is applied
to the drain terminal for operation while in a p-channel MOSFET a negative voltage is applied
to the drain terminal for operation. An n-channel and p-channel type MOSFET may be one of
two modes; enhancement mode or depletion mode. The enhancement mode MOSFET is
normally “off” (in cutoff and conducting no current) when no voltage is applied to the gate and
is “on” (in saturation and conducting current) when a voltage greater than the gate-to- source
threshold is applied to the gate. The depletion mode MOSFET is normally “on” (in saturation
and conducting current) when no voltage is applied to the gate and is “off” (in cutoff and not
conducting current) when a voltage more negative than the gate-to-source threshold is applied
to the gate.
Transfer Characteristics:
In most MOSFET applications, an input signal is the gate voltage VG and the output is the
drain current ID . The ability of MOSFET to amplify the signal is given by the output/input
ratio: the transconductance, gm = dID /dVGS with VDS constant
Drain Characteristics:
MOSFET operates in three operation mode, Cut-off when V GS <Vt, Linear mode when VGS
> Vth and VDS < ( VGS – Vth ) and Saturation when VGS > Vth and VDS≥( VGS – Vth ).
Pinch off occurs when VDS = VS,at= VGS – Vt. The drain resistance, Rd = dVDS/dI D with
VGS constant

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Circuit diagram, input/output plots:

Fig7(a). Circuit diagram

Fig 7(b). Drain Characteristics and Transfer Characteristics

Procedure:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Observation and Conclusion:

Applications of the experiment performed:

Outcome of the experiment:

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Evaluation:

Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome

Total 10
Checked on
Signature of the
faculty

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Experiment No: 8 Date:

Title: N CHANNEL E-MOSFET AMPLIFIER

Objective: To obtain the frequency response of the n-channel E-MOSFET amplifier withbypass
capacitor to determine the bandwidth using simulation tool.

Theory:

An amplifier that uses Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)

technology is known as a MOSFET amplifier. MOSFET is also called the MOS (metal-oxide-
silicon) transistor and it is one kind of insulated-gate field-effect transistor. So this transistor is
fabricated through silicon material.

A MOSFET amplifier circuit is shown below. A MOSFET amplifier simple circuit diagram is
shown below. In this circuit, the drain voltage (VD), the drain current (ID), the gate-source
voltage (VGS) & the locations of gate, source & drain are mentioned through the letters “G”,
“S”, and “D”.

Generally, MOSFETs work in three regions like Linear/Ohmic or Cut-off & Saturation.
Among these three regions, when MOSFETs are used as amplifiers, they should operate in an
ohmic region where the current flow throughout the device increases when the applied voltage
is increased.

MOSFET can be used as a small-signal linear amplifier within many applications. Usually, in
the amplifier circuits, field-effect transistors work within the saturation region. So in this
region, the flow of current does not depend on drain voltage (VD) but the current is the main
function of the Gate voltage (VG) simply. In these amplifiers, normally the operatingg point is
within the saturation region.

In the MOSFET amplifier, a small change within gate voltage will generate a large change
within drain current like in JFET. So, MOSFET will increase a weak signal’s strength;
consequently, it acts as an amplifier.

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Circuit diagram.

Frequency Response:

Fig 7(b). Drain Characteristics and Transfer Characteristics

| AEC Lab 22EC32

 Karnatak Law Society’s
Gogte Institute of Technology, Udyambag, Belagavi
Department of Electronics and Communication Engineering

Procedure:

Observation and Conclusion:

Applications of the experiment performed:

| AEC Lab 22EC32

 Outcome of the experiment:

Evaluation:

Maximum Marks
marks Scored
Conduction of 5
the experiment
Calculations, 5
results, graph,
conclusion &
outcome

Total 10
Checked on
Signature of the
faculty