ATmega32A

15. 8-bit Timer/Counter0 with PWM

15.1 Features
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

15.2 Overview
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram
of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual placement of I/O pins, refer to “Pinout
ATmega32A” on page 10. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the “Register Description” on page 86.

Figure 15-1. 8-bit Timer/Counter Block Diagram

TCCRn

count TOVn
clear (Int.Req.)
Control Logic
direction clk Tn Clock Select

Edge
Tn
Detector
BOTTOM TOP

( From Prescaler )
DATABUS

Timer/Counter
TCNTn
=0 = 0xFF OCn
(Int.Req.)

Waveform
= Generation
OCn

OCRn

15.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbrevi-
ated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure
since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)

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its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The
result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on
the Output Compare Pin (OC0). Refer to “Output Compare Unit” on page 78. for details. The compare match event
will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request.

15.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise
form must be used, that is, TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 15-1 are also used extensively throughout the document.
Table 15-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0 Register. The assignment is dependent
on the mode of operation.

15.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Regis-
ter (TCCR0). For details on clock sources and prescaler, refer to “Timer/Counter0 and Timer/Counter1 Prescalers”
on page 90.

15.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 15-2 shows a
block diagram of the counter and its surroundings.

Figure 15-2. Counter Unit Block Diagram

TOVn
DATA BUS (Int. Req.)

Clock Select

count Edge
Tn
clear clkTn Detector
TCNTn Control Logic
direction

( From Prescaler )

BOTTOM TOP

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.

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TOP Signalize that TCNT0 has reached maximum value.

BOTTOM Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clkT0 ). clk T0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how
waveforms are generated on the Output Compare output OC0. For more details about advanced counting
sequences and waveform generation, refer to “Modes of Operation” on page 80.
The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by the WGM01:0 bits.
TOV0 can be used for generating a CPU interrupt.

15.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0). Whenever
TCNT0 equals OCR0, the comparator signals a match. A match will set the Output Compare Flag (OCF0) at the
next timer clock cycle. If enabled (OCIE0 = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag
generates an output compare interrupt. The OCF0 Flag is automatically cleared when the interrupt is executed.
Alternatively, the OCF0 Flag can be cleared by software by writing a logical one to its I/O bit location. The wave-
form generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits
and Compare Output mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for
handling the special cases of the extreme values in some modes of operation (refer to “Modes of Operation” on
page 80).
Figure 15-3 shows a block diagram of the output compare unit.

Figure 15-3. Output Compare Unit, Block Diagram

DATA BUS

OCRn TCNTn

= (8-bit Comparator )

OCFn (Int.Req.)

top

bottom
Waveform Generator OCn
FOCn

WGMn1:0 COMn1:0

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The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the nor-
mal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0
directly.

15.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC0) bit. Forcing compare match will not set the OCF0 Flag or reload/clear the timer,
but the OC0 pin will be updated as if a real compare match had occurred (the COM0[1:0] bits settings define
whether the OC0 pin is set, cleared or toggled).

15.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0 to be initialized to the same value as TCNT0 with-
out triggering an interrupt when the Timer/Counter clock is enabled.

15.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the output compare unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The
easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bits in Normal mode. The
OC0 Register keeps its value even when changing between waveform generation modes.
Be aware that the COM0[1:0] bits are not double buffered together with the compare value. Changing the
COM0[1:0] bits will take effect immediately.

15.6 Compare Match Output Unit

The Compare Output mode (COM0[1:0]) bits have two functions. The Waveform Generator uses the COM0[1:0]
bits for defining the Output Compare (OC0) state at the next compare match. Also, the COM0[1:0] bits control the
OC0 pin output source. Figure 15-4 shows a simplified schematic of the logic affected by the COM0[1:0] bit setting.
The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port Con-
trol Registers (DDR and PORT) that are affected by the COM0[1:0] bits are shown. When referring to the OC0
state, the reference is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0 Register is
reset to “0”.

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Figure 15-4. Compare Match Output Unit, Schematic

COMn1
COMn0 Waveform
D Q
FOCn Generator
1
OCn
OCn Pin
0

D Q

DATA BUS
PORT

D Q

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either of
the COM0[1:0] bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction
Register (DDR) for the port pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output
before the OC0 value is visible on the pin. The port override function is independent of the Waveform Generation
mode.
The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled. Note
that some COM01:0 bit settings are reserved for certain modes of operation. Refer to “Register Description” on
page 86

15.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0[1:0] bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM0[1:0] = 0 tells the waveform generator that no action on the OC0 Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 15-3 on page 87. For
fast PWM mode, refer to Table 15-4 on page 87, and for phase correct PWM refer to Table 15-5 on page 87.
A change of the COM0[1:0] bits state will have effect at the first compare match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits.

15.7 Modes of Operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0[1:0]) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM0[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM0[1:0] bits control whether the output should be set, cleared, or toggled at a
compare match. Refer to “Compare Match Output Unit” on page 79.
For detailed timing information refer to Figure 15-8, Figure 15-9, Figure 15-10 and Figure 15-11 in “Timer/Counter
Timing Diagrams” on page 84.

15.7.1 Normal Mode

The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow

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Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the normal mode, a new counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output compare to gen-
erate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

15.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0. The
OCR0 defines the top value for the counter, hence also its resolution. This mode allows greater control of the com-
pare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-5. The counter value (TCNT0) increases until a com-
pare match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared.

Figure 15-5. CTC Mode, Timing Diagram

OCn Interrupt Flag Set

TCNTn

OCn
(COMn1:0 = 1)
(Toggle)

Period 1 2 3 4

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower
than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each com-
pare match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be
visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a
maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the
following equation:
f clk_I/O
f OCn = -----------------------------------------------
2  N   1 + OCRn 

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.

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15.7.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOTTOM. In inverting
Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope oper-
ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that
use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectifi-
cation, and DAC applications. High frequency allows physically small sized external components (coils,
capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-6. The
TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
compare matches between OCR0 and TCNT0.

Figure 15-6. Fast PWM Mode, Timing Diagram

OCRn Interrupt Flag Set

OCRn Update and

TOVn Interrupt Flag Set

TCNTn

OCn (COMn1:0 = 2)

OCn (COMn1:0 = 3)

Period 1 2 3 4 5 6 7

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the COM01:0
bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM01:0
to 3 (Table 15-4 on page 87). The actual OC0 value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0 Register at the compare
match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter
is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnPWM = ------------------
N  256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer

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clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity
of the output set by the COM01:0 bits.)

15.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM0[1:0] = 1) provides a high resolution phase correct PWM waveform genera-
tion option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from
BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC0) is cleared on the compare match between TCNT0 and OCR0 while upcounting, and set on the compare
match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the coun-
ter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count
direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase cor-
rect PWM mode is shown in Figure 15-7. The TCNT0 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small hor-
izontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0.

Figure 15-7. Phase Correct PWM Mode, Timing Diagram

OCn Interrupt Flag Set

OCRn Update

TOVn Interrupt Flag Set

TCNTn

OCn (COMn1:0 = 2)

OCn (COMn1:0 = 3)

Period 1 2 3

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the
COM01:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM01:0 to 3 (see Table 15-5 on page 87). The actual OC0 value will only be visible on the port pin if the data
direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0 Regis-
ter at the compare match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the

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OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnPCPWM = ------------------
N  510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 15-7, OCn has a transition from high to low even though there is no Compare
Match. The point of this transition is to ensure symmetry around BOTTOM. There are two cases that give a transi-
tion without Compare Match:
• OCR0A changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.

15.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 15-8 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.

Figure 15-8. Timer/Counter Timing Diagram, no Prescaling

clkI/O

clkTn
(clkI/O /1)

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

Figure 15-9 shows the same timing data, but with the prescaler enabled.

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Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clkI/O

clkTn
(clkI/O /8)

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

Figure 15-10 shows the setting of OCF0 in all modes except CTC mode.

Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)

clkI/O

clkTn
(clkI/O /8)

TCNTn OCRn - 1 OCRn OCRn + 1 OCRn + 2

OCRn OCRn Value

OCFn

Figure 15-11 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

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Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler
(fclk_I/O/8)

clkI/O

clkTn
(clkI/O /8)

TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC)

OCRn TOP

OCFn

15.9 Register Description

15.9.1 TCCR0 – Timer/Counter Control Register

Bit 7 6 5 4 3 2 1 0
FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility
with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writ-
ing a logical one to the FOC0 bit, an immediate compare match is forced on the Waveform Generation unit. The
OC0 output is changed according to its COM0[1:0] bits setting. Note that the FOC0 bit is implemented as a strobe.
Therefore it is the value present in the COM0[1:0] bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP.
The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM0[1:0]: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and
what type of Waveform Generation to be used. Modes of operation supported by the Timer/Counter unit are: Nor-
mal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.
See Table 15-2 and “Modes of Operation” on page 80.

Table 15-2. Waveform Generation Mode Bit Description(1)

WGM01 WGM00 Timer/Counter Mode of Update of TOV0 Flag
Mode (CTC0) (PWM0) Operation TOP OCR0 Set-on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0 Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX

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Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the function-
ality and location of these bits are compatible with previous versions of the timer.

• Bit 5:4 – COM0[1:0]: Compare Match Output Mode

These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0
output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction
Register (DDR) bit corresponding to the OC0 pin must be set in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table
15-3 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 15-3. Compare Output Mode, non-PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Toggle OC0 on compare match
1 0 Clear OC0 on compare match
1 1 Set OC0 on compare match

Table 15-4 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.

Table 15-4. Compare Output Mode, Fast PWM Mode(1)

COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Reserved
1 0 Clear OC0 on compare match, set OC0 at BOTTOM,
(nin-inverting mode)
1 1 Set OC0 on compare match, clear OC0 at BOTTOM,
(inverting mode)

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but
the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 82 for more details.
Table 15-5 shows the COM0[1:0] bit functionality when the WGM01:0 bits are set to phase correct PWM mode.

Table 15-5. Compare Output Mode, Phase Correct PWM Mode(1)

COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Reserved
1 0 Clear OC0 on compare match when up-counting. Set OC0 on compare match
when downcounting.
1 1 Set OC0 on compare match when up-counting. Clear OC0 on compare match
when downcounting.

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but
the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 83 for more details.

• Bit 2:0 – CS02:0: Clock Select

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The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 15-6. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/(No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.

15.9.2 TCNT0 – Timer/Counter Register

Bit 7 6 5 4 3 2 1 0
TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modify-
ing the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between
TCNT0 and the OCR0 Register.

15.9.3 OCR0 – Output Compare Register

Bit 7 6 5 4 3 2 1 0
OCR0[7:0] OCR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The Output Compare Register contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the
OC0 pin.

15.9.4 TIMSK – Timer/Counter Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare
Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs,
that is, when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.

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 ATmega32A

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when
the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.

15.9.5 TIFR – Timer/Counter Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 –
Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0
(Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare Match
Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0
changes counting direction at $00.

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 ATmega32A

16. Timer/Counter0 and Timer/Counter1 Prescalers

16.1 Overview
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different
prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0.

16.2 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fast-
est operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f CLK_I/O ).
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a fre-
quency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.

16.3 Prescaler Reset

The prescaler is free running, that is, operates independently of the clock select logic of the Timer/Counter, and it is
shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock
select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example
of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.

16.4 External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin
is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is
then passed through the edge detector. Figure 16-1 shows a functional equivalent block diagram of the T1/T0 syn-
chronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.

Figure 16-1. T1/T0 Pin Sampling

Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE

clk I/O

Synchronization Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 90