ATmega32A

28. Electrical Characteristics

28.1 Absolute Maximum Ratings*

Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or
Voltage on any Pin except RESET other conditions beyond those indicated in the
with respect to Ground.................................-0.5V to VCC+0.5V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Voltage on RESET with respect to Ground......-0.5V to +13.0V conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current VCC and GND Pins......................... 200.0 mA and

400.0 mA TQFP/MLF

28.2 DC Characteristics
TA = -40C to 85C, VCC = 2.7 V to 5.5 V (Unless Otherwise Noted)
Symbol Parameter Condition Min Typ Max Units

Input Low Voltage except VCC = 2.7 - 5.5

VIL -0.5 0.2 VCC(1) V
XTAL1 and RESET pins VCC = 4.5 - 5.5
Input High Voltage except VCC = 2.7 - 5.5
VIH 0.6 VCC(2) VCC + 0.5 V
XTAL1 and RESET pins VCC = 4.5 - 5.5
Input Low Voltage
VIL1 VCC = 2.7 - 5.5 -0.5 0.1 VCC(1) V
XTAL1 pin
Input High Voltage VCC = 2.7 - 5.5
VIH1 0.7 VCC(2) VCC + 0.5 V
XTAL1 pin VCC = 4.5 - 5.5
Input Low Voltage
VIL2 VCC = 2.7 - 5.5 -0.5 0.2 VCC V
RESET pin
Input High Voltage
VIH2 VCC = 2.7 - 5.5 0.9 VCC(2) VCC + 0.5 V
RESET pin
Output Low Voltage(3) IOL = 20 mA, VCC = 5V 0.7 V
VOL
(Ports A,B,C,D) IOL = 10 mA, VCC = 3V 0.5 V
Output High Voltage(4) IOH = -20 mA, VCC = 5V 4.2 V
VOH
(Ports A,B,C,D) IOH = -10 mA, VCC = 3V 2.2 V
Input Leakage VCC = 5.5V, pin low
IIL 1 µA
Current I/O Pin (absolute value)
Input Leakage VCC = 5.5V, pin high
IIH 1 µA
Current I/O Pin (absolute value)
RRST Reset Pull-up Resistor 30 60 85 k
Rpu I/O Pin Pull-up Resistor 20 50 k

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 ATmega32A

TA = -40C to 85C, VCC = 2.7 V to 5.5 V (Unless Otherwise Noted)

Symbol Parameter Condition Min Typ Max Units
Active 1MHz, VCC = 3V 0.6 mA
Active 4MHz, VCC = 3V 2.1 5 mA
Active 8MHz, VCC = 5V 7.5 15 mA
Power Supply Current
Idle 1MHz, VCC = 3V 0.2 mA
ICC
Idle 4MHz, VCC = 3V 0.6 2.5 mA
Idle 8MHz, VCC = 5V 2.8 8 mA
WDT enabled, VCC = 3V < 10 20 µA
Power-down Mode(5)
WDT disabled, VCC = 3V <1 10 µA

Analog Comparator VCC = 5V

VACIO 40 mV
Input Offset Voltage Vin = VCC/2
Analog Comparator VCC = 5V
IACLK -50 50 nA
Input Leakage Current Vin = VCC/2
Analog Comparator VCC = 2.7V 750
tACPD ns
Propagation Delay VCC = 4.0V 500
Notes: 1. “Max” means the highest value where the pin is ensured to be read as low
2. “Min” means the lowest value where the pin is ensured to be read as high
3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 200 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.
TQFP and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B4, should not exceed 100 mA.
4] The sum of all IOL, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 100 mA.
5] The sum of all IOL, for ports D3 - D7, should not exceed 100 mA.
6] The sum of all IOL, for ports C0 - C7, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not ensured to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 200 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.
TQFP and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B4, should not exceed 100 mA.
4] The sum of all IOH, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 100 mA.
5] The sum of all IOH, for ports D3 - D7, should not exceed 100 mA.
6] The sum of all IOH, for ports C0 - C7, should not exceed 100 mA.If IOH exceeds the test condition, VOH may exceed the
related specification. Pins are not ensured to source current greater than the listed test condition.
5. Minimum VCC for Power-down is 2.5V.

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 ATmega32A

28.3 Speed Grades

Figure 28-1. Maximum Frequency vs. VCC.

16 MHz

8 MHz
Safe Operating Area

2.7V 4.5V 5.5V

28.4 Clock Characteristics

28.4.1 External Clock Drive Waveforms

Figure 28-2. External Clock Drive Waveforms

V IH1

V IL1

28.4.2 External Clock Drive

Table 28-1. External Clock Drive

VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V
Symbol Parameter Min Max Min Max Units
1/tCLCL Oscillator Frequency 0 8 0 16 MHz
tCLCL Clock Period 125 62.5 ns
tCHCX High Time 50 25 ns
tCLCX Low Time 50 25 ns
tCLCH Rise Time 1.6 0.5 s
tCHCL Fall Time 1.6 0.5 s
Change in period from
one clock cycle to the 2 2 %
tCLCL next

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 ATmega32A

Table 28-2. External RC Oscillator, Typical Frequencies (VCC = 5V)

R [k](1) C [pF] f(2)
33 22 650kHz
10 22 2.0MHz

Notes: 1. R should be in the range 3 k - 100 k, and C should be at least 20 pF. The C values given in the table includes
pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.

28.5 System and Reset Characteristics

Table 28-3. Reset, Brown-out and Internal Voltage Reference Characteristics

Symbol Parameter Condition Min Typ Max Units
Power-on Reset Threshold
1.4 2.3 V
Voltage (rising)
VPOT
Power-on Reset Threshold
1.3 2.3 V
Voltage (falling)(1)
RESET Pin Threshold
VRST 0.2 VCC 0.9 VCC V
Voltage
Minimum pulse width on
tRST 1.5 µs
RESET Pin
Brown-out Reset Threshold BODLEVEL = 1 2.5 2.7 2.9
VBOT Voltage(2) V
BODLEVEL = 0 3.6 4.0 4.2
Minimum low voltage period BODLEVEL = 1 2 µs
tBOD for Brown-out Detection
BODLEVEL = 0 2 µs
Brown-out Detector
VHYST 50 mV
hysteresis
VBG Bandgap reference voltage 1.15 1.23 1.35 V
Bandgap reference start-up
tBG 40 70 µs
time
Bandgap reference current
IBG 10 µA
consumption

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the
device is tested down to VCC = VBOT during the production test. This ensures that a Brown-out Reset will occur
before VCC drops to a voltage where correct operation of the microcontroller is no longer ensured. The test is per-
formed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega32A.

28.6 Two-wire Serial Interface Characteristics

Table 28-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega32A Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.

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 ATmega32A

Timing symbols refer to Figure 28-3.

Table 28-4. Two-wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.5 0.3 VCC V
VIH Input High-voltage 0.7 VCC VCC + 0.5 V
(1) (2)
Vhys Hysteresis of Schmitt Trigger Inputs 0.05 VCC – V
(1)
VOL Output Low-voltage 3 mA sink current 0 0.4 V
(1) (3)(2)
tr Rise Time for both SDA and SCL 20 + 0.1Cb 300 ns
tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb(3)(2) 250 ns
(1) (2)
tSP Spikes Suppressed by Input Filter 0 50 ns
Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA
(1)
Ci Capacitance for each I/O Pin – 10 pF
fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz
fSCL  100kHz V CC – 0.4V 1000ns
---------------------------- ------------------- 
3 mA Cb
Rp Value of Pull-up resistor
fSCL > 100kHz V CC – 0.4V 300ns
---------------------------- ---------------- 
3 mA Cb

tHD;STA Hold Time (repeated) START Condition fSCL  100kHz 4.0 – µs

fSCL > 100kHz 0.6 – µs

tLOW Low Period of the SCL Clock fSCL  100kHz 4.7 – µs

fSCL > 100kHz 1.3 – µs

tHIGH High period of the SCL clock fSCL  100kHz 4.0 – µs

fSCL > 100kHz 0.6 – µs

tSU;STA fSCL  100kHz 4.7 – µs

Set-up time for a repeated START condition fSCL > 100kHz 0.6 – µs

tHD;DAT Data hold time fSCL  100kHz 0 3.45 µs

fSCL > 100kHz 0 0.9 µs

tSU;DAT Data setup time fSCL  100kHz 250 – ns

fSCL > 100kHz 100 – ns

tSU;STO Setup time for STOP condition fSCL  100kHz 4.0 – µs

fSCL > 100kHz 0.6 – µs

tBUF fSCL  100kHz 4.7 – µs

Bus free time between a STOP and START
condition fSCL > 100kHz 1.3 – µs
Notes: 1. In ATmega32A, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices connected to the Two-wire
Serial Bus need only obey the general fSCL requirement.

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 ATmega32A

Figure 28-3. Two-wire Serial Bus Timing

tof tHIGH tr

tLOW tLOW

SCL
tSU;STA tHD;STA tHD;DAT tSU;DAT
tSU;STO
SDA

tBUF

28.7 SPI Timing Characteristics

See Figure 28-4 and Figure 28-5 for details.

Table 28-5. SPI Timing Parameters

Description Mode Min Typ Max
1 SCK period Master See Table 19-4
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • tSCK ns
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low Slave 2 • tck
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
14 Hold Slave tck
15 SCK to out Slave 15
ns
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Salve 2 • tck

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 ATmega32A

Figure 28-4. SPI Interface Timing Requirements (Master Mode)

SS
6 1

SCK
(CPOL = 0)
2 2

SCK
(CPOL = 1)
4 5 3

MISO
MSB ... LSB
(Data Input)
7 8

MOSI
MSB ... LSB
(Data Output)

Figure 28-5. SPI Interface Timing Requirements (Slave Mode)

18

SS
10 16
9

SCK
(CPOL = 0)
11 11

SCK
(CPOL = 1)
13 14 12

MOSI
MSB ... LSB
(Data Input)
15 17

MISO
MSB ... LSB X
(Data Output)

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 ATmega32A

28.8 ADC Characteristics

Table 28-6. ADC Characteristics, Single Ended channels, TA = -40C to 85C
Symbol Parameter Condition Min Typ Max Units
Resolution Single Ended Conversion 10 Bits
Single Ended Conversion
VREF = 4V, VCC = 4V 1.5 LSB
ADC clock = 200kHz
Single Ended Conversion
VREF = 4V, VCC = 4V 3 LSB
ADC clock = 1MHz
Absolute Accuracy (Including INL, DNL, Single Ended Conversion
Quantization Error, Gain, and Offset Error) VREF = 4V, VCC = 4V
1.5 LSB
ADC clock = 200kHz
Noise Reduction mode
Single Ended Conversion
VREF = 4V, VCC = 4V
3 LSB
ADC clock = 1MHz
Noise Reduction mode
Single Ended Conversion
Integral Non-Linearity (INL) VREF = 4V, VCC = 4V 0.75 LSB
ADC clock = 200kHz
Single Ended Conversion
Differential Non-linearity (DNL) VREF = 4V, VCC = 4V 0.25 LSB
ADC clock = 200kHz
Single Ended Conversion
Gain Error VREF = 4V, VCC = 4V 0.75 LSB
ADC clock = 200kHz
Single Ended Conversion
Offset Error VREF = 4V, VCC = 4V 0.75 LSB
ADC clock = 200kHz
Clock Frequency 50 1000 kHz
Conversion Time 13 260 µs
(1) (2)
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
VREF Reference Voltage 2.0 AVCC V
VIN Input voltage GND VREF V
ADC conversion output 0 1023 LSB
Input bandwith 38.5 kHz
VINT Internal Voltage Reference 2.3 2.56 2.7 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
Notes: 1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.

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 ATmega32A

Table 28-7. ADC Characteristics, Differential channels, TA = -40C to 85C

Symbol Parameter Condition Min Typ Max Units
Gain = 1x 10 Bits
Resolution Gain = 10x 10 Bits
Gain = 200x 10 Bits
Gain = 1x
VREF = 4V, VCC = 5V 17 LSB
ADC clock = 50 - 200kHz
Gain = 10x
Absolute Accuracy VREF = 4V, VCC = 5V 16 LSB
ADC clock = 50 - 200kHz
Gain = 200x
VREF = 4V, VCC = 5V 7 LSB
ADC clock = 50 - 200kHz
Gain = 1x
VREF = 4V, VCC = 5V 0.75 LSB
ADC clock = 50 - 200kHz
Integral Non-Linearity (INL) Gain = 10x
(Accuracy after calibration for Offset and VREF = 4V, VCC = 5V 0.75 LSB
Gain Error) ADC clock = 50 - 200kHz
Gain = 200x
VREF = 4V, VCC = 5V 2 LSB
ADC clock = 50 - 200kHz
Gain = 1x 1.6 %
Gain Error Gain = 10x 1.5 %
Gain = 200x 0.2 %
Gain = 1x
VREF = 4V, VCC = 5V 1 LSB
ADC clock = 50 - 200kHz
Gain = 10x
Offset Error VREF = 4V, VCC = 5V 1.5 LSB
ADC clock = 50 - 200kHz
Gain = 200x
VREF = 4V, VCC = 5V 4.5 LSB
ADC clock = 50 - 200kHz
Clock Frequency 50 200 kHz
Conversion Time 65 260 µs
(1) (2)
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
VREF Reference Voltage 2.0 AVCC - 0.5 V
VIN Input voltage GND AVCC V
VDIFF Input differential voltage -VREF/Gain VREF/Gain/ V
ADC conversion output -511 511 LSB
Input bandwith 4 kHz

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 ATmega32A

Table 28-7. ADC Characteristics, Differential channels, TA = -40C to 85C (Continued)

Symbol Parameter Condition Min Typ Max Units
VINT Internal Voltage Reference 2.3 2.56 2.7 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
Notes: 1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.

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 ATmega32A

29. Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing. All current con-
sumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
square wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capac-
itance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not ensured to function properly at fre-
quencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

29.1 Active Supply Current

Figure 29-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)

1.6

1.4
5.5 V
1.2 5.0 V

1 4.5 V
ICC (mA)

4.0 V
0.8
3.6 V
3.3 V
0.6
2.7 V
0.4

0.2

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

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 ATmega32A

Figure 29-2. Active Supply Current vs. Frequency (1 - 16MHz)

18

16 5.5V

14 5.0V
12 4.5V
ICC (mA)

10
4.0V
8
3.6V
6
3.3V
4
2.7V
2

0
0 2 4 6 8 10 12 14 16
Frequency (MHz)

Figure 29-3. Active Supply Current vs. VCC (Internal

, RC Oscillator, 8MHz)

12
25 °C
10 85 °C
-40 °C
8
ICC (mA)

0
2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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 ATmega32A

Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz)

6
25 °C
85 °C
5
-40 °C

4
ICC (mA)

0
2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-5. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

1.6 25 °C
85 °C
1.4
-40 °C
1.2

1
ICC (mA)

0.8

0.6

0.4

0.2

0
2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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 ATmega32A

Figure 29-6. Active Supply Current vs. VCC (External Oscillator, 32kHz)

160

140 25 °C

120

100
ICC (uA)

80

60

40

20

0
2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.2 Idle Supply Current

Figure 29-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz)

0.7

0.6
5.5 V
0.5
5.0 V
0.4 4.5 V
ICC (mA)

4.0 V
0.3
3.6 V
3.3 V
0.2
2.7 V

0.1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

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 ATmega32A

Figure 29-8. Idle Supply Current vs. Frequency (1 MHz - 16 MHz)

7
5.5V
6
5.0V
5
4.5V
ICC (mA)

4
4.0V
3
3.6V
2
3.3V
1
2.7V

0
0 2 4 6 8 10 12 14 16
Frequency (MHz)

Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

5
-40 °C
25 °C
4 85 °C

3
ICC (mA)

0
2.5 3 3.5 4 4.5 5 5.5
VCC (V)

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 300