CS303 – Logic & Digital System Design

1) Answer the following questions for the circuit given below.

 A
x  D Q y1

Q’

B
D Q y2

Q’

clk

a. Obtain the next state and output equations, and the state table.
Present State Input Next State Output
A B x A(t+1) B(t+1) y1 y2
0 0 0 0 1 0 0
0 0 1 1 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 1
1 0 0 1 1 1 0
1 0 1 0 1 1 0
1 1 0 0 0 1 1
1 1 1 1 0 1 1

b. Draw the state diagram.

c. What does this circuit do?

Counts up when input is 0 and counts down when input is 1.

Fall 2020
 CS303 – Logic & Digital System Design
2) A sequential circuit has two inputs (A1,A0) and one output (B). The output B=1 every time the
input pattern “312” (11/01/10) is observed. Otherwise B is 0.

a. Assuming the circuit is implemented as a Moore machine, draw the corresponding state
diagram. (Also, implement using Mealy machine for exercise)

State encoding: S0: (00), S1: (01), S2: (10), S3: (11)

b. Obtain the stage diagram (use binary encoding to represent states)

Current State Input Next State Output

S1 S0 A1 A0 S1(t+1) S0(t+1) B
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 0 1 0
0 1 0 0 0 0 0
0 1 0 1 1 0 0
0 1 1 0 0 0 0
0 1 1 1 0 1 0
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 1 0
1 0 1 1 0 1 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 1

Fall 2020
 CS303 – Logic & Digital System Design

c. Derive flip-flop and output equations (using D flip-flops).

A1A0 A1A0 A1A0

S1S0 00 01 11 10 S1S0 00 01 11 10 S1S0 00 01 11 10

00 0 0 0 0 00 0 0 1 0 00 0 0 0 0

01 0 1 0 0 01 0 0 1 0 01 0 0 0 0

11 0 0 0 0 11 0 0 1 0 11 1 1 1 1

10 0 0 0 1 10 0 0 1 1 10 0 0 0 0

S1(t+1) = S1‘S0A1‘A0 S0(t+1) = A1A0 + B = S1.S0

+ S1S0‘A1A0‘ S1S0‘A1

d. Draw the corresponding circuit.

Fall 2020
 CS303 – Logic & Digital System Design
3) Consider the following two sequential circuits:

1 T y0 count T z0
clock
k

y1
T T z1

clock
k

The propagation delay of T flip-flop is tP,FF = 10 ps. The propagation delay of AND gate is tP,AND = 10 ps. Two
circuits are using the same clock. Fill the following timing diagram.

Fall 2020
 CS303 – Logic & Digital System Design
Answer:

4) Determine the minimum clock period and maximum clock frequency for the circuit given below.
The propagation delay of D flip-flop is tP,FF = 3 ns. The setup time of D flip-flop is ts = 1 ns. The
propagation delay of NAND gate is tP,NAND = 3 ns. The propagation delay of NOT gate is tP,NOT = 1 ns.

D Q D Q D Q

clock

Tmin = tP,NAND + tP,FF + tS

Tmin = 3 + 3 + 1 = 7 ns
1 1
Fmax = (1/ Tmin) = 7 ns = 7 GHz = 142.85... MHz

Fall 2020
 CS303 – Logic & Digital System Design
5) Consider the following sequential circuit and the timing values tP,FF = tP,XOR = 200.0ps, tP,AND = ts =
100.0 ps and th = 150.0 ps.

a. Find the maximum clock frequency that can be applied to the circuit.

There are two path we need to evaluate (red and blue given below).

Time for red path → tP,FF + tP,AND + ts = 200 ps + 100 ps + 100 ps = 400 ps
Time for blue path → tP,FF + ts = 200 ps + 100 ps = 300 ps

For determining clock frequency, we need to take longest path which is red.

Then, maximum clock frequency is 1/T = 1/(400 ps) = 2.5 GHz

b. Is hold time violated in the circuit? Why or why not? Express the hold time violation
condition.

Hold time should meet the condition: tP;FF + tP;COMB (for shortest path) > th

In the circuit above, we need to satisfy tP,FF > th (200 ps > 150 ps) which si satisfied. So, there
is NO hold time violation.

Hold time violation condition is tP,FF < th

Fall 2020
 CS303 – Logic & Digital System Design
5) Design a counter with D flip-flops that goes through the following repeated sequence: 0, 1, 2, 4, 5,
6, 0, 1, 2, ... Treat unused states 011 and 111 as don’t care conditions, i.e. we don’t care what their
next states are. Draw its logic diagram.

Present State Next State FFs (same as next state)

Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 0 0
0 1 1 X X X X X X
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 0 0 0 0 0 0
1 1 1 X X X X X X

Q1Q0 Q1Q0 Q1Q0

Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10

0 0 0 X 1 0 0 1 X 0 0 1 0 X 0

1 1 1 X 0 1 0 1 X 0 1 1 0 X 0

D2 = Q1 ⊕ Q2 D1 = Q0 D0 = Q0’.Q1’

Circuit: Counter outputs are (Q2, Q1, Q0)

Fall 2020
 CS303 – Logic & Digital System Design
6) Draw logic diagram of the circuit that would result from synthesizing the following Verilog
module.

module sample_question (A, B, clk, result);

input [2:0] A, B;
input clk;
output [2:0] result;
reg [2:0] result;

always @ (posedge clk)

if (A == B) result <= A;
else result <= B;
endmodule

(A==B) can be represented as ((A[0] ⊕ B[0]) + (A[1] ⊕ B[1]) + (A[2] ⊕ B[2]))’

Circuit:

Fall 2020