ATmega16(L)

also assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret

C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}

21
2466T–AVR–07/10
 ATmega16(L)

The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret

C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}

EEPROM Write During When entering Power-down Sleep mode while an EEPROM write operation is active, the
Power-down Sleep EEPROM write operation will continue, and will complete before the Write Access time has
Mode passed. However, when the write operation is completed, the Oscillator continues running, and
as a consequence, the device does not enter Power-down entirely. It is therefore recommended
to verify that the EEPROM write operation is completed before entering Power-down.

Preventing EEPROM During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
Corruption too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

22
2466T–AVR–07/10
 ATmega16(L)

EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This
can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the
internal BOD does not match the needed detection level, an external low VCC Reset Protec-
tion circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.

I/O Memory The I/O space definition of the ATmega16 is shown in “Register Summary” on page 331.
All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed
by the IN and OUT instructions, transferring data between the 32 general purpose working regis-
ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-
accessible using the SBI and CBI instructions. In these registers, the value of single bits can be
checked by using the SBIS and SBIC instructions. Refer to the Instruction Set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must
be used. When addressing I/O Registers as data space using LD and ST instructions, $20 must
be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as
set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and Peripherals Control Registers are explained in later sections.

23
2466T–AVR–07/10
 ATmega16(L)

System Clock
and Clock
Options

Clock Systems Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks
and their need not be active at a given time. In order to reduce power consumption, the clocks to modules
Distribution not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 32. The clock systems are detailed Figure 11.

Figure 11. Clock Distribution

Asynchronous General I/O Flash and
ADC CPU Core RAM
Timer/Counter Modules EEPROM

clkADC

clkI/O AVR Clock clkCPU

Control Unit

clkASY clkFLASH

Reset Logic Watchdog Timer

Source Clock Watchdog Clock

Clock Watchdog
Multiplexer Oscillator

Timer/Counter External RC External Clock Crystal Low-frequency Calibrated RC

Oscillator Oscillator Oscillator Crystal Oscillator Oscillator

CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.

I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clkI/O is halted, enabling TWI address reception in all sleep modes.

Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.

Asynchronous Timer The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
Clock – clkASY from an external 32 kHz clock crystal. The dedicated clock domain allows using this
Timer/Counter as a real-time counter even when the device is in sleep mode.

24
2466T–AVR–07/10
 ATmega16(L)

ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.

Table 2. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0
External Crystal/Ceramic Resonator 1111 - 1010
External Low-frequency Crystal 1001
External RC Oscillator 1000 - 0101
Calibrated Internal RC Oscillator 0100 - 0001
External Clock 0000
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from Reset, there is as an additional delay allowing the power to reach a stable level before
commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of
the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table
3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega16 Typ-
ical Characteristics” on page 299.

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)

Default Clock The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is
Source therefore the 1 MHz Internal RC Oscillator with longest startup time. This default setting ensures
that all users can make their desired clock source setting using an In-System or Parallel
Programmer.

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-
figured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a
ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator
amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-
to-rail swing on the output. This mode is suitable when operating in a very noisy environment or
when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency
range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces
power consumption considerably. This mode has a limited frequency range and it can not be
used to drive other clock buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with
CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The
optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray
capacitance, and the electromagnetic noise of the environment. Some initial guidelines for

25
2466T–AVR–07/10
 ATmega16(L)

choosing capacitors for use with crystals are given in Table 4. For ceramic resonators, the
capacitor values given by the manufacturer should be used.

Figure 12. Crystal Oscillator Connections

C2
XTAL2

C1
XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4.

Table 4. Crystal Oscillator Operating Modes

Frequency Range Recommended Range for Capacitors
CKOPT CKSEL3..1 (MHz) C1 and C2 for Use with Crystals (pF)
1 101(1) 0.4 - 0.9 –
1 110 0.9 - 3.0 12 - 22
1 111 3.0 - 8.0 12 - 22
0 101, 110, 111 1.0 ≤ 12 - 22
Note: 1. This option should not be used with crystals, only with ceramic resonators.

26
2466T–AVR–07/10
 ATmega16(L)

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
5.

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from Additional Delay
Power-down and from Reset
CKSEL0 SUT1..0 Power-save (VCC = 5.0V) Recommended Usage
Ceramic resonator, fast
0 00 258 CK(1) 4.1 ms
rising power
Ceramic resonator, slowly
0 01 258 CK(1) 65 ms
rising power
Ceramic resonator, BOD
0 10 1K CK(2) –
enabled
Ceramic resonator, fast
0 11 1K CK(2) 4.1 ms
rising power
Ceramic resonator, slowly
1 00 1K CK(2) 65 ms
rising power
Crystal Oscillator, BOD
1 01 16K CK –
enabled
Crystal Oscillator, fast
1 10 16K CK 4.1 ms
rising power
Crystal Oscillator, slowly
1 11 16K CK 65 ms
rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.

27
2466T–AVR–07/10
 ATmega16(L)

Low-frequency To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal
Crystal Oscillator Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be con-
nected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal
capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The inter-
nal capacitors have a nominal value of 36 pF.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 6.

Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time from Additional Delay
Power-down and from Reset
SUT1..0 Power-save (VCC = 5.0V) Recommended Usage
00 1K CK(1) 4.1 ms Fast rising power or BOD enabled
(1)
01 1K CK 65 ms Slowly rising power
10 32K CK 65 ms Stable frequency at start-up
11 Reserved
Note: 1. These options should only be used if frequency stability at start-up is not important for the
application.

External RC For timing insensitive applications, the external RC configuration shown in Figure 13 can be
Oscillator used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22
pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between
XTAL1 and GND, thereby removing the need for an external capacitor. For more information on
Oscillator operation and details on how to choose R and C, refer to the External RC Oscillator
application note.

Figure 13. External RC Configuration

VCC

R NC XTAL2

XTAL1
C
GND

The Oscillator can operate in four different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7.

Table 7. External RC Oscillator Operating Modes

CKSEL3..0 Frequency Range (MHz)
0101 0.1 ≤ 0.9
0110 0.9 - 3.0
0111 3.0 - 8.0
1000 8.0 - 12.0

28
2466T–AVR–07/10
 ATmega16(L)

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 8.

Table 8. Start-up Times for the External RC Oscillator Clock Selection

Start-up Time from Additional Delay
Power-down and from Reset
SUT1..0 Power-save (VCC = 5.0V) Recommended Usage
00 18 CK – BOD enabled
01 18 CK 4.1 ms Fast rising power
10 18 CK 65 ms Slowly rising power
11 6 CK(1) 4.1 ms Fast rising power or BOD enabled
Note: 1. This option should not be used when operating close to the maximum frequency of the device.

Calibrated Internal The Calibrated Internal RC Oscillator provides a fixed 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz
RC Oscillator clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the
system-clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will operate
with no external components. The CKOPT Fuse should always be unpro-grammed when using
this clock option. During Reset, hardware loads the calibration byte into the OSCCAL Register
and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0 MHz, 2.0 MHz, 4.0
MHz or 8.0 MHz Oscillator frequency selected, this calibration gives a frequency within ±3% of
the nominal frequency. Using calibration methods as described in application notes available at
www.atmel.com/avr it is possible to achieve ±1% accuracy at any given VCC and Temperature.
When this Oscillator is used as the Chip Clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the reset time-out. For more information on the pre-programmed cali-
bration value, see the section “Calibration Byte” on page 261.

Table 9. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency (MHz)
(1)
0001 1.0
0010 2.0
0011 4.0
0100 8.0
Note: 1. The device is shipped with this option selected.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 10. XTAL1 and XTAL2 should be left unconnected (NC).

Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Time from Additional Delay
Power-down and from Reset
SUT1..0 Power-save (VCC = 5.0V) Recommended Usage
00 6 CK – BOD enabled
01 6 CK 4.1 ms Fast rising power
(1)
10 6 CK 65 ms Slowly rising power
11 Reserved
Note: 1. The device is shipped with this option selected.

29
2466T–AVR–07/10
 ATmega16(L)

Oscillator Calibration
Register – OSCCAL Bit 7 6 5 4 3 2 1 0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove process vari-
ations from the Oscillator frequency. This is done automatically during Chip Reset. When
OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis-
ter will increase the frequency of the Internal Oscillator. Writing $FF to the register gives the
highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash
access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal fre-
quency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for
calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz. Tuning to other values is not guaranteed,
as indicated in Table 11.

Table 11. Internal RC Oscillator Frequency Range.

Min Frequency in Percentage of Max Frequency in Percentage of
OSCCAL Value Nominal Frequency (%) Nominal Frequency (%)
$00 50 100
$7F 75 150
$FF 100 200

30
2466T–AVR–07/10