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Decoder 11

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KRISHNA RAJU DANANNA
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19 views

Decoder 11

Uploaded by

KRISHNA RAJU DANANNA
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Date:

Experiment - 10

3 to 8 DECODER

AIM:

To design, simulate and synthesize 3*8 decoder. Develop a testbench for functional
verification of the design.

TOOLS USED:

1. Cadence tool
2. Incisive Simulator
3. Genus Synthesizer

THEORY:

A 3*8 decoder is a digital combinational circuit that takes 3 input signals and decodes them
into 8 unique output signals. Essentially, it converts binary-coded inputs into one of the
eight outputs, each of which corresponds to a unique binary combination of the inputs. The
circuit has 3 input lines and 8 output lines, which is why it is referred to as a "3-to-8"
decoder.

Functionality In a 3x8 decoder:

The 3 input lines are often denoted as, and, where is the most significant bit (MSB) and is
the least significant bit (LSB). The 8 output lines are labelled through.For each unique
combination of inputs, only one of the eight outputs is activated (logic ‘1’ or high), while
the others remain deactivated (logic ‘0’ or low).

Reg No:238W5A0411
SIMULATION RESULT:

SCHEMATIC DIAGRAM:

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PROCEDURE:

Simulation and synthesis:

1. Create a new folder and name it.


2. Open the folder and select the option open in terminal
3. Give the following commands
a) csh >enter
b) source /home/install/cshrc >enter
c) gedit rca.v>enter
d) gedit rcatb.v>enter
e) nclaunch -new>enter
4. Choose multiple step in the nc launch window
5. Click create serials.library files
6. Click on save
7. Select don’t include any libraries and click on ok and again click on ok
8. Select module and testbench in nc launch window and click on launch
verilog compiler(2nd tool).
9. Click on plus symbol beside work library
10. Select each module seperately and click on launch elaborator (3rd tool).
11. Click on + symbol besides the snapshots and select the testbench module and
then clickon launch simulator (4th tool).
12. Select testbench module.
13. On the righthand page all the signals in the module will appear select all
those signalsand send them to waveform window by clicking on waveform
window.
14. click on run button, waveform will be generated. Where we get the simulated
graph values.
15. To do synthesis rca.sdc and genus.tcl files should be present in the folder created
in thefirst step.
16. In genus.tcl replace current module with desired module name.
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AREA REPORT:

POWER REPORT:

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17. In the .sdc file make sure no of inputs and no of outputs and their name are same as
that of the module that you like to synthesis.
18. Give the command genus and enter.
19. Give the command source genus.tcl.
20. Obtain schematic diagram, netlist, area report, power and time report.

PROGRAM:
module decod(w,y,e);

input [2:0]w;

output [7:0]y;

input e;

reg [7:0]y;

always@(w,e)

begin

if(e==1’b1)

case(w)

3’b000: y=8’b00000001;

3’b001: y=8’b00000010;

3’b010: y=8’b00000100;

3’b011: y=8’b00001000;

3’b100: y=8’b00010000;

3’b101: y=8’b00100000;

3’b110:y=8’b01000000;

3’b111:y=8’b10000000;

endcase

else

y=8’b00000000;

end

endmodule

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TIMING REPORT:

NETLIST:

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TEST BENCH:

module tb_decod;

reg [2:0] w;

reg e;

reg [7:0] y;

wire [7:0] y;

decod uut (.w(w),.y(y),.e(e));

initial begin

w=0; e=0; #100;

w=3’b000; e=1; #100;

w=3’b001; e=1; #100;

w=3’b010; e=1; #100;

w=3’b011; e=1; #100;

w=3’b100; e=1; #100;

w=3’b101; e=1; #100;

w=3’b110; e=1; #100;

w=3’b111; e=1; #100;

end

endmodule

RESULT:

The 3*8 decoder is designed using Verilog HDL. Simulation and synthesis
performed using cadence tool. Functional verification of the design is performed using a
verilog HDL testbench.

Reg No:238W5A0411

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