Name: Kainat Bano

Degree: 43

Department: Electrical

Syndicate: B

Subject: Digital System Design

Assignment no: 01

Submitted to: Asst Professor Dr Usman Ali

Question#01:

Show block diagrams and compare architectures of the following

 Microcontroller
 Microprocessor
 DSP
 SoC (System on chip

 MICROCONTROLLER(8051):
 MICROPROCESSOR(8085):

 DSP:
  SoC (system on chip):

 Comparison :

Feature 8051 8085 DSP (6713) SoC(TI OMAP5432

Microcontroller Microprocessor

Compact CPU-focused, VLIW Dual-core ARM

Architecture single-chip with relies on architecture, 8 Cortex-A15, each
CPU, memory, external instructions per core running up
timers, and I/O components cycle, 225 MHz to 1.5 GHz, with
integrated. like memory clock, supports ARMv7-A
and I/O. 32-bit fixed- architecture,
point and 64-bit supporting
floating-point. symmetric
multiprocessing
(SMP) for high
performance.
Memory 4KB ROM, 128B External 256 KB on-chip Supports up to 8
RAM (on-chip) memory SRAM, 4MB on GB of
required (no DSP6713 DSK, DDR3/LPDDR2
internal 16/32-bit EMIF, RAM, with internal
RAM/ROM). 4KB L1 L1 (32KB
(program/data), instruction, 32KB
64KB L2 data per core)
(cache/SRAM). and L2 (2MB
shared) caches.
I/O Ports 4 I/O ports (P0- External I/O 2 McBSP serial Features USB 2.0,
P3) directly devices ports, 32-bit USB 3.0, HDMI,
interfaced for connected HPI, 32-bit SDIO, and
external via buses. EMIF, GPIO pins multiple UART,
communication. for external SPI, I²C, and GPIO
interfaces. interfaces for
versatile
connectivity.
Interrupt Interrupt Supports 16-level Advanced
System Control block multiple interrupt interrupt
for handling interrupts controller, controller (GIC)
external (5.5, 6.5, supports with hardware
interrupts. etc.) internal and support for
controlled by external prioritized
the interrupt interrupts with interrupt handling
system. fast context across multiple
switching. cores.
Timers/ Timer 0 and No internal Two 32-bit includes multiple
Counters Timer 1 for timers, general- general-purpose
timing and external purpose timers, timers, a
counting hardware watchdog timer watchdog timer,
operations. required. for system and a real-time
monitoring. clock (RTC) for
time-based
operations.
Control System Internal Bus Timing and JTAG interface On-chip
Control and Control for debugging, debugging
CPU for Circuit for supported by through JTAG,
managing coordinating Code Composer with TI’s Code
operations. CPU, I/O, and Studio (CCS) for Composer Studio
memory. development. (CCS) support for
software
development and
real-time
debugging.
Buses Internal bus 8-bit internal 32/64-bit data High-performance
connects CPU, data bus, 16- bus, 32-bit internal bus
memory, and bit address address bus for architecture with
bus for memory and AXI and AHB
I/O
external peripheral buses for efficient
peripherals. memory and interfacing. data transfer
I/O. across cores and
peripherals.
Power Low (suitable Higher due to 1.2V core, 3.3V Supports dynamic
Consumption for embedded reliance on I/O, power- voltage and
 systems). external saving modes frequency scaling
components. available. (DVFS), with low-
power modes for
energy efficiency,
operating at 1.1V
for core.
Serial Built-in Serial Requires McBSP supports Includes UART,
Communicatio Port for external I²S, SPI, TDM, SPI, I²C, and USB
n communication serial I/O with UART for 3.0 for fast serial
(TXD/RXD). circuits. serial communication,
communication. with support for
multiple high-
speed
peripherals.
Specialized Built-in General- Enhanced DMA, Integrated
Functionality peripherals for purpose floating-point Imagination
specific control processing, unit, optimized Technologies
applications flexible but DSP libraries for PowerVR SGX544
(timers, ports). external signal GPU for graphics
dependencie processing processing, and a
s for tasks. DSP for real-time
peripherals. audio and video
processing.
Computational 12 MHz clock 3 MHz clock VLIW Dual ARM Cortex-
Power with 1 speed, with architecture A15 cores, each
instruction per most with up to 8 up to 1.5 GHz,
12 clock cycles. instructions instructions per capable of
Provides around taking 3 to 5 cycle at 225 approximately
1 MIPS (Million cycles. MHz. Capable 20,000 DMIPS
Instructions Per Capable of of around 1.8 (Dhrystone MIPS).
Second), approximatel GFLOPS (Giga Supports SIMD
suitable for low- y 0.64 MIPS Floating Point (Single
power Operations per Instruction,
embedded Second) in Multiple Data) for
control tasks. single high-performance
precision. multimedia tasks.

Q2
•Write Verilog code for 8 to 3 line simple encoder and priority
encoder
•Show both circuits synthesized by Intel Quartus/Xilinx ISE
•Compare and discuss the results

8 to 3 line Simple Encoder :

module encoder_8to3_mod (
input [7:0] data_in,
output reg [2:0] encoded_out
);
always @(*) begin
case (data_in)
8'b00000001: encoded_out = 3'b000;
8'b00000010: encoded_out = 3'b001;
8'b00000100: encoded_out = 3'b010;
8'b00001000: encoded_out = 3'b011;
8'b00010000: encoded_out = 3'b100;
8'b00100000: encoded_out = 3'b101;
8'b01000000: encoded_out = 3'b110;
8'b10000000: encoded_out = 3'b111;
default: encoded_out = 3'bxxx; // Undefined input
endcase
end
endmodule

TEST BENCH :
module tb_encoder_8to3_mod;
// Inputs
reg [7:0] test_in;
// Outputs
wire [2:0] test_out;

// Instantiate the Unit Under Test (UUT)

encoder_8to3_mod uut (
.data_in(test_in),
.encoded_out(test_out)
);

initial begin
// Initialize input
test_in = 8'b00000000;
 // Apply test vectors
#10 test_in = 8'b00000001; // Expected output: 000
#10 test_in = 8'b00000010; // Expected output: 001
#10 test_in = 8'b00000100; // Expected output: 010
#10 test_in = 8'b00001000; // Expected output: 011
#10 test_in = 8'b00010000; // Expected output: 100
#10 test_in = 8'b00100000; // Expected output: 101
#10 test_in = 8'b01000000; // Expected output: 110
#10 test_in = 8'b10000000; // Expected output: 111

// Test invalid input case

#10 test_in = 8'b00001111; // Expected output: xxx (Invalid input)

#10 $finish; // End simulation

end

initial begin
$monitor("Time = %d, Input = %b, Output = %b", $time, test_in,
test_out);
end
endmodule

OUTPUT:

priority encoder :
CODE:
module prio_encoder_8to3 (
input [7:0] data_in,
output reg [2:0] encoded_out
);
always @(*) begin
if (data_in[7]) encoded_out = 3'b111;
else if (data_in[6]) encoded_out = 3'b110;
else if (data_in[5]) encoded_out = 3'b101;
else if (data_in[4]) encoded_out = 3'b100;
else if (data_in[3]) encoded_out = 3'b011;
else if (data_in[2]) encoded_out = 3'b010;
else if (data_in[1]) encoded_out = 3'b001;
else if (data_in[0]) encoded_out = 3'b000;
else encoded_out = 3'bxxx; // Undefined case
end
endmodule
TEST BENCH :
module tb_prio_encoder_8to3;
// Test Inputs
reg [7:0] test_data_in;
// Test Outputs
wire [2:0] test_encoded_out;

// Instantiate the Priority Encoder Module

prio_encoder_8to3 uut (
.data_in(test_data_in),
.encoded_out(test_encoded_out)
);

initial begin
// Initialize test data
test_data_in = 8'b00000000;

// Test vector application

#10 test_data_in = 8'b00000001; // Expected output: 000
#10 test_data_in = 8'b00000010; // Expected output: 001
#10 test_data_in = 8'b00000100; // Expected output: 010
#10 test_data_in = 8'b00001000; // Expected output: 011
#10 test_data_in = 8'b00010000; // Expected output: 100
#10 test_data_in = 8'b00100000; // Expected output: 101
 #10 test_data_in = 8'b01000000; // Expected output: 110
#10 test_data_in = 8'b10000000; // Expected output: 111

// Testing with multiple bits high

#10 test_data_in = 8'b00001111; // Expected output: 011 (Highest
priority to data_in[3])
#10 test_data_in = 8'b11000000; // Expected output: 111 (Highest
priority to data_in[7])

// Test with no bits set high

#10 test_data_in = 8'b00000000; // Expected output: xxx (Undefined
input)

#10 $finish; // End the simulation

end

initial begin
$monitor("Time = %d, Input = %b, Output = %b", $time,
test_data_in, test_encoded_out);
end
endmodule
OUTPUT:

A Concise Comparison Between a Simple 8-to-3 Encoder and an 8-to-

3 Priority Encoder:
1) Code Differences:

 Simple Encoder:

o The output is based on which single input bit is active.

o Only one input can be active at any given time.

o If two or more input bits are high simultaneously, the output

becomes undefined (3'bxxx).

o Example: When in = 8'b00010000, the output is 3'b100.

 Priority Encoder:

o The output corresponds to the highest-order active bit, following

a priority from the most significant to the least significant bit.

o If multiple input bits are high, the encoder outputs the index of
the highest-priority bit.

o Example: When in = 8'b00001111, the output is 3'b011 because

in[3] has the highest priority.

2) Output Differences and Internal Architecture:

 Simple Encoder Output:

o Each input is mapped directly to a unique output.

o If multiple inputs are active, the output becomes undefined (e.g.,

xxx).

o Example: For in = 8'b00001111, the output would be undefined

(xxx).

 Priority Encoder Output:

o The encoder always outputs the position of the highest-priority

bit that is set, even when multiple bits are active.

o This ensures the output is always valid and deterministic.

o Example: For in = 8'b00001111, the output is 011 because in[3]

is the highest-priority active bit.

3) Functional Behavior:

 Simple Encoder:
 o It operates under a strict one-to-one input-output mapping. It
does not handle cases where more than one input bit is active.

 Priority Encoder:

o It can manage multiple active inputs by giving precedence to the

highest-priority bit. The output is always predictable, showing the
position of the highest active bit.

Summary:

 The simple encoder is designed for systems where it is guaranteed

that only one input will be active at a time. It has a simpler architecture
and provides faster performance in such cases.

 The priority encoder is suitable for situations where multiple inputs

might be active simultaneously, and prioritization is necessary. It is
commonly used in systems like interrupt controllers or resource
allocation mechanisms.