Microprocessors

and Microcontrollers
Ali Parsayan
[email protected]
1
 Chapter 1

Z80
Microprocessor
2
 Outline

1.1 Z80 Pins Assignment and Description

1.2 Z80 Structure
1.3 Z80 Programming Model
1.4 Register Set
1.5 CPU Timing
1.6 Interrupts
1.7 Configuration of a Z80 Microcomputer
1.8 Z80 Input Output
1.9 Z80 Instructions Description
3
 Z80 Microprocessor
Company 4 bit 8 bit 16 bit 32 bit 64 bit

8008 8088/6
4004 80386 80860
intel 8080 80186
4040 80486 pentium
8085 80286
Z8000
zilog Z80 Z8001
Z8002
6800 68006 68020
Motorola 6802 68008 68030
6809 68010 68040
 Z80 Pins Assignment
27 30
M1 - A0
31
A1
19 32
MREQ - A2
20 33
System IORQ -
21 34
A3
Control Lines RD - A4
22 35
WR - A5
36
A6
28 37
RFSH - A7
38
A8 Address Bus
18 39
HALT - A9
40
A10
WAIT -
24
Z - 80 CPU 1
2
A11
CPU 16 3
A12
Control Lines INT - A13
17 4
NMI - A14
5
A15
26
RESET -
14
D0
25 15
Bus BUSRQ - D1
23 12
Control Lines BUSAK - D2
8
D3
7
D4 Data Bus
6 9
 D5
11 10
+ 5V D6
29 13
GND D7
5
Z80 Pins Assignment

6
Z80 Microprocessor
• An Osborne Executive
portable computer, from 1982,
with:
o a Zilog Z80 4 MHz CPU,
o and a 2007 Apple iPhone
with a 412 MHz ARM11
CPU;
• The Executive has 100 times
the weight, almost 500 times
the volume, approximately 10
times the inflation adjusted
cost, and 1/1000 frequency of
the smartphone.
 Z80 Pin Description
• A15-A0:
o Address bus (output, active high, 3-state).
o Used for accessing the memory and I/O ports.
• D7-D0:
o Data Bus (input/output, active high, 3-state).
o Used for data exchanges with memory, I/O and
interrupts.
• RD:
o Read (output, active Low, 3-state).
o Indicates that the CPU wants to read data from
memory or I/O.
• WR:
o Write (output, active Low, 3-state).
o Indicates that the CPU data bus holds valid
data to be stored at the addressed memory or
I/O location. 8
 Z80 Pin Description
• MREQ:
o Memory Request (output, active Low, 3-state).
o Indicates memory read/write operation.
• IORQ:
o Input/Output Request (output, active Low,3-
state).
o Indicates I/O read/write operation.
• M1:
o Machine Cycle One (output, active Low).
o Together with MREQ indicates opcode fetch
cycle, and together with IORQ indicates an
Interrupt Ack cycle.
• RFSH:
o Refresh (output, active Low).
o Together with MREQ indicates refresh cycle and
Lower 7-bits address is refresh address to DRAM. 9
 Z80 Pin Description

• INT:
o Interrupt Request (input, active Low).
o It is generated by I/O devices.
o Checked at the end of the current
instruction if IFF flag is enabled.
• NMI:
o Non-Maskable Interrupt (Input, negative
edge-triggered).
o Higher priority than INT and Recognized
at the end of the current instruction.
o Independent of the status of IFF.
o Forces the CPU to restart at location
0066H. 10
 Z80 Pin Description
• BUSREQ:
o Bus Request (input, active Low).
o Higher priority than NMI.
o Recognized at the end of the current machine
cycle.
o Forces the CPU address bus, data bus, and
MREQ, IORQ, RD, and WR to high-imp.
• BUSACK:
o Bus Acknowledge (output, active Low).
o Indicates to the requesting device that address,
data, and control signals MREQ, IORQ, RD,
and WR have entered their high-impedance
states.

11
 Z80 Pin Description

• RESET:
o Reset (input, active Low).
o RESET initializes the CPU as follows:
➢ Resets the IFF
➢ Clears the PC and registers I and R.
➢ Sets the interrupt status to Mode 0.
➢ During reset time, the address and
data bus go to a high-impedance state
➢ And all control output signals go to the
inactive state.
➢ Must be active for a minimum of three
full clock cycles before the reset
operation is complete.
12
 Z80 Structure B
8 U
INTERNAL DATA BUS (8 BIT) F
F
E
R
DATA BUS
MUX MUX
A F
INSTRUCTION W'
TMP
Z' W Z
REGISTER
I R A' F'
B' C' B C
D' E' D E
H' L' H L ACT
DECODER
IX
IY
SP
ALU
CONTROLLER
SEQUENCER
PC

±k ±k
CONTROL
SECTION B ADDRESS BUS
16 U
INTERNAL ADDRESS BUS (16 BIT)
F
F
E
R

B CONTROL BUS
13 U
INTERNAL CONTROL BUS F
F
E
R 13
Z80 Programming Model

14
 Register Set
• A: Accumulator Register
• F: Flag register
• Two sets of six general-purpose registers
o may be used individually as 8-bit A, F, B, C, D, E, H, and L (A’,
F’, B’, C’, D’, E’, H’, and L’)
o or in pairs as 16-bit registers AF, BC, DE, and HL (AF’, BC’,
DE’, and HL’)
• The Alternative registers (A’, F’, B’, C’, D’, E’, H’, and
L’) not visible to the programmer but can access via:
o EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL’)
o EX AF, AF ’ (AF)<->(AF’)
o What is this instruction useful for? 15
 Register Set

• 4 16-bit registers hold memory address (pointers)

o Index registers (IX) and (IY) are 16-bit memory pointers
o 16 bit stack pointer (SP)
o Program counter (PC)
• Program counter (PC)
o PC points to the next opcode to be fetched from ROM
o When the µP places an address on the address bus to fetch the byte from
memory, it then increments the program counter by one to the next location
• Special purpose registers
o I : Interrupt vector register.
o R : memory Refresh register
16
 Flag Register
7 6 5 4 3 2 1 0

P
S Z X H X V N C
• S: Sign Flag (1: Negativ)
• Z: Zero Flag (1: Zero)
• H: Half Carry Flag (1: Carry from Bit 3 to Bit 4)**
• P: Parity Flag (1: Even)
• V: Overflow Flag (1: Overflow)
o 2-complement number representation
• N: Operation Flag (1: Previous Operation was subtraction)
o used in DAA-operation for BCD-arithmetic
• C: Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of
operand)
 DAA - Decimal Adjust Accumulator
• Adjusts the content of the Accumulator A for BCD addition and subtraction
operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
before DAA after DAA
Op N C Bits 4-7 H Bits 0-3 A=A+.. C
0 0 0-9 0 0-9 00 0
0 0 0-8 0 A-F 06 0
0 0 0-9 1 0-3 06 0
0 0 A-F 0 0-9 60 1
ADD
0 0 9-F 0 A-F 66 1
ADC
0 0 A-F 1 0-3 66 1
0 1 0-2 0 0-9 60 1
0 1 0-2 0 A-F 66 1
0 1 0-3 1 0-3 66 1
1 0 0-9 0 0-9 00 0
SUB
1 0 0-8 1 6-F FA 0
SBC
1 1 7-F 0 0-9 A0 1
NEG 1 1 6-F 1 6-F 9A 1
 Instruction Cycles,
Machine Cycles and “T-states”
• T-state = 1/f (f: Z80 Clock Frequency)
o f = 4 MHZ → T-state = 0.25 us
• Machine cycle is defined as the time required to
complete one operation of accessing memory,
accessing IO, etc.
• Instruction cycle is the time taken to complete the
execution of an instruction

19
Basic CPU Timing Example

20
Opcode Fetch Bus Timings (M1 Cycle)

21
 M1 Refresh Cycle

• Takes 4T to 6Ts
• Z80 includes built in circuitry for refreshing
DRAM
• This simplifies the external interfacing hardware
• DRAM consists of MOS transistors, which store
Information as capacitive charges; each cell
needs to be periodically refreshed
• During T3 and T4 (when Z80 is performing
internal ops), the low order address is used to
supply a 7-bit address for refresh 22
 The R register

• Is increased at every first machine cycle (M1).

• Bit 7 of it is never changed by this.
• Only the lower 7 bits are included in the addition.
• So bit 7 stays the same.
• Bit 7 can be changed using the LD R, A instruction.
• LD A, R and LD R, A access the R register after it is
increased
• R is often used in programs for a random value, which is
good but of course not truly random.
• The block instructions decrease the PC with two, so the
instructions are re-executed. 23
 Wait Signal

• The Z80 samples the wait signal during T2

if low then Z80 adds wait.
• States to extend the machine cycle.
• Used to interface memories with slow
response time.
• Slow memory is low cost.

24
Adding One Wait State to an M1 Cycle

25
Adding One Wait State
to Any Memory Cycle

26
Memory Read/Write Cycle

27
 IO Read/Write Cycle

• During I/O operations a single wait state is automatically inserted

28
Bus Request/Acknowledge Cycle

29
 Interrupts

• There are two types of interrupts:

o Non Mask-able (NMI)
➢Could not be masked
➢Jump to 0066H of memory
o Mask-able (INT)
➢Has 3 mode
➢Can be set with the IM x Instruction
✓ IM 0 sets Interrupt mode 0
✓ IM 1 sets Interrupt mode 1
✓ IM 2 sets Interrupt mode 2
30
 Interrupt Modes

• Mode 0:
o An 8 bit opcode is Fetched from Data BUS and executed
o The source interrupt device must put 8 bit opcode at data bus
o 8 bit opcode usually is RST p instructions

• Mode 1:
o A jump is made to address 0038h
o No value is required at data bus

• Mode 2:
o A jump is made to address (register I × 256 + value from interrupting device that
puts at bus)
o I is high 8 bit of interrupt vector
o Value is low 8 bit of interrupt vector
31
Interrupt Modes

32
 Interrupt Request/Acknowledge Cycle

• Two wait states are automatically added to this cycle 33

 Non-Maskable
Interrupt Request Operation

34
 Minimal Configuration of a
Z80 Microcomputer
Clock Memory Power
Generator (ROM, RAM) Supply

Address Bus
Input Out
Z - 80 CPU Data Bus Output
In
Control Bus (I/O)
35
 Z80 Memory Connection

• CPU 16 bit address bus ➔ 64 KB memory (max)

• CPU 8 bit data bus ➔ 8 bit data width
• Generally should be connected
o Data to Data
o Address to Address
o wr to wr
o rd to rd
o Mreq to cs
36
 Z80 Memory Connection

• If only one RAM chip Full size (64 kb capacity)

D7~D0 D7~D0
RAM
64 kb

A15~A0 A15~A0

Z80 RD WR CS

RD
WR

MREQ
 Z80 Memory Connection

• If RAM capacity was D7~D0 D7~D0

32 kb RAM
32 kb
• A15 composed with A14~A0 A14~A0
MREQ
Z80 RD WR CS
• RAM area is from
0000h to 7FFFh RD
WR

A15 MREQ
 Z80 Memory Connection

• There is two 32 kb RAM

• Problem :
o Bus Conflict.
o The two memory chips will provide data at the same
time when microprocessor performs a memory read.
• Solution:
o Use address line A15 as an “arbiter”.
o If A15 outputs a logic “1” the upper memory is
enabled (and the lower memory is disabled) and vice-
versa.
39
 Z80 Memory Connection

• There is two 32 kb RAM

D7~ D7~ D7~
• A15 applied to select one D0 D0 RAM D0 RAM
32 kb 32 kb
RAM chip A14~ A14~ A14~
• Two RAM area is from A0
Z80
A0 WR CS
RD
A0 WR CS
RD

0000h to 7FFFh (RAM1)

RD
and 8000h to FFFFh WR

(RAM1) A15 MREQ

 Z80 Memory Connection

• 32 kb ROM and 32 kb RAM

• ROM doesn’t have wr signal

D7~D0 D7~D0 D7~D0

ROM RAM
32 kb 32 kb
A14~A0 A14~A0 A14~A0

Z80 OE CS RD WR CS

RD
WR

A15 MREQ
 Z80 Memory Connection

• If there is 4 memory chip, A14 and A15 applied to chip selection

D7~D0 D7~D0 D7~D0 D7~D0 D7~D0

ROM RAM RAM RAM

16 kb 16 kb 16 kb 16 kb
A13~A0 A13~A0 A13~A0 A13~A0 A13~A0

Z80 OE CS RD WR CS RD WR CS RD WR CS

RD
WR

En
A14
A15

MREQ
S0
S1
 Address Bit Map
Selects chip Selects location within chips

A15 to A0 AA AA AAAA AAAA AAAA

Memory
(HEX) 11 11 1198 7654 3210
Chip
54 32 10
0000h 00 00 0000 0000 0000
ROM
3FFFh 00 11 1111 1111 1111
4000h 01 00 0000 0000 0000
RAM1
7FFFh 01 11 1111 1111 1111
8000h 10 00 0000 0000 0000
RAM2
BFFFh 10 11 1111 1111 1111
C000h 11 00 0000 0000 0000
RAM3
FFFFh 11 11 1111 1111 1111 43
 Memory Map
0000h
• Represents the memory type ROM
16k
• Address area of each memory chip 3FFFh
4000h
• Empty area RAM1
16k
7FFFh
D7~D0 D7~D0 D7~D0 D7~D0 D7~D0
8000h
RAM2
ROM RAM RAM RAM
16 kb 16 kb 16 kb 16 kb
A13~A0 A13~A0 A13~A0 A13~A0 A13~A0

Z80 16k
OE CS RD WR CS RD WR CS RD WR CS
BFFFh
RD
C000h
RAM3
WR

En
A14
A15

MREQ
S0
16k
S1
FFFFh
 Memory Map
0000h
• Empty Area can't write and read ROM
• rd op. returns FFh value (usually) 3FFFh
4000h
• wr op. can't store any value on it Empty

7FFFh
D7~D0 D7~D0 D7~D0 D7~D0
8000h
RAM2
ROM RAM RAM
16 kb 16 kb 16 kb
A13~A0 A13~A0 A13~A0 A13~A0

Z80 OE CS RD WR CS RD WR CS
BFFFh
RD
WR
C000h
En RAM3
A14
A15

MREQ
S0
S1
FFFFh
 Memory Map
0000h
• Empty Area can't write and read ROM
• rd op. returns FFh value (usually) 3FFFh
4000h
• wr op. can't store any value on it Empty

7FFFh
D7~D0 D7~D0 D7~D0
8000h
ROM

RAM
RAM
16 kb 16 kb
A13~A0 A13~A0 A13~A0

Z80 OE CS RD WR CS
BFFFh
RD
WR
C000h
En Empty
A14
A15

MREQ
S0
S1
FFFFh
 Full and Partial Decoding

• Full (exhaust) Decoding

o All of the address lines are connected to any memory/device to
perform selection
o Absolute address: any memory location has one address

• Partial Decoding
o When some of the address lines are connected the
memory/device to perform selection
o Using this type of decoding results into roll-over addresses
(fold back or shading).
o Roll-over address: any memory location has more than one
address 47
 Partial Decoding

• A15~A12 has no connection

• Then doesn’t play any role in addressing
• What is the Memory and Address Bit map?
D7~D0 D7~D0
RAM
4 kb
A11~A0 A11~A0

A15~A12 X RD WR CS

Z80
RD
CPU WR

MREQ 48
 Partial Decoding 0000h
RAM
0FFFh
1000h
RAM’
1FFFh
o Every memory location has more than one address
2000h
o For example first RAM location has addresses: RAM’
2FFFh

o 0000h 3000h
RAM’
3FFFh
o 1000h
o 2000h Roll-over Address
o 3000h F000h
RAM’
o …………….
FFFFh
o …………….

o F000h D7~D0 D7~D0

RAM
AAAA AAAA AAAA AAAA 4 kb
A15 to A0 Memory A11~A0 A11~A0
1111 1198 7654 3210
(HEX) Chip A15~A12 X RD WR CS
5432 10

X000h xxxx 0000 0000 0000 Z80 RD

RAM CPU WR

XFFFh xxxx 1111 1111 1111 MREQ

 Partial Decoding
• A12 only connected to RAM
• A13 has no connection
• What is the memory map?

D7~D0 D7~D0 D7~D0

ROM RAM
4 kb 8 kb
A12~A0 A11~A0 A12~A0

A13 X OE CS RD WR CS

Z80
RD
CPU
WR
A15
A14

MREQ

50
 Partial Decoding
• 8 roll-over address for ROM
• 4 roll-over address for RAM

D7~D0 AAAA AAAA AAAA AAAA

D7~D0 D7~D0 Memory
ROM 1111 1198 7654 3210
RAM Chip
4 kb 8 kb 5432 10
A12~A0 A11~A0 A12~A0

Z80 OE CS RD WR CS 0xxx 0000 0000 0000

A13
X
CPU ROM
0xxx 1111 1111 1111
RD
WR
X0x0 0000 0000 0000
RAM
A15
A14

MREQ
X0x1 1111 1111 1111

51
 0000h 0000h
ROM
0FFFh
RAM’
1000h
ROM’
Partial Decoding Conflict 1FFFh

2000h
1FFFh

2000h
2FFFh
ROM’
RAM’
3000h
ROM’
D7~D0 D7~D0 D7~D0 3FFFh 3FFFh
ROM
4 kb
RAM
8 kb
4000h 4000h
ROM’
4FFFh
A12~A0 A11~A0 A12~A0
5000h
ROM’
OE CS RD WR CS 5FFFh 5FFFh
Z80 A13
X
CPU 6000h 6000h
ROM’
RD 6FFFh
WR
7000h
ROM’
7FFFh 7FFFh
A15
A14

MREQ
8000h F000h

RAM
9FFFh
AAAA AAAA AAAA AAAA A000h
Memory
1111 1198 7654 3210
Chip RAM’
5432 10
BFFFh

0xxx 0000 0000 0000 4k C000h

ROM
0xxx 1111 1111 1111
DFFFh
X0x0 0000 0000 0000 8k
E000h
RAM
X0x1 1111 1111 1111 FFFFh
FFFFh
 0000h 0000h
ROM
0FFFh

1000h
ROM’
Partial Decoding 1FFFh

2000h
1FFFh

2000h
2FFFh
ROM’
3000h
ROM’
D7~D0 D7~D0 D7~D0 3FFFh 3FFFh
ROM
4 kb
RAM
8 kb
4000h 4000h
ROM’
4FFFh
A12~A0 A11~A0 A12~A0 RAM’
5000h
ROM’
Z80
CPU
A13
X
OE CS RD WR CS 5FFFh

6000h
Conflict
5FFFh

6000h
ROM’
RD 6FFFh
WR RAM’
7000h
ROM’
7FFFh 7FFFh
A15
A14

MREQ
8000h F000h

9FFFh
AAAA AAAA AAAA AAAA A000h
Memory
1111 1198 7654 3210
Chip
5432 10
BFFFh

0xxx 0000 0000 0000 4k C000h

ROM RAM
0xxx 1111 1111 1111
DFFFh
X1x0 0000 0000 0000 8k
E000h
RAM
X1x1 1111 1111 1111 RAM’
FFFFh
FFFFh
 Full (exhaustive) Decoding
AAAA AAAA AAAA AAAA
Memory
1111 1198 7654 3210
Chip
5432 10
A12~A0 A12~A0
0000 0000 0000 0000 D7~D0
ROM 2764
0001 1111 1111 1111 EPROM
0010 0000 0000 0000 8k8
RAM
0010 0111 1111 1111 OE CE

D7~D0
RD
A13 C 0000h-07FFh
Y0
A12 B Y1 0800h-0FFFh
A11 A Y2 1000h-17FFh 7421
1800h-1FFFh
A10~A0 A10~A0
74138 Y3 D7~D0
2000h-27FFh 6116
Y4 RAM
A15 G2A Y5 2k8

A14 G2B Y6 RD WR CS
MREQ G1 Y7

RD WR
 Partial Decoding
AAAA AAAA AAAA AAAA
Memory
1111 1198 7654 3210
Chip
5432 10
A12~A0 A12~A0
0000 0000 0000 0000 D7~D0
ROM 2764
0001 1111 1111 1111 EPROM
001x x000 0000 0000 8k8
RAM
001x x111 1111 1111 OE CE

D7~D0
RD
A15 C 0000h-1FFFh
Y0
A14 B Y1 2000h-3FFFh
A13 A Y2
A10~A0 A10~A0
74138 Y3 D7~D0
6116
Y4 RWM
MREQ G2A Y5 2k8

GND G2B Y6 RD WR CS
VCC G1 Y7

RD WR
 1 Bit Memory With Separated I/O

D7-D0

D7 D1 D0

Din Din Din

A11~A0 Dout A11~A0 Dout A11~A0 Dout
A11-A0 A11-A0 A11-A0
2147 2147 2147
RWM RWM RWM
4k1 4k1 4k1

WR / RD CS WR / RD CS WR / RD CS

WR / RD

CS

56
 What is The Memory (addr. bit) Map
A12~A0
D7~D0
2764
EPROM
8k8
OE CE

RD
A15 C 0000h-1FFFh
Y0
A14 B 2000h-3FFFh D7-D0
Y1 D0
D7 D1
A13 A Y2

74138 Y3 Din Din Din

A11~A0 Dout A11~A0 Dout A11~A0 Dout
Y4 A11-A0 A11-A0 A11-A0
2147 2147 2147
MREQ G2A Y5 RWM RWM RWM
4k1 4k1 4k1
GND G2B Y6 WR / RD CS WR / RD CS WR / RD CS

VCC G1 Y7

WR WR
RD
Adding RAM & ROM

58
Minimum Z80 Computer System

59
Z80-µP-Family (Typical Environment)
PIO DMA
+5V

INT - INT - IEI RDY

System Buses (Address, Data, Control)

INT - INT - INT - IEO W/RDYB -

Z80 CPU CTC SIO
+5V IEI IEO IEI TxCA - TxCB -
ZC/TO1 ZC/TO2 RxCA - RxCB -

60
 Z80 Input/Output
• Z80 at most could have 256 input port and 256 output
• 8 bit port address is placed on A7–A0 pin to select the I/O device
• OUT (n), A
o n is 8 bit port address
o Content of A is data
• OUT (C), r
o Content of C is a port address
o r is a data register
• IN A, (n)
o n is 8 bit port address
o Data is transferred to A
• IN r (C)
o Content of Reg C is a port address
o Input data is transferred to r (data reg) 61
Remember IO Read/Write Cycle

62
Z80 and Simple Output Port
A15
A14 OUT (03), A
:
A0

D7 D0 Q0
D6 D1 Q1
D5 D2 Q2
Z80 D4 D3 Q3
D3 D4 Q4
74LS373
D2 D5 Q5
D1 D6 Q6
D0 D7 Q7

LE OE
IORQ
WR

AAAAAAAA
IOWR 76543210
63
Z80 and Simple Output Port (74LS373)

64
Z80 and Simple Input Port
A15 5V
A14 IN A, (02)
:
A0
D7 Y0 A0
D6 Y1 A1
D5 Y2 A2
Z80 D4 Y3 A3
D3 Y4 74LS244 A4
D2 Y5 A5
D1 Y6 A6
D0 Y7 A7

G1 G2
IORQ
RD

AAAAAAAA
IORD 76543210

65
Z80 and Simple Input Port (74LS244)

66
 Z80 Instructions Description

• 158 different instruction types

• Including all 78 of the 8080A CPU
• Instruction groups
o Load and Exchange
o Block Transfer and Search
o Arithmetic and Logical
o Rotate and Shift
o Bit Manipulation (Set, Reset, Test)
o Jump, Call, and Return
o Input/Output
o Basic CPU Control
67
 Addressing Modes

• Immediate
• Immediate Extended
• Modified Page Zero Addressing (rst p)
• Relative Addressing
o Jump Relative (2 byte)
➢ One Byte Op Code
➢ 8-Bit Two’s Complement Displacement (A+2)
• Extended Addressing
o Absolute jump
➢ One byte opcode
➢ 2 byte address
• Indexed Addressing
o (Index Register + Displacement) (IX+d)
o 2 byte opcode
o 1 byte displacement 68
 Addressing Modes

• Register Addressing
o LD C, B
• Implied Addressing
o Op Code implies other operand(s)
o ADD E
• Register Indirect Addressing
o 16-bit CPU register pair as pointer (such as HL)
o ADD (HL)
• Bit Addressing
o Set, Reset, and test instructions.
o SET 3, A
o RES 7, B
69
 Z80 Instructions

• INST <dst> , <src>

• INST : 2, 3 or 4 characters
• Operands :
o 8 bit registers (A, B, C, …)
o 16 bit registers (AF, BC, …, A’F’, …)
o 3BH
o 45F0H
o (1000H)
70
 Z80 Instructions

• DATA Transfer Instructions

o LD r, s
o LD r, n
o LD r, (nn)
o LD r, (HL)
o LD r, (IX+n)
o LD rr, nn
• Operands:
o r and s are 8 bit registers
o n is a hex number
71
 Z80 Instructions

• Stack DATA Transferring Instructions

o PUSH rr
o POP rr
• Operands:
o rr is a 16 bit register
o First high value 8 bit register is pushed
o Then low value ……
o First low value 8 bit register is popped
o Then high value ……
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 Z80 Instructions
• Arithmetic Instructions
o ADD r, s
o ADC r, s
o SUB r, s
o SBC r, s
o NEG r
o CP r or n or (nn) or …..
o ADD r, n
o ADD r, (nn)
o ADD r, (ss)
o ADD r, (IX+n)
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 Z80 Instructions

• Logical Instructions
o AND r, s
o OR r, s
o CPL r
o XOR r, s
o AND r, n
o AND r, (nn)
o AND r, (ss)
o AND r, (IX+n)
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 Z80 Instructions

• Jump Instructions
o JP z, Address
o JP nz, Address
o JP c, Address
o JP nc, Address
o …………………
o …………………
o …………………
o JR nn, Address (jump to PC + nn)
o DJNZ Address (B=B-1 if B=0 then jump)
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 Z80 Instructions
• Shift and Rotate Instructions
o RLCA rotate all ACC bits and put MSB in LSB and Carry
o RRCA rotate all ACC bits and put LSB in MSB and Carry
o RLA rotate all ACC bits and Carry
o RLA rotate all ACC bits and Carry
o RLC
o RRC
o ………..
o SLA shift all ACC bits and put ‘0’ in LSB and put MSB in
Carry
o SRA
o ………...
o …………
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 Z80 Instructions

• Bit Set or Reset Instructions

o BIT bit Address put not of bit in one of flags as Z
o SET bit Address
o RES bit Address

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 Z80 Instructions

• I/O Instructions
o IN A, (nn)
o OUT (nn), A
o ………………
o ………………
o ………………

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Question?

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