MCR8DSM D
MCR8DSM D
Preferred Device
Sensitive Gate
Silicon Controlled Rectifiers
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance — Junction to Case RqJC 2.2 °C/W
Thermal Resistance — Junction to Ambient RqJA 88
Thermal Resistance — Junction to Ambient(1) RqJA 80
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
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2
MCR8DSM, MCR8DSN
110 12
10
105
a a 180°
a = Conduction 8.0
a = Conduction 90°
120°
100
Angle Angle dc
6.0 60°
a = 30°
95
dc 4.0
90
2.0
a = 30° 60° 90° 120° 180°
85 0
0 1.0 2.0 3.0 4.0 5.0 6.0 0 1.0 2.0 3.0 4.0 5.0 6.0
IT(AV), AVERAGE ON–STATE CURRENT (AMPS) IT(AV), AVERAGE ON–STATE CURRENT (AMPS)
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3
MCR8DSM, MCR8DSN
100 1.0
I T, INSTANTANEOUS ON–STATE CURRENT (AMPS) TYPICAL @ TJ = 25°C
10
(NORMALIZED)
0.1
MAXIMUM @ TJ = 25°C ZqJC(t) = RqJC(t)Sr(t)
1.0
0.1 0.01
0 1.0 2.0 3.0 4.0 5.0 0.1 1.0 10 100 1000 10 K
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS) t, TIME (ms)
1000 1.0
RGK = 1.0 KW
100
GATE OPEN
10
1.0 0.1
–40 –25 –10 5.0 20 35 50 65 80 95 110 –40 –25 –10 5.0 20 35 50 65 80 95 110
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Gate Trigger Current versus Figure 6. Typical Gate Trigger Voltage versus
Junction Temperature Junction Temperature
10 10
RGK = 1.0 KW RGK = 1.0 KW
IH , HOLDING CURRENT (mA)
1.0 1.0
0.1 0.1
–40 –25 –10 5.0 20 35 50 65 80 95 110 –40 –25 –10 5.0 20 35 50 65 80 95 110
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Holding Current versus Figure 8. Typical Latching Current versus
Junction Temperature Junction Temperature
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4
MCR8DSM, MCR8DSN
10 1000
TJ = 25°C
8.0
IH, HOLDING CURRENT (mA)
70°C
2.0 IGT = 10 mA
0 1.0
100 1000 10 K 100 1000
RGK, GATE–CATHODE RESISTANCE (OHMS) RGK, GATE–CATHODE RESISTANCE (OHMS)
Figure 9. Holding Current versus Figure 10. Exponential Static dv/dt versus
Gate–Cathode Resistance Gate–Cathode Resistance and Junction
Temperature
1000 1000
TJ = 110°C VD = 800 V
400 V TJ = 110°C
STATIC dv/dt (V/ ms)
100 100
600 V IGT = 25 mA
VPK = 800 V
IGT = 10 mA
10 10
1.0 1.0
100 1000 100 1000
RGK, GATE–CATHODE RESISTANCE (OHMS) RGK, GATE–CATHODE RESISTANCE (OHMS)
Figure 11. Exponential Static dv/dt versus Figure 12. Exponential Static dv/dt versus
Gate–Cathode Resistance and Peak Voltage Gate–Cathode Resistance and Gate Trigger
Current Sensitivity
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MCR8DSM, MCR8DSN
Surface mount board layout is a critical portion of the interface between the board and the package. With the
total design. The footprint for the semiconductor packages correct pad geometry, the packages will self align when
must be the correct size to insure proper solder connection subjected to a solder reflow process.
0.165 0.118
4.191 3.0
0.100
2.54
0.063
1.6
0.190 0.243
4.826 6.172
inches
mm
DPAK
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6
MCR8DSM, MCR8DSN
PACKAGE DIMENSIONS
D–PAK
CASE 369A–13
ISSUE Z
NOTES:
–T– SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
PLANE Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B C
INCHES MILLIMETERS
V R E DIM MIN MAX MIN MAX
A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
4 C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.033 0.040 0.84 1.01
S F 0.037 0.047 0.94 1.19
1 2 3 G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.175 0.215 4.45 5.46
L S 0.020 0.050 0.51 1.27
H U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
D 2 PL Z 0.138 ––– 3.51 –––
G 0.13 (0.005) M T STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
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7
MCR8DSM, MCR8DSN
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8
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