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Practice Problems 5 - Sequential Circuit Design

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42 views2 pages

Practice Problems 5 - Sequential Circuit Design

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khollahrehan12345
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© © All Rights Reserved
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Second Year – CIS

Course Teacher: Dr. Zareen Sadiq

CS-220 DIGITAL LOGIC DESIGN

PROBLEMS

Sequential Circuit Design


1. Design sequential circuit for the following state diagram. Map all unused states to don’t cares. Use:
a. D flip flops
[ans: 𝐷2 = 𝑥. ̅̅̅
𝑄2 . ̅̅̅
𝑄1 , 𝐷1 = 𝑥̅ . ̅̅̅
𝑄0 + 𝑄2 . ̅̅̅
𝑄0 + 𝑥. ̅̅̅
𝑄1 . 𝑄0 , 𝐷0 = 𝑥. 𝑄2 + 𝑥̅ . 𝑄0 + 𝑥̅ . ̅̅̅
𝑄2 . ̅̅̅
𝑄1 , 𝑦 = 𝑥. 𝑄0 + 𝑥. 𝑄1 ]
b. T flip flops
[ans: 𝑇2 = 𝑄2 + 𝑄 ̅̅̅1 . 𝑥 , 𝑇1 = 𝑄2 + 𝑥̅ . 𝑄1 . 𝑄0 + 𝑥. 𝑄1 . ̅̅̅
𝑄0 + 𝑥̅ . ̅̅̅
𝑄1 . ̅̅̅
𝑄0 , 𝑇0 = 𝑥. 𝑄0 + 𝑥. 𝑄2 + 𝑥̅ . ̅̅̅
𝑄2 . ̅̅̅
𝑄1 . ̅̅̅
𝑄0 , 𝑦 = 𝑥. 𝑄0 + 𝑥. 𝑄1 ]

0/0

001
1/1 0/0
1/0
100 0/0 011
0/0 1/1
010
1/0 0/0
1/1

000

2. Design sequential circuit for the following state diagram using SR flip flops. Map all unused states to don’t cares.
[ans: 𝑆0 = 𝑥 , 𝑅0 = 0 , 𝑆1 = ̅̅̅
𝑄1 . 𝑥 + 𝑅1 = 𝑄1 . 𝑥 , 𝑆2 = ̅̅̅
𝑄2 . 𝑄1 . 𝑥 , 𝑅2 = 𝑄2 . 𝑄1 . 𝑥 , 𝑦 = 𝑥
0/0

001
1/1 1/1

0/0 111 011 0/0

1/1 1/1
101

0/0

3. Design decade counter. Map all unused states to don’t cares. Use:
a. T flip flops
[ans: 𝑇3 = 𝑄2 . 𝑄1 . 𝑄0 + 𝑄3 . 𝑄0 , 𝑇2 = 𝑄1 . 𝑄0 , 𝑇1 = ̅̅̅
𝑄3 . 𝑄0 , 𝑇0 = 1]
b. JK flip flops
[ans: 𝐽3 = 𝑄2 . 𝑄1 . 𝑄0 , 𝐾3 = 𝑄0 , 𝐽2 = 𝐾2 = 𝑄1 . 𝑄0 , 𝐽1 = ̅̅̅
𝑄3 . 𝑄1 , 𝐾1 = 𝑄0 , 𝐽0 = 𝐾0 = 1]

4. Design decade counter using JK flip flop. Map all unused states to 0.
[ans: 𝐽3 = 𝑄2 . 𝑄1 . 𝑄0 , 𝐾3 = 𝑄2 + 𝑄1 + 𝑄0 , 𝐽2 = ̅̅̅
𝑄3 . 𝑄1 . 𝑄0 , 𝐾2 = 𝑄3 + 𝑄0 , 𝐽1 = ̅̅̅
𝑄3 . 𝑄2 . 𝑄0 , 𝐾1 = 𝑄0 + 𝑄3 (𝑄2 + 𝑄1 ),
𝐽0 = ̅̅̅
𝑄3 + ̅̅̅
𝑄2 . 𝑄1 , 𝐾0 = 1]

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5. Design odd value counter. Map all unused states to don’t cares. Use:
a. T flip flops
[ans: 𝑇2 = 𝑄1 , 𝑇1 = 1 , 𝑇0 = 0 ]
b. JK flip flops
[ans: 𝐽2 = 𝐾2 = 𝑄1 , 𝐽1 = 𝐾1 = 1 , 𝐽0 = 𝑋 , 𝐾0 = 0]

6. Design the following counter using T flip flops. Map all unused states to don’t cares.
[ans: 𝑇2 = 𝑄1 , 𝑇1 = 1 , 𝑇0 = ̅̅̅
𝑄2 , ]

001

111 010

101

7. Design the following counter using T flip flops.


[ans: 𝑇2 = 𝑄2 + 𝑄1 . 𝑄0 , 𝑇1 = 𝑄0 , 𝑇0 = ̅̅̅
𝑄2 + 𝑄0 , ]
7

4 1

5
3 2

8. Design a 3-bit up/down counter. Use any flip flop.

9. Design a 3-bit up/down even sequence counter. Use any flip flop.

10. Design a 2-bit up/down counter which produces an output 1 if the next/settled state is an even number and 0 otherwise.

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