IBC Lecture Week2
IBC Lecture Week2
Biomedical
Computing
1
Overview
• IoT Hardware
– Microcontrollers and Microprocessors
• Introduction
• Microprosessor
• Microcontroller
2
Design Challenges
• Privacy
• Interoperability
• Power Consumption
• Scalability
• Data Management
• Connectivity
• Hardware Limitations
• Regulation Compliance
• Integration Challenges
3
IOT based Healthcare Architecture
4
Overview of IoT
5
Layer Architecture
6
Communication Protocols
7
8
9
IOT Hardware
11
Cont.
12
Example
13
Applications
Here are a few examples of how microprocessors spring into action in
varying IoT devices:
• Smart Thermostat: The microprocessor reads the data taken in by
home temperature sensors, runs tasks to digest the data, and
consequently triggers a change in the state of the heating and cooling
system.
• Wearable Fitness Trackers: The microprocessor takes in the data
collected by the body trackers, computes necessary measurements
from the data, and often sends the data to the cloud.
• Smart Vacuum: The microprocessor takes proximity data from the
sensors, analyzes potential next moves, and triggers the device to
move and clean the space. 14
15
Components of Microprocessor
16
Cont.
• The microprocessor performs three main tasks for the
system:
(1) Data transfer between itself and the memory or I/O
systems.
(2) Simple operations.
(3) Program flow via simple decisions.
• The power of the microprocessor is in its capability to
execute billions of millions of instructions per second
from a program or software (group of instructions) stored
in the memory system. 17
Generations of Microprocessors
Generation Era Chip Size Word Size Maximum Clock Cores Example
Memory Speed
Size
First 1971- LSI 4/8 bit 1 KB 108-200 Single Intel 8080
1973 KHz
Second 1974-78 LSI 8 bit 1 MB Upto 2MHz Single Motorola 6800
Intel 8085
Third 1979-80 VLSI 16 bit 16 MB 4-6 MHz Single Intel 8086
Quad, Octa
18
Definitions
• Von Neuman
• Harvard
• CISC
• RISC
• Super Scalar
• VLIW
20
Architectures
1 - 21
Architectures
• Von Neuman
• Data and Program share the same bus and the
same memory, and so must have the same width.
• CPU Registers:
• Program Counter (PC), Instruction Register (IR) and
other general purpose registers, etc.
• Bottleneck: Getting instructions interferes with
accessing RAM
• Self-correcting programs
22
Architectures contd…
• Harvard
• Separate program bus and data bus (can be of
different widths!)
1 - 23
Architectures contd…
• Harvard
• Easy Instruction Pipelining
• Can’t use self modifying codes
• Allows 2 simultaneous memory Fetches
• Most DSPs use Harvard Architecture for streaming data.
• Greater memory Band-width
• More predictable Band-width
24
Architectures contd…
26
Architectures
contd…
• RISC vs CISC
27
Architectures
contd…
• Super Scalar
• Multiple CPUs in a single Processor
• Processor decides at runtime about the instructions that can be
executed parallel.
• Instructions will be executed in an order different from the strictly sequential
one with the restriction that the result must be correct.
• Execution policies:
1. In-order issue with in-order completion
2. In-order issue with out-of-order completion
3. Out-of-order issue with out-of-order completion
• Examples:
• Intel’s Pentium, IBM Power2, AMD K5, MIPS R10K, HP PA8500, Cyrix 6x86
28
Architectures contd…
29
CISC vs RISC vs SS vs VLIW
CISC RISC Superscalar VLIW
Instruction fixed size (but
variable size fixed size fixed size
size large)
Instruction variable
fixed format fixed format fixed format
format format
few, some GP and rename many, many
Registers many GP
special (RUU) GP
Memory embedded in
load/store load/store load/store
reference many instr’s
data hardware code
decode
Key Issues forwarding, dependency scheduling,
complexity
hazards resolution (compiler)
Instruction IF ID EX M WB
IF ID EX M WB IF ID EX M WB
flow IF ID EX M WB
IF ID EX M WB EX M WB
IF ID EX M WB IF ID EX M WB
IF ID EX M WB IF ID EX M WB EX M WB
ARM Cortex M4-based System
33
Platform for IoT development
35