2015 IEEE International Conference on Communication Networks (ICCN)

Design of Power Efficient Multiplexer using

Dual-Gate FinFET Technology
Mohit Vyas Soumya Kanti Manna Shyam Akashe
Research Scholar, Assistant Professor Professor
ECE Department Department of Electronics and Head of Department
ITM University, Gwalior(MP) Communication, ITM University, Electronics and Communication
[email protected] Gwalior (M.P.) ITM University, Gwalior (M.P.)
[email protected] [email protected]

Abstract -This paper presents the design and analysis programmable logic devices component we can use
of a 2:1 multiplexer. The conventional circuit of 2:1 multiplexer by itemize logic arrangement in the
multiplexer (MUX) is used for the calculation of
input signal then selected input act as logic input.
different parameters like power consumption, noise,
This is mainly useful when cost is a factor. By
delay, leakage power, etc .The multiplexer designed
using FinFET for multiplexer designing we can
in this paper is suitable for low-power applications
control over leakage reduction, and current analysis
and works on very low supply voltage. Multiplexer is
a digital circuit, it consists of 2N input and has n for the better performance in design. Some designs
select line which are used to select the input line to of 2:I Mux are done in 120 nm to achieve the
transmit to the output .The multiplexer are used to operating speed of 34 Gb/s which uses the 2:I
expand the measure of information that can be sent serealizer which consists of CMOS MUX and a
over the system of a sure measure of time and CMU [1].
bandwidth. Multiplexer comprises of multiple input
signals and gives a single output switch. In this paper, Different technique like glue logic in Mux is
a novel FinFET technique is used for the reduction of applied for better performance in the circuit during
leakage power. The parameters of the conventional
run time [2]. Current mode technique is applied in
circuit and FinFET are compared and the
the design of MUX which helps in the reduction of
performance of the multiplexer circuit is increased.
leakage and improving the stability of the circuit
The proposed multiplexer works on supply voltage of
O.7V. The design and simulation of FinFET based 2:1
[3]. Designing of the circuit using adiabatic
multiplexer is done by using 45nm technology at switching for energy consumption and ultra low
cadence virtuoso version 6.1 platform. power approach [4]. By adjusting the duty cycle we
can improve the efficiency of the circuit and with
Keywords - MUX, noise, delay, FinFET, Leakage low power approach [5]. Using transmission gate
power
MUX is designed for low power approach and least
average power consumption and for other
I. INTRODUCTION
performance parameters [6]. High fan in and high
Multiplexer is a device that selects one of many performance in the priority encoder is also
digital or analog input signals and forwards the achieved using MUX [7].
selected input into a single line. 2:1 multiplexer can
Mux has 2m input and one input, where m is the
be considered as a multiple input into a single
selection line. Depending on the select line the
output switch. Multiplexer makes it feasible for a
number of input is decided and hence processed.
few signs to share one gadget or asset for instance
The logical diagram is shown in Fig.l showing
one analog to digital converter or one
input, output and select lines.
correspondence line rather than having one gadget
for every information signal. The schematic
representation for a multiplexer is an isosceles
trapezoid. In a digital circuit, the select line are of
digital value, a logic value of 0 would connect a to
2 input lines � MUX
1 output

the output switch while a logic value of 1 would

/'
connect to the output switch. A 2:1 multiplexer has
a Boolean expression where a and b both are se e ct line
selected as input while s is a select line. In Fig. 1: Diagram of 2:I MUX

978-1-5090-0051-7/15/$31.00©2015 IEEE
DOI I0.II09/ICCN.2015.23
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A multiplexer, or MUX chooses one of n inputs Truth Table of 2:I MUX can be reduced to
and direct it. Depending upon the controlling input
or the selection lines present the total input of the Compressed Truth Table
MUX can be ascertained. With the select line data
TABLE II. Compressed truth table
we get the output depending on the input value.

For instance, in event of 16 conceivable inputs, you RO C Z

require 4 bits to indicate one of 16 qualities. In case 0 0 XO

of, 12 conceivable inputs, despite everything you
require 4 bits, despite the fact that a 4's percentage 1 1 Xl
bit examples may not relate to any of the 12
decisions.
Control bit as a I bit number and c == 0 or c == I,
Table I. Truth table of 2:1 MUX
When �c == 1 (equivalently, c == 0) or c == 1.
Row C XI XO Z
When one minterm is 1, the other minterms are o.

0 0 0 0 0 Thus, when c == 0, we get:

I 0 0 I I z = �cxO + cx1

2 0 I 0 0 = I xO + 0 xl

= xO
3 0 I I I
When c == 1, we get:
4 I 0 0 0
z = �cxO + cx1
5 1 0 1 0
= 0 xO + I xl
6 1 1 0 1
A multiplexer is likewise called a data selector.
7 I I I I
II. WORKING OF 2:1 MUX

The initial four lines have c == 0, so they select A----1

section xO. The second four lines have c == I, so
they select segment xl.

K-map is drawn according to the truth table from

table I, and the equation is reduced to

AB .------.l====;--out
11 10

Fig. 2: K-map of 2:I MUX

PUN = �SA +SB (1)

PDN = -S-A +S-B (2)

Fig.3: 2:1 using CMOS

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Depending on the select line the output is obtained.
As shown in Fig.3 when S =O, A =O and B =O then
the Vdd will get direct path to ground and we get 0
as output. When the select line(S) is 0, A =O and
B =l then also the output we will get will be O.
When A = 1 and B =O then from S and B PMOS the
output we will get is 1 because the entire NMOS
transistor will be off during that time. When A =l
and B =I then also the output we will get is I. When
S =I, A =O and B =O the Vdd will directly go to
ground thus giving 0 at the output. When A =O and
B =I, then the output we will get is I because the
NMOS transistor will be in off stage. When A =I Fig. 5 Output of 2:1 Mux
and B =O then output we will get is 0 as Vdd will
IV. PARAMETERS
get direct path from Vdd to ground. And when A =l
and B =l then the output we will obtain will be high
1. Noise
Noise in any digital on analog circuit
output. Due to so many transitions the leakage in
provide undesired output that will
the CMOS based design circuit is high so the
decrease the efficiency of output signal
proposed design is also shown.
and distortion input signal .due to
III. PROPOSED DESIGN unwanted signal noise is created .Many
technique to reduce noise from the circuit
here we have apply FinFET based
technique.
Sv(f) = 4kTR, f 2:: 0 (3)
A
Where k is Boltzmann constant, R is
noiseless resistor and T is temperature

s 2. Power consumption
Power consumption is characterized as the
�===:E==�-- out average power consumed by the circuit so
as to give us the output .By reducing the
power supply from the circuit then
automatically power consumption of the
circuit will reduce. By using FinFET
A technique the average power is reduce.
The output is shown in Fig.6.

Power (P) = (Vdd) * (a

I vg) (4)

FigA: FinFET based 2:1 MUX

11
The 2:1 MUX is designed by using FinFET in
place of CMOS. The FinFET is used for the ID
reduction in leakage power and thus improving the
performance of the circuit. The working of the
CMOS based 2:I design and FinFET based 2:I is
same but with enhance performance parameter. The
proposed design is shown in Fig, 4. The output of
the designed 2:I MUX is shown in Fig.5. I Ii. Ii i iii i i' i' iii i ii iii i ii iii i i' iii . iii
DD 110 lOO 110

Fig.6: Power Consumption Graph

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 3. Leakage power output switch .[n this paper we measure delay in
Leakage power may be defined as picoseconds. Higher will be the propagation delay
undesirable sub threshold current in the more the time required by the circuit to provide us
channel of transistor when the transistor is the output.
turned off .Now variation in threshold
T (rf)+ T (fr)
voltage then it will strongly affect leakage DeI ay ()
'"[ = (8)
2
power. Leakage power is due to static or
dynamic power. When system in working
mode is known as dynamic power and Where T (rt) = time for rising to falling and T (fr) =
when system is in sleep mode is called time for falling to rising
static power .By using different technique
we can reduce leakage power .In this Y. SIMULATION
paper we have applied FinFET technique
The data acquired regarding the parameters of
to reduce leakage power.
CMOS based and Fin FET based 2:1 MUX is
Power (P o
t a
t )l = Sa
t it c power shown in Table III.
+ Dynamic Power
Table III. Comparison of different parameters of
P (t) = (Vdd) * (Idd ()t ) (5) 2:1 Mux

Where static power, S1. Parameter CMOS FinFET

No based 2:1 based 2:1
P = I * Vdd (6) MUX MUX
1 Noise (yL/Hz) 38.9907p 14.255p
Where dynamic power 2 Power 13.673n 2.68n
Consumption(W)
,P = Ca(Vdd)2F (7) 3 Leakage 37.59p 16.89p
Power(W)
Where C =capacitance 3 Propagation 1.813n 1.76n
Delay(s)
a =switching activity

F = frequency The graph of the CMOS and FinFET based 2:1

MUX parameters are calculated in Table III and the
[ =static current comparison graph is shown in Fig. 8 which tells us
that there is reduction in every performance
Switching activity must be always one. degrading parameter studied above and we get a
better output performance using FinFET.

Comparision Graph
I
110

I I

'I
U

�5D

100
·

Noise powe Leaka Delay

· 150
I iiii Ii. ii' iii, iiiiiiiii Iii Iii iii i ge
DD liD 100 I.
consu Powe
mptio
n
Fig.7: Leakage Power
• CMOS 2:1 MUX 38.99 13.67 37.5 1.81

4. Propagation delay • FinFET 2:1 MUX 13.255 2.68 16.8 1.76

[t may be defined as time required for a digital

Fig. 8: Comparison graph of parameters
signal to travel from the input of a logic gate to the

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 VI. CONCLUSION Computational Intelligence & Communication
Technology, 2015
In this paper we successfully implemented
Multiplier by using CMOS and FinFET technique. [7] Hing Mo Lam, Chi Ying Tsui., " A MUX-based
Thus, result and simulation are measured in table High-Performance Single-Cycle CMOS
III .The analysis and simulation of the desired
Comparator," m proceeding of IEEE
circuit is done with supply voltage of 0.7 V. By
TRANSACTIONS on Circuit and System, vol. 54,
using FinFET based design we reduced such
parameter like leakage power and power no. 7, July 2007, Hong Kong
consumption which will increase the performance
of your circuit. The reduction in noise in the circuit
is about 60% while the reduction in power
consumption and leakage current is about 40% and
50% respectively by using FinFET in place of
CMOS.

ACKNOWLEDGEMENT

I would like to thanks ITM University, Gwalior

which provides the cadence virtuoso tool and doing
work at 45nm technology.

REFERENCE

[I] Ullas Singh, Lijun Li and Michael M.Green., "

A 34 Gb/s Distributed 2:1 MUX and CMU Using
0.18flm CMOS," in proceeding of IEEE Journal of
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2006, California

[2] DJ Greaves, MJ Nam., " Synthesis of Glue

Logic, Transactors, Multiplexors and Serialisors
from Protocol Specifications," in proceeding of
Institute of Electrical and Electronics Engineering,
2010

[3] Lahcen Hamouche and Bruno Allard., "Portless

Low Power Mux Architecture with Line Hard
duplication"

[4] Prasad D Khandekar, Shaila Subbaraman., "

Low Power 2:I MUX for Barrel Shifter," in
proceeding of Institute of Electrical and Electronics
Engineering, 2008

[5] Ahmad Yazdi, Micheal M. Green., " A 40- Gb/s

Full-Rate 2:I MUX in 0.I8-flm CMOS," in
proceeding of IEEE TRANSACTIONS ON
Microwave Theory and Techniques, vol. 59, no. 1l.
November 2011, California

[6] Vivek Kumar Agarwal, Manisha Guduri and

Aminul Islam., " Which is the Best 2-to-I
Multiplexer for Ultralow-Power Applications?," in
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