Interconnects

Design Techniques—Dealing with Capacitive Cross Talk

• Cross talk is a proportional noise source.
• A number of ground rules can be established
1. Bad practice to have two wires on the same layer run parallel for a long distance. Wires on
adjacent layers should be run perpendicular
2. Avoid floating nodes if at all possible. Nodes sensitive to cross talk problems, should be
equipped with keeper devices
3. Sensitive nodes should be well-separated from full-swing signals
4. Make the rise (fall) time as large as possible, subject to timing constraints
5. Use differential signaling in sensitive low-swing wiring networks. This turns the cross talk
signal into a common-mode noise source that does not impact the operation of the circuit.
6. If necessary, provide a shielding wire—GND or VDD—between the two signals
7. The interwire capacitance between signals on different layers can be further reduced by the
addition of extra routing layers. When four or more routing layers are available, we can fall
back to an approach often used in printed circuit board design.
Cross talk and Performance in CMOS
• If all inputs experience a simultaneous transition
in the same direction, the voltage over the
coupling capacitances remains constant, resulting
in a zero contribution to the effective load
capacitance
• The total load capacitance CL of gate Y hence
depends upon the data activities on the
neighboring signals and varies between the
following bounds:
Design Techniques—Circuit Fabrics with Predictable Wire
Delay
1. Evaluate and improve—After detailed extraction and simulation, the bottlenecks
in delay are identified, and the circuit is appropriately modified
2. Constructive layout generation—Wire routing programs take into account the
effects of the adjacent wires, ensuring that the performance requirements are
met
3. Predictable structures—By using predefined, known, or conservative wiring
structures the designer is ensured that the circuit will meet his specifications and
that cross talk will not be a show stopper
Resistive Parasitics • Consider now a 2 cm long VDD or GND wire with a
current of 1mA per µm width, sheet resis tance of 0.05
Ω/q
• the resistance of this wire (per µm width) equals 1 kΩ
• A current of 1 mA/µm would result in a voltage drop of 1
V
• The altered value of the voltage supply reduces noise
margins and changes the logic levels as a function of the
distance from the supply terminals
• Voltage Drop (ΔV):
• The voltage drop across R′ and R leads to a reduction in
the actual supply voltage reaching the components of the
circuit.
• The original supply voltage is VDD​, but after the
parasitic resistance R′, the voltage drops to VDD−ΔV at
the input of the logic gate
Impact on the Circuit:
• Reduced Noise Margins:
• The voltage drop caused by the parasitic resistances decreases the overall power
supplied to the circuit components (the gate in this case).
• With lower voltage levels, the circuit becomes more sensitive to noise.
• The noise margin, which defines how much noise a circuit can tolerate without
causing errors, is reduced because the effective voltage difference between logic
levels (e.g., between VDD​ and ground) becomes smaller.

• Signal Integrity Issues:

• The reduced supply voltage can lead to weaker signals, slower switching times, or
incorrect logic operations.
Electromigration
• The current density (current per unit area) in a metal wire is limited due to an effect called electromigration

• A direct current in a metal wire running over a substantial time period, causes a transport of the metal ions

• this causes the wire to break or to short circuit to another wire. This type of failure will only occur after the
device has been in use for some time

• The rate of the Electro-migration depends upon the temperature, the crystal structure, and the average
current density.

• Electro-migration depends upon the temperature, the crystal structure, and the average current density.

• The latter is the only factor that can be effectively controlled by the circuit designer

• Keeping the current below 0.5 to 1 mA/µm normally prevents migration. This parameter can be used to
determine the minimal wire width of the power and ground network.
Resistance and Performance—RC Delay
1. RC Time Constant:
• The product of resistance (R) and capacitance (C) gives the RC time constant
(τ=RC)
• This time constant determines how long it takes for a signal to rise or fall in a
circuit.
• Specifically, the delay is proportional to RC, meaning that as R or C increases, the
delay increases.
2. Distributed RC Model
• As a signal moves through the wire, it experiences delays at each small segment
due to the resistance and capacitance at that point
• The total delay is the sum of all these small delays along the wire.

3. Effects on Signal Propagation:

• The RC delay causes the signal to slowly rise and fall rather than instantly
switching from low to high or high to low.
• This affects the timing of digital circuits and can limit how fast a chip can operate
A number of design techniques that may help to cope with the delay
imposed by the resistance of a wire

1. Better Interconnect Materials

2. Better Interconnect Strategies

3. Introducing Repeaters

4. Optimizing the Interconnect Architecture

1. Better Interconnect Materials
As circuits scale down in size, interconnect delay due to resistive and
capacitive parasitics becomes more pronounced. One way to address this
challenge is by using better materials that offer lower resistance and
capacitance

• Copper interconnects: Copper has replaced aluminum in many modern integrated

circuits because it has lower resistivity (about 40% lower). This reduces the
resistance (R) in the RC delay equation, directly improving the speed of signal
propagation.

• Low-k dielectrics: To reduce capacitance (C), designers use low-k dielectric

materials between the metal lines. These materials have a lower dielectric constant
(k), which reduces the capacitive coupling between wires, thereby lowering the
overall delay.
• When designing memory arrays, such as SRAM or DRAM, it can be
challenging to avoid using long polysilicon wires, especially for address
lines (such as word lines).
• These wires must connect to many transistors (memory cells), but using
polysilicon for the wires helps maintain high memory density. This is
because polysilicon requires fewer metal contacts, which can take up
space, so it preserves compactness.
• The downside is that polysilicon wires have higher resistance, leading to
longer delays in signal propagation due to the RC delay.
• To address this, there are two strategies for reducing the delay without
compromising density:
• 1. Driving the Word Line from Both Ends
• 2. Metal Bypass
Driving the Word Line from Both Ends
• polysilicon word line is driven by two drivers,
one at each end of the line.
• Instead of a signal having to travel all the way
across a long word line (which would lead to
significant delay), the signal is driven from both
sides.
• Driving from both ends effectively cuts the worst-
case delay by a factor of four. This is because the
signal propagates from both ends towards the
middle, reducing the total distance it must travel
across the high-resistance polysilicon line.
• By splitting the distance the signal needs to travel
in half and using drivers on both ends, the RC
delay is reduced quadratically, resulting in a much
faster signal propagation across the word line.
Metal Bypass

• Another approach is to use a metal bypass wire, which runs parallel to the polysilicon
word line. This metal wire has significantly lower resistance than polysilicon, but it only
connects to the polysilicon line at certain intervals, every k cells.
• Instead of the entire word line being limited by the high resistance of a long polysilicon
wire, the signal now mainly travels through the low-resistance metal wire, while the
polysilicon is only responsible for short segments between the contacts. As a result, the
propagation delay is significantly reduced, and the delay is dominated by the shorter
polysilicon segments.
• By limiting the use of high-resistance polysilicon to small segments and relying on a low-
resistance metal line for the longer distances, this method speeds up signal propagation
while still preserving implementation density. The memory array remains dense because
metal contacts are only placed every k cells.
2. Better Interconnect Strategies
• In the design of electronic chips, one of the biggest challenges is how to connect
different parts of the chip (called interconnections) using wires

• These wires carry signals from one part of the chip to another. The length of the
wire is really important because:
• Longer wires cause more delay (signals take longer to travel).
• Longer wires also use more power, which reduces the chip's efficiency.

• To solve this, different methods of routing the wires are used. Traditionally, a
method called Manhattan routing was used. Recently, a better method, diagonal
routing, has been found to improve the chip's performance by shortening the
wires.
• Manhattan Routing: Wires are routed in horizontal and vertical directions (along x and y
axes).
Example: A wire first moves horizontally (x-axis) and then vertically (y-axis) to reach its
destination.

• Diagonal Routing: Instead of strict x and y movement, wires can follow diagonal paths
(45° lines), which reduces the total wire length
• Diagonal Routing:
• Reduces wire length
• Shorter wires mean faster signal transmission and lower energy consumption.
• Chip area reduction: Less wire length leads to more efficient use of space on the chip,
reducing the overall chip size.
Challenges with Diagonal Routing:
•Early on, 45° lines were popular but then fell out of use due to:
•Tool complexity: More complex design and manufacturing processes.
•Mask-making issues: Difficulty in creating masks for integrated
circuit fabrication

Recent Improvements:
•Newer techniques have made diagonal routing feasible again, and it can
reduce wire length by 20%, leading to:
•Higher performance
•Lower power usage
•Smaller chip area
3. Introducing Repeaters
• The most popular design approach to reducing the propagation delay of long wires
is to introduce intermediate buffers, also called repeaters, in the interconnect line

• Making an interconnect line m times shorter reduces its propagation delay

quadratically, and is sufficient to offset the extra delay of the repeaters when the
wire is sufficiently long
• Assuming that the repeaters have a fixed delay tpbuf , we can derive the delay of
the partitioned wire
4. Optimizing the Interconnect Architecture
• When designing computer chips, wire delay—the time it takes for
signals to travel along a wire—is a big problem, especially as chips get
faster and wires get longer.
• Even if we use buffers, there is still a limit to how fast we can send
signals down long wires.
• This delay can slow down the performance of the entire chip.
• Chips operate at very high speeds, typically with a clock that controls
how fast everything happens.
• Some wires, however, are so long that even with optimizations, the
signal may take much longer to travel across them
• This means that even though the chip’s clock is fast, the wire itself
slows things down. This limits the overall performance of the chip.
• Solution: Wire Pipelining
• In chip design, pipelining means splitting the work across multiple stages, so even
though each stage takes time, you can process many signals at the same time.
• With wire pipelining, you insert registers or latches along the wire to break it into
smaller sections.
• Instead of waiting for the signal to travel the whole length in one go, you process
it in smaller steps.
• This doesn't reduce the total delay (the signal still needs time to travel), but it
increases the throughput—meaning you can have multiple signals moving through
the wire at the same time.
• Another option is you can add repeaters (boosters for signals) between segments
to ensure the signals move fast enough within each segment and that the delay is
kept below one clock cycle for each segment.
Inductive Parasitic
• Inductive Parasitic occur due to the inductance in interconnect wires,
bonding wires, and chip packages, which are not ideal and introduce
parasitic elements in a circuit
• These parasitic inductances cause issues such as voltage drops, signal
ringing, overshooting, and wave propagation delays at high switching
speeds.
• Signal ringing refers to the unwanted oscillations or "bouncing" of a
signal around its final value, especially after a sharp change, such as
when a signal switches from low to high (or vice versa)
• Overshooting is when a signal goes beyond its intended maximum
value during a transition.
Inductance and Reliability—L(di/dt) Voltage Drop:
• When a circuit switches, transient currents are sourced from (or sunk
into) the supply rails to charge or discharge capacitors in the circuit
• This transient current creates a voltage drop due to parasitic
inductance in the interconnects, following the relationship 𝐿𝑑𝑖/𝑑𝑡
(where L is inductance, and 𝑑𝑖/𝑑𝑡 is the rate of change of current)
• This voltage drop can cause a difference between external and internal
supply voltages, denoted as 𝑉𝐷𝐷−𝐺𝑁𝐷 in the diagram.
• This voltage difference, especially at the output, can become
significant when large capacitive loads are driven, leading to large
current surges.
• This can affect the internal supply voltage, thereby reducing noise
margins and affecting logic levels.
 • The diagram illustrates inductive coupling between external
and internal power supply voltages in a circuit

• It shows a transient current 𝑖(𝑡) passing through an inductor 𝐿,

which causes a voltage drop across the inductor, resulting in a
difference between the supply voltage (𝑉𝐷𝐷) and ground (𝐺𝑁
𝐷)

• The circuit also shows the presence of a load capacitor 𝐶𝐿,

which requires current to charge and discharge during
switching events, leading to the effects described

• When multiple output drivers, such as the 16 drivers of an output bus, switch at the
same time, they draw a large transient current simultaneously

• This simultaneous current demand can cause a substantial voltage drop across the
inductive parasitic in the power supply network
Design Techniques
A number of approaches are available to the designer to address the L(di/dt)
problem
1. Separate power pins for I/O pads and chip core
2. Multiple power and ground pins
3. Careful selection of the positions of the power and ground pins on the package
4. Increase the rise and fall times
5. Use advanced packaging technologies
6. Adding decoupling capacitances on the board
7. Adding decoupling capacitances on the chip
1. Separate power pins for I/O pads and chip core
• I/O drivers typically require the largest switching currents, as they handle signals
going in and out of the chip.
• These drivers experience the most significant current changes when they switch
states, leading to large L(di/dt) voltage drops
• To prevent the noise and voltage fluctuations caused by these large current
changes from affecting the core logic of the chip, it is beneficial to isolate the
power supplies for the I/O pads and the chip’s internal logic
• This is done by using separate power and ground pins for:
• The I/O drivers (which handle external communication)
• The chip core (which handles the internal logic operations)
• By separating the power supplies, the switching noise generated by the I/O drivers
does not propagate to the sensitive core logic circuitry
• This isolation reduces the risk of logic errors and ensures more stable operation
for the core logic, especially in high-speed circuits where fast switching occurs.
 2. Multiple power and ground pins
• I/O drivers require substantial current to switch, and when multiple drivers switch
simultaneously, it causes large current surges, leading to significant voltage drops due to
parasitic inductance
• To minimize this, designers can reduce the di/dt per supply pin by limiting the number of
I/O drivers connected to each power pin.
• Typical designs connect around five to ten drivers per power pin to distribute the current
load.
• The exact number of drivers connected to a single pin depends on factors such as:
• The switching characteristics of the drivers (how fast they switch and how much current they draw).
• The number of gates switching simultaneously
• The rise and fall times of the signals
• By distributing the load across multiple power and ground pins, the current per pin is
reduced, lowering the L(di/dt) voltage drop
• This approach helps maintain stable supply voltages, minimizing the risk of noise and
ensuring more reliable circuit operation, particularly during high-speed switching.
3. Careful selection of the positions of the power and ground pins on
the package
• The inductance of the pins on the chip package can vary based on their physical location
• Pins located at the corners of the package generally have substantially higher inductance
compared to those positioned closer to the center
• This higher inductance at the corners can lead to larger voltage drops due to the L(di/dt) effect,
especially during fast switching events when the current changes rapidly.
• It is advisable to place power and ground pins closer to the center of the package rather than at
the corners, where inductance is lower
• This helps in reducing the inductive parasitic effects and ensures a more stable power supply to
the chip
• By optimizing the positions of the power and ground pins, the inductive voltage drop across the
pins can be minimized, improving the reliability of the circuit
• This careful pin placement can also help in enhancing performance, especially for high-speed
circuits where the impact of inductance is more significant.
Increase the rise and fall times
• When electronic signals travel from a chip to the outside world (off-
chip), it's better to make the signals change (rise and fall) as slowly as
possible, within allowed limits.
• This helps reduce problems, especially when the signals have to travel
over long distances across the chip, like under data buses.
• If you try to make signals change too fast, you need bigger
components, which take up more space on the chip
Use advanced packaging technologies
• Advanced packaging technologies, like surface-mount or hybrid techniques, help
make electronic components smaller and more efficient. These methods
significantly reduce the unwanted effects of capacitance and inductance (which
can cause delays or noise in the circuit)

• One example is a flip-chip package, where the chip is mounted directly onto the
circuit board using tiny solder bumps. This setup reduces the inductance (which
slows down the signal) to just 0.1 nano henries (nH), which is 50 to 100 times
smaller compared to traditional packaging methods

• In simple terms, the newer packaging methods make the connections shorter and
cleaner, leading to faster and more reliable electronic devices.
Adding decoupling capacitances on the board
• Adding decoupling capacitors to a circuit helps keep the power supply to a chip
steady
• These capacitors act like small energy storage units placed next to the chip
• When the power supply fluctuates (due to fast-changing signals), the capacitors
release energy to smooth out these changes and prevent voltage drops or spikes
• They also help filter out unwanted noise from the power lines, making sure the
chip receives clean, stable power, which improves its performance and reliability
Adding decoupling capacitances on the chip
• In high-performance circuits, where signals switch quickly, adding
decoupling capacitors directly on the chip is a common practice to stabilize
the power supply and reduce voltage fluctuations. These on-chip capacitors
help ensure that the chip gets a steady voltage, especially during fast
changes in current demand

• For instance, in a typical design, around 12.5 nano farads (nF) of

capacitance is needed for every 50,000 logic gates to keep the voltage ripple
(variation) under 0.25 volts. These capacitors are often made using thin
layers of material (like thin gate oxide in transistors). Essentially, a thin-
oxide capacitor is like a MOS transistor, but with both ends (drain and
source) connected together to act as a capacitor, which stores and releases
charge when needed to stabilize the voltage.
Inductance and Performance—Transmission Line Effects
• When circuits run very fast or when wires become long enough, the inductance of the wire starts
affecting how quickly signals can travel through the circuit. This means that transmission line
effects must be considered. These effects become significant when the time it takes for a signal to
rise or fall is similar to the time it takes the signal to travel across the wire (based on the speed of
light).
• Initially, these issues mainly affected the fastest digital circuits or specialized technologies (like
GaAs and SiGe). But as modern CMOS circuits become faster and more complex, transmission
line effects are also becoming a concern in CMOS design.
• To reduce these effects:
• Termination: Properly "terminating" the wire at the ends (with resistors or other techniques) can
help prevent signal reflections, which cause noise and delay.
• Current-return path: Ensuring the current has a clear path to return is crucial for effective
termination.
• Shielding: Using shields around wires that are prone to transmission line effects helps protect them
from interference and minimizes signal distortion.
• These techniques help ensure that signals travel cleanly and quickly without interference.
Termination
• In circuits where transmission line effects are significant, such as when signals travel
through long wires or at high speeds, proper termination is key to minimizing issues like
ringing and slow signal delays.
• Termination refers to adding a resistor at either the source (where the signal starts) or the
destination (where the signal ends). This resistor should match the characteristic
impedance (Z₀) of the transmission line. When done correctly, termination ensures the
signal travels smoothly along the wire without bouncing back or causing delays.
• There are two common methods of termination:
• Series termination: A resistor is placed at the source of the signal. This helps prevent
reflections by slowing the signal just enough so that it matches the impedance of the line.
• Parallel termination: A resistor is placed at the destination, which absorbs any
reflections and prevents them from bouncing back down the line.
• Matching the load impedance to the line’s impedance results in the fastest signal response,
reducing unwanted effects like ringing and improving overall performance.
Shielding
• Signal and Return Path: When you send a current through a wire, there must be a return path for the
current to complete the circuit. The return current flows in the opposite direction. How this return current
flows is very important because it affects how well the signal travels through the wire. If it's not
managed properly, the signal can get distorted or interfere with other signals.
• Shielding:
On a circuit board or chip, we can do something similar by placing ground planes or shielding
wires around the signal wires. This helps ensure that the signal behaves predictably and isn’t
affected by other signals or noise.
• Benefit: Shielding makes the signal more reliable and reduces interference.
• Challenge: It takes up more space on the board or chip, which can be expensive. Also, as circuits get
faster and more complex, engineers will need better tools to simulate and manage these connections to
ensure they work correctly. In short, shielding helps keep signals clean and predictable, but it requires
careful planning and extra space.