Verilog Practice Sheet 1

Sudhanva Joshi - 202310202022

27-09-2024

Note: Some Practice Problem folders contain files which were used to test logical
implementation of circuits under the assumption that they shall be exempt from grading.

1 Q9: Constructing Sequential Circuits

1.1 9A. Equations
Given corresponding equations for our inputs A and B:

A(t + 1) = xy + xB

B(t + 1) = xA + xB
Z=A
We get the following Logic Diagram after connecting our D flip-flops to our com-
binational logic.

Figure 1: Logic Diagram from Equations

To get various combinations of present state and inputs, we run multiple for loops
to simulate for output. Therefore, we have 16 different cases that are possible.
Note: The output relation Z = A refers to the current value of A.

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 Figure 2: State Table

Our results are cross-verified after running the corresponding simulations.

Figure 3: Timing Diagram, GTKWave

The following State Diagram is found.

Figure 4: Timing Diagram, GTKWave

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 We have the following Verilog Modules written for simulation.
Clock Module
module c l k g e n ( output r e g c l k ) ;
i n i t i a l clk = 0;
always #10 c l k = ˜ c l k ;

endmodule
D Flip-Flop
module d f f ( i n p u t c l k , i n p u t d , i n p u t r s t , output r e g q ) ;

always @( p o s e d g e c l k ) b e g i n
i f ( ! r s t ) begin
q <= 0 ;
end
e l s e begin
q <= d ;
end
end

endmodule
Module, Q9 A
module q 9 a ( i n p u t c l k , i n p u t x , i n p u t y , output r e g z ) ;

wire a curr , b curr ;

wire a next , b next ;
assign a n e x t = ( x & ˜y ) | ( x & b c u r r ) ;
assign b next = ( x & a curr ) | ( x & ˜ b curr ) ;

d f f dA( c l k , a n e x t , a c u r r ) ;
d f f dB( c l k , b next , b c u r r ) ;

always @( p o s e d g e c l k ) b e g i n
z = a curr ;
end
endmodule
Testbench, Q9 A
module q 9 t b ; // t e s t b e n c h f o r q 9 a .
reg clk , x , y , r s t ;
wire z ;
q 9 a U1 ( c l k , x , y , z ) ;
// q9 b U2 ( . c l k ( c l k ) , . r s t ( r s t ) , . o u t a ( a n e x t ) , . o u t b ( b n e x t ) ) ;

i n i t i a l begin
$ d u m p f i l e ( ” q9 . vcd ” ) ;
$ dumpvars ( 0 , q 9 t b ) ;
c l k = 1 ’ b0 ;

f o r e v e r #5 c l k = ˜ c l k ;
end

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 i n i t i a l begin
clk = 0;
#10; \\ I t e r a t e through x and y v a l u e s
$finish ;
end

i n i t i a l begin
$ d i s p l a y (” ”);
$display (”| x | y | z | ” ) ;
$ monitor ( ” | %b | %b | %b | ” , x , y , z ) ;
$ d i s p l a y (”’===========’”);
end
endmodule

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1.2 9B. State Diagram & Verilog Simulation
We have the given Logic Diagram.

Figure 5: Logic Diagram from Equations

We can define our Inputs as follows.

X = A(t) + B(t)
Y = A′ (t) + B(t)
Then, our Outputs shall be based on our T flip-flop logic.
A(t + 1) = A(t) + B(t)
Y (t + 1) = A′ (t) + B(t)
Applying different Present States to get our Inputs, we get the following conditions
for Next States.

Figure 6: State Diagram, Input/Output Transitions

We see that this gives us a cycle as follows:

11− > Cycle(00− > 01− > 10)
We can set our states as given below.
S0 = 00, S1 = 01, S2 = 10, S3 = 11

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 Deriving our State Diagram from the Table:

Figure 7: State Diagram, Input/Output Transitions

Our results are cross-verified after running the corresponding simulations.

Figure 8: Monitor, Testbench

Figure 9: Timing Diagram, GTKWave

Recreating this logic in our design file, the following code can be used to simulate
our sequential logic.
T Flip-Flop
module t f f ( c l k , r s t , t , q ) ;
input clk , rst , t ;
output r e g q ;
always @( p o s e d g e c l k ) b e g i n
i f (! rst )
q <= 0 ;
else
if (t)
q <= ˜q ;
else
q <= q ;
end
endmodule

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 Module, Q9 B
module q9 b ( c l k , r s t , o ut a , o u t b ) ;
input clk , r s t ;
output r e g ou t a , o u t b ;
wire a , b ;
t f f A ff ( . clk ( clk ) , . rst ( rst ) , . t (a | b) , . q(a ) ) ;
t f f B ff ( . c l k ( c l k ) , . r s t ( r s t ) , . t (˜ a | b ) , . q (b ) ) ;
always @( p o s e d g e c l k o r negedge r s t ) b e g i n
i f ( ! r s t ) begin
o u t a <= 0 ;
o u t b <= 0 ;
end

e l s e begin
o u t a <= a ;
o u t b <= b ;
end
end
endmodule
Testbench, Q9 B
module q 9 t b ; // t e s t b e n c h f o r q9 b
reg clk , r s t ;

w i r e x , y , a n e x t , b next , z ;

// q 9 a U1 ( c l k , x , y , z ) ;
q9 b U2 ( . c l k ( c l k ) , . r s t ( r s t ) , . o u t a ( a n e x t ) , . o u t b ( b n e x t ) ) ;

i n i t i a l begin
$ d u m p f i l e ( ” q9 . vcd ” ) ;
$ dumpvars ( 0 , q 9 t b ) ;
c l k = 1 ’ b0 ;
f o r e v e r #5 c l k = ˜ c l k ;
end

i n i t i a l begin
r s t = 1 ’ b0 ;
#10 r s t = 1 ’ b1 ;
#70;
$finish ;
end

i n i t i a l begin
$ d i s p l a y (” ”);
$display (”| a | b | ” ) ;
$ monitor ( ” | %b | %b | ” , a n e x t , b n e x t ) ;
$ d i s p l a y (”’=======’”);
end
endmodule

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2 Q10: Finite State Machines
2.1 10A. Moore FSM
Given below is the respective design and Testbench modules for our Moore FSM.
Module, Moore FSM
module moore fsm ( i n p u t c l k , i n p u t r s t , i n p u t x , output r e g z ) ;

parameter A = 2 ’ b00 ;
parameter B = 2 ’ b01 ;
parameter C = 2 ’ b10 ;
parameter D = 2 ’ b11 ;
reg [ 1 : 0 ] curr state , next state ;
always @( p o s e d g e c l k o r p o s e d g e r s t ) b e g i n
i f ( r s t ) begin
c u r r s t a t e <= A;
end
e l s e c u r r s t a t e <= n e x t s t a t e ;
end

always @( c u r r s t a t e o r x ) b e g i n
case ( curr state )
A: b e g i n
i f ( x == 0 ) n e x t s t a t e = B;
else next state = C;
end
B: begin
i f ( x == 0 ) n e x t s t a t e = C;
else next state = D;
end
C: begin
i f ( x == 0 ) n e x t s t a t e = B;
else next state = D;
end
D: b e g i n
i f ( x == 0 ) n e x t s t a t e = C;
else next state = A;
end
d e f a u l t : n e x t s t a t e = A;
endcase
end

always@ ( c u r r s t a t e ) b e g i n
case ( curr state )
A : z = 0;
B : z = 1;
C : z = 1;
D : z = 0;
default : z = 0;
endcase
end
endmodule

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 Testbench, Moore FSM
module q 1 0 t b ;
reg clk , rst , x ;
wire z ;
moore fsm U1( c l k , r s t , x , z ) ;
// m o o r e s e q d e t e c t o r 1 0 1 0 tb ( c l k , r s t n , x , z ) ;
// mealy fsm U2( c l k , r s t , x , z ) ;
i n i t i a l begin
$ d u m p f i l e ( ” q10 . vcd ” ) ;
$ dumpvars ( 0 , q 1 0 t b ) ;
clk = 0;
rst = 1;
f o r e v e r #5 c l k = ˜ c l k ;
end
i n i t i a l begin
// c y c l i n g through i n p u t s
end
i n i t i a l begin
$ d i s p l a y (” ”);
$display (”| x | z | ” ) ;
$ monitor ( ” | %b | %b | ” , x , z ) ;
$ d i s p l a y (”’=======’”);
end
endmodule
We get the following State Table from our module simulations.

Current State Input Next State Output

a 0 b 1
a 1 c 1
b 0 c 1
b 1 d 0
c 0 b 1
c 1 d 0
d 0 c 1
d 1 a 0

Table 1: State Table, Moore FSM

We get the following Timing Diagram from our module simulations.

Figure 10: Moore FSM Timing Diagram, GTKWave

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2.2 10B. Mealy FSM
Given below is the respective design and Testbench modules for our Moore FSM.
Module, Mealy FSM
module mealy fsm ( i n p u t c l k , i n p u t r s t , i n p u t x , output r e g z ) ;
parameter A = 2 ’ b00 ;
parameter B = 2 ’ b01 ;
parameter C = 2 ’ b10 ;
parameter D = 2 ’ b11 ;

reg [ 1 : 0 ] curr state , next state ;

always @( p o s e d g e c l k o r p o s e d g e r s t ) b e g i n
i f ( r s t ) begin
c u r r s t a t e <= A;
end
e l s e c u r r s t a t e <= n e x t s t a t e ;
end

always @( c u r r s t a t e o r x ) b e g i n
case ( curr state )
A: b e g i n
i f ( x == 0 ) n e x t s t a t e = B;
else next state = C;
end
B: begin
i f ( x == 0 ) n e x t s t a t e = C;
else next state = D;
end
C: begin
i f ( x == 0 ) n e x t s t a t e = B;
else next state = D;
end
D: b e g i n
i f ( x == 0 ) n e x t s t a t e = C;
else next state = A;
end
d e f a u l t : n e x t s t a t e = A;
endcase
end

always@ ( * ) b e g i n
case ( curr state )
A : z = ( x == 0) ? 1 : 0;
B : z = ( x == 0) ? 0 : 1;
C : z = ( x == 0) ? 0 : 1;
D : z = ( x == 0) ? 1 : 0;
default : z = 0;
endcase
end

endmodule

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 Testbench, Mealy FSM
module q 1 0 t b ;
reg clk , rst , x ;
wire z ;
// moore fsm U1( c l k , r s t , x , z ) ;
mealy fsm U2( c l k , r s t , x , z ) ;
i n i t i a l begin
$ d u m p f i l e ( ” q10 . vcd ” ) ;
$ dumpvars ( 0 , q 1 0 t b ) ;
clk = 0;
rst = 1;
f o r e v e r #5 c l k = ˜ c l k ;
end
i n i t i a l begin
// c y c l i n g through i n p u t s
end
i n i t i a l begin
$ d i s p l a y (” ”);
$display (”| x | z | ” ) ;
$ monitor ( ” | %b | %b | ” , x , z ) ;
$ d i s p l a y (”’=======’”);
end
endmodule
We get the following State Table from our module simulations.

Current State Input Next State Output

a 0 b 1
a 1 c 0
b 0 c 0
b 1 d 1
c 0 b 0
c 1 d 1
d 0 c 1
d 1 a 0

Table 2: State Table, Mealy FSM

We get the following Timing Diagram from our module simulations.

Figure 11: Mealy FSM Timing Diagram, GTKWave

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