Introduction to VLSI LAB

REPORT

Submitted to:
Sir Omer Imtiaz
Submitted by:
Maham Aamir 2020-EE-52

Department of Electrical Engineering

University of Engineering and Technology Lahore
 Lab 1 – Virtuoso - Inverter Design and Simulation
Introduction:
We were tasked with designing an inverter using MOSFETs from gpdk045, which was a made-
up 45nm process by Cadence. We had to manually place parts and connect them together, then
observe how they worked. Additionally, we had to do the same process for a NAND gate. We
created the design and tested it on the computer, and then we organized everything neatly
within the given time frame.

Description:
In Lab VLSI 1, we were tasked with designing an inverter using MOSFETs from Cadence's fictional 45nm
process PDK, gpdk045. Our process involved manually placing components and creating connections
while observing resulting electrical properties. We replicated this procedure for a NAND gate.We
initiated the setup by creating a new folder named "training_inverter" in the Documents directory and
accessed Virtuoso through the terminal using the "virtuoso &" command.

Subsequently, we established a new library called "Labvlsi" linked to the gpdk045 technology. Within
this library, we crafted an inverter schematic by adding NMOS and PMOS components, supply (vdd) and
ground (gnd) symbols, and input/output pins. To evaluate our design, we employed the ADE-L tool to
simulate the inverter schematic. This involved setting up model libraries, defining analyses, selecting
outputs for plotting, and creating stimuli for input signals. After running the simulation, we analyzed the
waveform results obtained. Additionally, we generated a symbol for the inverter schematic that
represented its function accurately, ensuring its usability for future applications. We proceeded by
creating an "inverter_tb" schematic to test the inverter as a component. Within this test bench, we
placed the inverter symbol and included essential supply, ground, and input/output pins for testing
purposes .Simulations for the inverter test bench were conducted using ADE L.
 Lab 2 – Virtuoso - Digital Gate Custom Layout

Introduction:

This lab was a continuation of the previous lab.

Description:

We opened Virtuoso and accessed the inverter schematic from the Library Manager. Then we launched
Layout XL and a blank Virtuoso Layout Suite XL window appeared. We generated the layout for the
inverter, created VDD and GND rails, and connected terminals. Then for running DRC using PVS we
prepared directories for DRC by creating folders in the working directory. Ran DRC using PVS, set the run
directory, specified technology mapping files, and checked for any DRC violations.

Then came the part of Running LVS using PVS. We created a folder for LVS in the working directory. Ran
LVS using PVS, set the run directory, mapped technology files, and verified the comparison results to
ensure schematic and layout matching. And then corrected layout issues

Then we ran Parasitic Extraction using QRC-L. We established a directory for QRC in the working
directory. We executed parasitic extraction using QRC-L, ensuring the creation of quantus input data.
Checked for clean and match status, ran the extraction, and verified parasitic components in the
extracted layout. We Created symbols for the inverter and inverter test bench schematic. Configured
ADE-L to simulate the extracted layout from the pvs extracted view. At the end we ran the simulation
and verified the output waveform, ensuring correctness.
 Lab 3 – Draw MOSFET’s Layout

Introduction:

In this lab we looked into the analogy of an IC design. Our primary task was to manually construct the
pmos layout using rectangles representing distinct layers.

Description:

We generated the PR boundary and adjusted grid dimensions to align with the manufacturing grid for
ease of drawing. Subsequently, we created the N-well rectangle for the pmos, fine-tuned its dimensions,
and rectified its length as per instructions. The pmos layout took shape with rectangles for layers such as
Nimp, Pimp, Poly, Oxide, Metal1, and Cont. Completing connections for the inverter and conducting a
Design Rule Check (DRC) helped identify errors, leading us to review specific pages in the DRC
documentation and document error names and descriptions. We rectified them and proceeded to
perform the Layout Versus Schematic (LVS) check. Adjustments were made in pmos’ finger length. Then
we created a nmos layout and made comparison between the top-down view of the inverter's layout
developed in Virtuoso and the cross-sectional view presented in the textbook.
 Lab 4a – TCL Introduction

Introduction:

This lab was based on TCL which is a scripting language that has traditionally been used in VLSI design
for decades.

Description:

We were given 5 tasks for this lab which are given below

1. Set and print variable values, and perform computation.

❖ set num1 10
❖ set num2 5
❖ set result [expr $num1 + $num2]
❖ puts "The sum of $num1 and $num2 is $result"

2. If-then-else statement, and for and while loops

# IF Else

❖ set x 7
❖ if {$x > 5} {
❖ puts "x is greater than 5"
❖ } else {
❖ puts "x is less than or equal to 5"
❖ }

# For Loop

❖ for {set i 0} {$i < 5} {incr i} {

❖ puts "Iteration $i"
❖ }

# While Loop

❖ set j 0
❖ while {$j < 5} {
❖ puts "Value of j is $j"
❖ incr j
❖ }
3. Creating and indexing lists:

❖ set fruits {apple orange banana}

❖ puts "The second fruit in the list is [lindex $fruits 1]"

4. File IO:
❖ set filename "lab4a.txt"
❖ set file [open $lab4a "w"]
❖ puts $file "This lab is based on TCL."
❖ close $file

# Reading from File

❖ set file [open $lab4a"r"]

❖ set content [read $file]
❖ puts $content
❖ close $file

5. Accessing shell environment variables:

❖ puts "The current user is $env(USER)"
❖ puts "The home directory is $env(HOME)"
 Lab 4b – Synthesis in Genus

Introduction:

We utilized the Genus TM Synthesis Solution (Genus) tool in Stylus Common UI mode for RTL to
gate-level netlist synthesis. Our process involved using RTL, standard cell library, and
constraints as inputs, yielding gate-level netlist and detailed SDC outputs for subsequent
placement and routing steps. Additionally, an optional SDF file was generated to aid in gate-
level simulation post-synthesis.

Description:

In preparation for synthesizing the RISC-V processor, we initiated by establishing a dedicated working
directory (/home/student/Documents/riscv_practice) using terminal commands, confirmed the
directory, and utilized helpful shortcuts like TAB for efficient navigation. Essential folders—constraints,
lib, rtl, and synthesis—were copied from the provided directory to the designated location, ensuring
their presence. Moving the 'riscv.v' file to the rtl folder and deleting an outdated file ('counter.v') was
accomplished and verified. Next, a detailed examination of the 'riscv.v' code, focusing on RISCVCPU
module's input and output names, was conducted. Alterations were made in the constraints file
('constraints_top.sdc') by replacing specific terms, facilitating necessary modifications in
'set_input_delay' and 'set_output_delay' commands.

Q1- Why was this change made?

The alteration in the constraints file aimed to synchronize the timing constraints with the inputs
and outputs of the RISC-V processor design, substituting "rst" with "Instr DMem_in" and "count"
with "DMem_out DMem_addr IMem_addr" to accurately reflect the processor's signal
functionalities during synthesis.

We navigated to the synthesis folder, updated the Genus script, launched Genus, executed synthesis-
related commands, and analyzed the timing report for the synthesized design.
Q2-Which two registers is the critical path between? (see Startpoint and Endpoint).

Start point: IDEXIR_reg [4]/CK

End point: EXMEMALUOout_reg [31]/D

We dead the report riscv_power_report

Q3-Note total power consumed

Total power consumed = 2.66977 × 10−4Watts

We dead the report riscv_qor_report

Q4- Use the Critical Path Slack to determine the upper bound of the clock frequency for your
synthesized module

Frequency was 152MHz

Files `riscv_timing_report`, `riscv_power_report`, and `riscv_qor_report` were renamed to `.old`

versions. Then, the RTL code in `riscv.v` was altered by adding a multiply instruction. the Genus TCL
script using `genus -f genus_script.tcl` generated timing, power, and quality of results (QoR) reports for
the modified processor design.

Q5-Which two registers is the critical path between now?

Start point: IDEXB_reg [1]/CK

End point: EXMEMALUOut_reg [30]/D

Q6-Percentage increase in total power?

 After using the given formula the percentage is 86.6%

Q7-Percentage increase in total area?

After using the given formula the percentage is 21.44%

Q8-Calculate the upper bound on clock frequency?

It was 152.3MHz

We Commented the following line in the riscv.v code

1: EXMEMALUOut <= Ain * Bin; // mul operation

And ran genus again.

Q9-What is the total instance count?

2988.

Q10-Note the new values of Target and Slack. Keep searching for “cost group” and note
values of Target and Slack every time they have changed.

TARGET SLACK

295 3432

196 342

297 3064

198 2986
 Lab 5 – Innovus: Floorplan Design and Layout for RISC-V Processor

Intoduction:

In this lab we works on synthesized netlist in INNOVUS for placement and routing.

Description:

In our work on the RISC-V processor within Innovus for placement and routing, we commenced by
setting the work directory to `/home/student/Documents/riscv_practice/physical_design`. Necessary
design folders were copied from the specified source directory, and then Innovus was launched via the
terminal. We imported the design, configured corners, modes, and pointers in the `riscv.view` file, and
subsequently conducted floorplanning, specifying the aspect ratio, core boundaries, and distances for
the design. Following this, we carried out power planning, adding rings and stripes for VDD/VSS nets,
and formed power rails through special routes. We proceeded with placement optimization, examined
post-placement cell placements and routes in the Physical View, and saved the configured design. Clock
tree synthesis was performed, accompanied by RC extraction, timing analysis, and physical verification
for geometry and connectivity. Lastly, we ran the design on another setup and explored Innovus
commands and their effects through a provided script.
 Lab 6 - Genus PPA Trade-Offs

Introduction:

Power performance and area tradeoff was studies in this manual.

Description:

We started with 'riscv_with_scan_chains' folder. Within this folder 'riscv_with_scan_chains' folder, we

accessed the 'synthesis' directory and edited the 'genus_script.tcl' file using the 'subl' command,
modifying it to save it as 'riscv_timing_report_run1', 'riscv_power_report_run1', 'riscv_qor_report_run1',
and renaming the netlist as 'run1_riscv_netlist.v'. Upon executing 'genus -f genus_script.tcl', this time with
additional DFT commands, we ensured the completion of the script. Following this, we recorded various
parameters in a table, encompassing Effort, Clock Period, Critical Path Slack, Area, and Power after the
first synthesis run. For the second run, denoted as 'run2', we adjusted the 'genus_script.tcl' file accordingly
and modified the clock specifications within the 'constraints_top.sdc' file to ensure a time period of 4ns
with a 50% duty cycle. Executing 'genus_script.tcl' once again, we diligently observed and documented
the outcomes of this second synthesis run, especially noting the alterations in the critical path compared
to the initial run.

Q1- Has run2 achieved non-negative slack?

Run Effort Clock Period Critical Path Slack Area Power

2 Medium 4 0.3 18676.9 0.8129

We changed clock period to 2ns, with 50% duty cycle. Ran genus_script.tcl again

Q1- Has run3 achieved non-negative slack?

Run Effort Clock Period Critical Path Slack Area Power

3 Medium 2 -632.3 20324.7 1.754

 Q1- For the fourth synthesis run, change effort levels in genus_script.tcl from medium to high,
and change run3 to run4.?

Run Effort Clock Period Critical Path Slack Area Power

4 High 2 -402.5 21711.3 2.594

 Lab 7: Innovus - OA Library Format, DRC & Timing Analysis

Introduction:

This lab was based on timing violation discussions

Description:

We commenced by copying the 'riscv_with_scan_chains_v2' folder from the specified location to our
'Documents' directory '/home/student/Documents/riscv_with_scan_chains_v2/physical_design'. To
include library formats instead of 'lef' files, we sought 'cds.lib' files within the '/mnt/Cadence/PDK'
directory. Upon identifying the 'cds.lib' file in 'gpdk045_v_6_0', we programmatically stored this path into
a bash variable 'gpdk_oa_path' by using the 'find' and 'grep' commands. Verifying its value using 'echo
${gpdk_oa_path}', we appended this path to a newly created 'cds.lib' file and added another line for the
library 'gsclib045_all_v4.4/cds.lib' using the 'echo' command. Next, we opened the 'innovus_script.tcl' file
with 'subl' command and modified it by commenting the 'read_physical -lef' command and inserted a new
line 'read_physical -oa_ref_libs {gsclib045 giolib045} -oa_tech_lib {gsclib045_tech}' below it. This
command was researched using 'man read_physical' to comprehend its flags and implications. Executing
'innovus_script.tcl', we observed numerous Design Rule Check (DRC) violations. Using the GUI, we
inspected the violations by zooming in on crosses and clicked to view the description of the selected
violation in the status bar at the bottom, recording these issues for further analysis.

Q1-Write down the descriptions of any two DRC violations.

MAR Violation, R-Grid Violation

We adjusted the 'innovus_script.tcl' to save the 'check_drc' output as 'drc_report'. By altering the stripes
to 'Metal10', we reran the script, eliminating DRC violations. Next, we confirmed no setup timing issues
but found 1291 hold time violations. Debugging in 'Timing > Debug Timing…' showcased SE (scan enable
input) as a predominant startpoint for violations.

Q2- Note the delay caused by wire length and clock buffer
 4381.27 ns

Q3- Note Type, Slack, Start and End.

Type: Hold Check

Slack: 0.1340

Start: Regs_reg[16][0] / CK

End: DEXB_reg[0] / D

Then alterations were made via Interactive ECO for SE pin, initially adding a BUFX20 cell. Despite insertion,
the delay remained insignificant. Additional BUFX20 cells (totaling three) were then added, resolving the
hold time issues associated with the SE input. To ensure automatic resolution during placement and
routing, commands for SE pin were inserted in the script. Rerunning the script fixed hold time violations
for the SE input. For the second path with the SE pin, Innovus inserted BUFX20 cells automatically.
Similarly, a pin was created for the scan_in input to resolve its hold time violations. Adding the command
'create_basic_path_groups -expanded' below 'init_design' and rerunning the script exhibited changes in
setup and hold time analyses.
 Lab 8: Innovus - IO File, Connectivity, Power Analysis, GDS

Introduction:

In this lab, we added the IO file to innovus layout and check its connectivity and ran power analysis and
Graphical Data Stream (GDS)

Description:

Copied the 'riscv_with_scan_chains_v3' folder using commands and navigated to the 'physical_design'
directory. Opened the 'innovus_script.tcl' file and executed it through the Innovus terminal. After the
script ran, performed a connectivity check by selecting 'Check > Check Connectivity...' from the Innovus
menu.

Q1- Write down the first of the warnings displayed by the connectivity check.

10 pin Instr [31] of net Instr [31] has not been assigned.

Then we added a command in script innovus_script.tcl.

Q2- Are there any errors?

No.

Then we did the power analysis.

Q3-What is the total internal power and its percentage to total power?

Internal Power=0.6435mW

Percentage=69.96%

Q4-What is the switching power and its percentage to total power?

 Switching Power=0.2795mW

Percentage=30%

Q5-What is the leakage power and its percentage to total power?

Leakage Power=0.00053mW

Percentage=0.038%

Q6-What is the total power consumed?

0.9235mW

Q7-What is the total capacitance?

15.3 pF

Then we did rail analysis.

Q8- What is the power density of our design?

Die Area = 166.55 x 166.55 = 27738.90 micro-meter-square

Q9- Are there any red areas displayed in the main Innovus window?

YES

Q10- What is the lowest voltage provided to any cell in the entire chip?

0.12986mV

Q11- Looking at the color plot, tell which color denotes the largest voltage drop. Which general
location in the chip has the largest voltage drop and why?
Red color shows the largest voltage drop.
 Lab 9: Gate-Level Simulation and Conformal Equivalence Checking

Introduction:

We did gate level simulation in this lab.

Description:

We copied the 'riscv_with_scan_chains_v4' folder and navigated to it. Inside the 'rtl' directory, we found
'mem.v' defining instruction and data memory modules. These modules were word-addressable with a
word size of 4 bytes and contain hard-coded instructions. In the 'simulation' directory, executed the initial
command in the makefile by using the command "make all".

Q1- Note the xrun command run here.

Xrun -timescale 1ns/1ps ../rtl/riscv.v ../rtl/mem.v ../rtl/riscv_tb.v -access +rwc -mess -gui

After closing SimVision, I used the "make restore" command, allowing the restoration of a previously
saved layout. Simulation revealed updates in specific memory addresses, following instructions from the
mem.v file, with a 1 ns delay post-clock edge. In the gate_level_simulation directory, changes in file names
were noted, and the SDF_TEST was defined in the makefile. Investigation into the SDF annotation, gate-
level simulation, and equivalence checking using Conformal was conducted. Finally, new scripts were
executed in the synthesis and physical_design directories, involving additional commands like add_tieoffs,
add_endcaps, add_welltaps, and add_fillers.

Q2- What is riscv_netlist.v?

It is a file containing IO port definitions, wire and module instantiations.

Q3-Note what the command is doing, including the meanings of its flags.

“../../synthesis/delays.sdf”, RISCVCPU_tb.my_cpu, “sdf.log”, “MAXIMUM”

Q4- Write down one sentence describing each of the four arguments i.e. a total of four
sentences.
 1 st parameter is an SDF file. 2 nd parameter is module instance.

3 rd parameter is log file.

4 th parameter is mtm_spec.

Q5- Zoom in and note this delay, in ps.

290ps

Q6- Write one sentence to describe each of the relevant Info/Warn/Error messages.

Warning: Library has no output pin defined.

Warning: Ignoring non-synthesizable (#) mentioned in Verilog file.

Info: An output library pin lacks a function attribute [LBR-41]. Output pin “HOLD X11Y” has no function.
Error: No errors