Chapter 4: Processor Fundamentals

Central Processing Unit Architecture

 Von Neumann model

o Von Neumann realized data & programs are indistinguishable and can therefore use
same memory.

o Von Neumann architecture uses a single processor.

o It follows a linear sequence of fetch–decode–execute operations for the set of

instructions i.e. the program.

o In order to do this, the processor uses registers.

 Registers: smallest unit of storage of microprocessor; allows fast data transfer between other
registers

 General Purpose registers

o Used to temporarily store data values which have been read from memory or some
processed result

o Can be used by assembly language instructions

 Special Purpose Registers

o Some are accessible by assembly language instructions

o Only holds either data or memory location, not both

o Special purpose registers include:

 Program Counter (PC): holds address of next instruction to be fetched

 Memory Data Register (MDR): holds data value fetched from memory

 Memory Address Register (MAR): Holds address of memory cell of program

which is to be accessed

 Accumulator (ACC): holds all values that are processed by arithmetic & logical
operations.

 Index Register (IX): Stores a number used to change an address value

 Current Instruction Register (CIR): Once program instruction fetched, it is stored

in CIR and allows the processor to decode & execute it

 Status Register: holds results of comparisons to decide later for action,

intermediate and erroneous results of arithmetic performed
 The Processor (CPU)

o Arithmetic and Logic Unit (ALU): part of processor that processes instructions which
require some form of arithmetic or logical operation

o Control Unit (CU): part of CPU that fetches instructions from memory, decodes them &
synchronizes operations before sending signals to computer’s memory, ALU and I/O
devices to direct how to respond to instructions sent to processor

o System Clock: timing device connected to processor that is needed to synchronize all
components.

 Buses
o set of parallel wires that allow the transfer data between components in a computer
system
o Data bus: bidirectional bus that carries data instructions between processor, memory,
and I/O devices.
o Address bus: unidirectional bus that carries address of main memory location or
input/output device about to be used, from processor to memory address register
(MAR)
o Control bus
 Bidirectional
 used to transmit control signals from control unit to ensure access/use of data &
address buses by components of system does not lead to conflict

 Performance of Computer System Factors

o Clock Speed

 number of pulses the clock sends out in a given time interval, which determines
the number of cycles (processes) the CPU executes in a given time interval

 usually measured in Gigahertz (GHz)

 If the clock speed is increased, then the execution time for instructions
decreases. Hence, more cycles per unit time, which increases performance.

 However, there is a limit on clock speed since the heat generated by higher
clock speeds cannot be removed fast enough, which leads to overheating.

o Bus Width

 Determines the number of bits that can be simultaneously transferred

  Refers to the number of lines in a bus

 Increasing bus width increases the number of bits transferred simultaneously,

increasing processing speed and performance.

o Cache Memory

 Commonly used instructions are stored in the cache memory area of the CPU.

 If the cache memory size is increased, more commonly executed instructions

can be stored, and the need for the CPU to wait for instructions to be loaded
reduces. Hence, the CPU executes more cycles per unit of time, thus improving
performance.

o Number of Cores

 Most CPU chips are multi-core — have more than one core (essentially a
processor)

 Each core simultaneously processes different instructions through

multithreading, improving computer performance.

 Ports

o Hardware which provides a physical interface between a device with CPU and a
peripheral device

o Peripheral (I/O) devices cannot be directly connected to the CPU, hence connected
through ports.

o Universal Serial Bus (USB): Can connect both input and output devices to the processor
through a USB port.

o High Definition Multimedia Interface (HDMI)

 Can only connect output devices (e.g. LCD) to the processor through a HDMI
port

 HDMI cables transmit high-bandwidth and high-resolution video & audio

streams through HDMI ports

o Video Graphics Array (VGA)

 Can only connect output devices (e.g. second monitor/display) to the processor
through a VGA port
  VGA ports allow only the transmission of video streams but not audio
components

 Fetch-Execute (F-E) cycle

o Fetch stage

 PC holds the address of the next instruction to be fetched

 The address on the PC is copied to MAR

 PC is incremented

 Instruction loaded to MDR from the address held in MAR

 Instruction from MDR loaded to CIR

o Decode stage: The opcode and operand parts of instruction are identified

o Execute stage: Instructions executed by the control unit sending control signals

o Register Transfer Notation (RTN)

 MAR ← [PC]

 PC ← [PC] + 1

 MDR ← [[MAR]]

 CIR ← [MDR]

 Decode

 Execute

 Return to start

 Square brackets: value currently in that register

 Double square brackets: CPU is getting value stored at the address in the
register

 Interrupts

o A signal from a program seeking the processor’s attention

 o Interrupt Service Routine (ISR):

 Handles the interrupt by controlling the processor

 Different ISRs used for different sources of interrupt

 A typical sequence of actions when an interrupt occurs:

o The processor checks the interrupt register for interrupt at the end of the F-E cycle for
the current instruction

o If the interrupt flag is set in the interrupt register, the interrupt source is detected

o If the interrupt is low priority, then an interrupt is disabled

o If interrupting is a high priority:

 All contents of registers of the running process are saved on the stack

 PC is loaded with the ISR and is executed

 Once ISR is completed, the processor restores the registers’ contents from the
stack, and the interrupted program continues its execution.

 Interrupts re-enabled and

 Return to the start of the cycle

Assembly Language

 Assembly language: low-level programming language with instructions made up of an op code

and an operand

 Machine code: code written in binary that uses the processor’s basic machine operations

 Relationship between machine and assembly language: every assembly language instruction
(source code) translates into exactly one machine code instruction (object code)

 Symbolic addressing

o Symbols used to represent operation codes

o Labels can be used for addresses

 Absolute addressing: a fixed address in memory

 Assembler

o Software that changes assembly language into machine code for the processor to
understand

o The assembler replaces all mnemonics and labels with their respective binary values
(that are predefined before by the assembler software)

 One pass assembler

o Assembler converts mnemonic source code into machine code in one sweep of program

o Cannot handle code that involves forward referencing

 Two pass assembler: software makes 2 passes thru code

o On the first pass:

 Symbol table created to enter symbolic addresses and labels into specific
addresses

 All errors are suppressed

o On the second pass:

 Jump instructions access memory addresses via table

 Whole source code translates into machine code

o Error reported if they exist

 Grouping the Processor’s Instruction Set

# is immediate addressing e.g. #5

B is a binary number, e.g. B01001010

& is a hexadecimal number, e.g. &4A

 Modes of Addressing

o Direct Addressing: loads contents at address into ACC

o Indirect Addressing: The address to be used is at given address. Load contents of this
second address to ACC
 o Indexed addressing: form the address to be used as

Address given in ACC + the contents of the IR (Index Register)

o Relative addressing: next instruction to be carried out is an offset number of locations

away, relative to address of current instruction held in PC; allows for relocatable code

Bit Manipulation

 Binary numbers can be multiplied or divided by shifting

 Left shift (LSL #n)

o Bits are shifted to the left to multiply

o E.g. to multiply by four, all digits shift two places to left

 Right shift (LSR #n)

o Bits are shifted to the right to divide

o E.g. to divide by four, all digits shift two places to right

 Logical shift: zeros replace the vacated bit position

 Arithmetic shift: Used to carry out multiplication and division of signed integers represented by
bits in the accumulator by ensuring that the sign-bit (usually the MSB) is the same after the shift.

 Cyclic shift: the bit that is removed from one end by the shift is added to the other end.

 Bit Masking

o Each bit can represent an individual flag.

o ∴ by altering the bits, flags could be operated upon.

o Bit manipulation operations:

 Masking: an operation that defines which bits you want to keep and which bits
you want to clear.

 Masking to 1: The OR operation is used with a 1.

 Masking to 0: The AND operation is used with a 0.

  Matching: an operation that allows the accumulator to compare the value it
contains to the given value in order to change the state of the status register.

 Practical applications of Bit Masking:

o Setting an individual bit position:

 Mask the content of the register with a mask pattern which has 0 in the ‘mask
out’ positions and 1 in the ‘retain’ positions.

 Set the result with the match pattern by using the AND command with a direct
address.

o Testing one or more bits:

 Mask the content of the register with a mask pattern which has 0 in the ‘mask
out’ positions and 1 in the ‘retain’ positions.

 Compare the result with the match pattern by using the CMP command or by
“Checking the pattern”.

o Checking the pattern

 Use AND operation to mask bits and obtain resultant.

 Now subtract matching bit pattern from resultant.

 The final ‘non-zero’ result confirms the patterns are not the same else vice
versa.