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VLSI Design KEC 072

Engineering Graphics & Design Lab (Dr. A.P.J. Abdul Kalam Technical University)

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Subject Code: KEC072
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B TECH.
(SEM VII) THEORY EXAMINATION 2021-22
VLSI DESIGN
Time: 3 Hours Total Marks: 100
Note: 1. Attempt all Sections. If require any missing data; then choose suitably.

SECTION A

1. Attempt all questions in brief. 2 x 10 = 20

Qno. Question Marks CO
a. What is Photolithography? 2 1
b. Why we need a low power VLSI circuits in today’s scenario? 2 1
c. What is contamination delay? 2 2
d. Define logical effect with example. 2 2
e. Differentiate between static power and dynamic power. 2 3
f. Implement 2:1 MUX using CMOS transmission gate. 2 3
g. Describe different storage elements. 2 4
h. Distinguish between SRAM and DRAM. 2 4
i. Explain the term controllability and observability. 2 5

1
90
j. What is meant by Stuck-at-1 fault and Stuck-at-0 fault? 2 5

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2.
SECTION B
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2. Attempt any three of the following:
2O

5.
Qno. Question Marks CO

.5
P2

a. Discuss the hierarchy of various semiconductors with Moore’s law. 10 1

17
Write short note on VLSI testing.
Q

|1

b. Explain Elmore delay model with suitable RC networks. Mention its 10 2

35

merits.
c. Compare the performance of Domino CMOS logic and NP Domino 10 3
3:
:5

CMOS logic with suitable example.

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d. Explain read/ Write operation of SRAM memory cell. How 1 bit cell is 10 4
used in bigger memory systems.
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02

e. Explain the issues involved in BIST techniques in details. 10 5

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SECTION C
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Ja

3. Attempt any one part of the following:

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Qno. Question Marks CO

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a. Draw the Y-chart and explain VLSI design process. Mention its 10 1
advantages.
b. Explain the CMOS fabrication steps with neat diagram using n-well 10 1
process.

4. Attempt any one part of the following:

Qno. Question Marks CO
a. Derive the expression for total power dissipation of a CMOS circuit. 10 2
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Subject Code: KEC072
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b. Draw and explain the working of RC delay model for interconnects. 10 2

5. Attempt any one part of the following:

Qno. Question Marks CO
a. Draw and explain NORA and TSPC dynamic CMOS logic. 10 3
b. What is pre-charge evaluate logic in dynamic CMOS logic and draw 10 3
the basic architecture of SRAM and DRAM.

6. Attempt any one part of the following:

Qno. Question Marks CO
a. Write short note on DRAM cell. Explain leakage and refresh operation 10 4
in DRAM cells.
b. Explain the various types of power dissipation in CMOS circuits. 10 4

7. Attempt any one part of the following:

Qno. Question Marks CO
a. Explain the parallel procession approach in low power CMOS circuits. 10 5

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90

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b. Write a short note on 10 5
_2

i. Adiabatic logic circuits

2.
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ii. Scan cell based approach.

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2O

5.
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P2

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35
3:
:5
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02
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Ja
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QP22O1P_290 | 04-Jan-2022 13:53:35 | 117.55.242.131
Downloaded by Dr. Himanshu Chhabra ([email protected])