Unit 2

A simple one-bit full adder

A B

Cout (+) Cin

It takes A, B, and Cin as input and generates S and Cout in 2 gate delays (SOP)
Ripple Carry Adder
• A ripple carry adder is a digital circuit that produces the
arithmetic sum of two binary numbers. It. can be constructed
with full adders connected in cascaded (see section 2.1), with
the carry output. from each full adder connected to the carry
input of the next full adder in the chain.
• Ripple Carry Adder is a combinational logic circuit.
• It is used for the purpose of adding two n-bit binary numbers.
• It requires n full adders in its circuit for adding two n-bit binary
numbers.
• It is also known as n-bit parallel adder.
• 4-bit ripple carry adder is used for the purpose of adding two 4-bit
binary numbers.
• In Mathematics, any two 4-bit binary numbers A3A2A1A0 and
B3B2B1B0 are added as shown below-
• Ripple Carry Adder works in different stages.
• Each full adder takes the carry-in as input and produces carry-out and
sum bit as output.
• The carry-out produced by a full adder serves as carry-in for its
adjacent most significant full adder.
• When carry-in becomes available to the full adder, it activates the full
adder.
• After full adder becomes activated, it comes into operation
• Working Of 4-bit Ripple Carry Adder-
•
• Let-
• The two 4-bit numbers are 0101 (A3A2A1A0) and 1010 (B3B2B1B0).
• These numbers are to be added using a 4-bit ripple carry adder.
• 4-bit Ripple Carry Adder carries out the addition as explained in the following stages-
• Stage-01:
•
• When Cin is fed as input to the full Adder A, it activates the full adder A.
• Then at full adder A, A0 = 1, B0 = 0, Cin = 0.
• Full adder A computes the sum bit and carry bit as-
•
RCA
• In Ripple Carry Adder,
• The carry out produced by each full adder serves as carry-in for its
adjacent most significant full adder.
• Each carry bit ripples or waves into the next stage.
• That’s why, it is called as “Ripple Carry Adder”.
• Disadvantages of Ripple Carry Adder-
•
• Ripple Carry Adder does not allow to use all the full adders
simultaneously.
• Each full adder has to necessarily wait until the carry bit becomes
available from its adjacent full adder.
• This increases the propagation time.
• Due to this reason, ripple carry adder becomes extremely slow.
• This is considered to be the biggest disadvantage of using ripple carry
adder.
FA
Observations
• The critical component each bit adder waits for is the carry input.
• Instead of generating and propagating carry bit-by-bit, can we
generate all of them in parallel and break the sequential chain?
• This is exactly the idea of CLA (carry look-ahead adder).
Carry Look Ahead Logic
• Now even before the carry in (Cin) is available, based on the inputs
(A,B) only, can we say anything about the carry out?
• Under what condition will the bit propagate an outgoing carry (Cout),
if there is an incoming carry (Cin)?
• Under what condition will the bit generate an outgoing carry (Cout),
regardless of whether there is an incoming carry (Cin)?
1-bit CLA adder
A B

S
(+) Cin

p g

• Instead of Cout, an 1-bit CLA adder block takes A, B inputs and generates p,g
• p=propagator =>I will propagate the Cin to the next bit. p = A+B
(If either A or B is 1, Cin=1 causes Cout=1)
• g=generator =>I will generate a Cout independent of what Cin is. g = AB
(If both A and B are 1, Cout=1 for sure)
• p,g are generated in 1 gate delay after we have A,B. Note that Cin is not needed
to generate p,g.
• S is generated in 2 gate delay after we get Cin (SOP).
4-bit CLA
A B A B A B A B

C3 C2
(+) (+) (+) C1
(+) C0

p g p g p g p g

CLL (carry look-ahead logic)

C4

• The CLL takes p,g from all 4 bits and C0 as input to generate all Cs in 2 gate delay.
• C1=g0+p0C0,
• C2=g1+p1g0+p1p0C0,
• C3=g2+p2g1+p2p1g0+p2p1p0c0,
• C4=g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 (Note: this C4 is too complicated
to generate in 2-level SOP representation)
4-bit CLA
A3 B3 A2 B2 A1 B1 A0 B0

C3 C2
S3
(+) S2
(+) S1
(+) C1
S0
(+) C0

p3 g3 p2 g2 p1 g1 p0 g0

CLL (carry look-ahead logic)

• Given A,B’s, all p,g’s are generated in 1 gate delay in parallel.

• Given all p,g’s, all C’s are generated in 2 gate delay in parallel.
• Given all C’s, all S’s are generated in 2 gate delay in parallel.
• Key virtue of CLA: sequential operation in RCA is broken into parallel operation!!
Observation
• The CLL block cannot be made too big (at most 4 bits) because if the
equations for C’s are too long it cannot be evaluated in 2 gate delay.
• So how about long operands, say 16 bits?
• We add another layer of CLL and make a multi-level CLA.
A bit more details
A3 B3 A2 B2 A1 B1 A0 B0

C3 C2
S3
(+) S2
(+) S1
(+) C1
S0
(+) C0

p3 g3 p2 g2 p1 g1 p0 g0

CLL (carry look-ahead logic)

C4

• Do all these 4 S’s (S3, S2, S1, S0) come together?

Actually no! Since C0 is available from the beginning, S0 can be calculated in
2 gate delays (using original SOP expression for S bit in a single bit adder)
(before S3,S2,S1)
• In ripple carry adders, the carry propagation time is the major speed limiting factor as seen in the previous
lesson.
•Most other arithmetic operations, e.g. multiplication and division are implemented
using several add/subtract steps. Thus, improving the speed of addition will improve
the speed of all other arithmetic operations.
•
•Accordingly, reducing the carry propagation delay of adders is of great importance.
Different logic design approaches have been employed to overcome the carry
propagation problem.
•
•One widely used approach employs the principle of carry look-ahead solves this
problem by calculating the carry signals in advance, based on the input signals.
•
•This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based
on the fact that a carry signal will be generated in two cases:
(1) when both bits Ai and Bi are 1, or

(2) when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

•
•Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi

•=1, regardless of the input carry (Ci).

•
•Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to the output
carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0).

•
•Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi) as clear from the Figure and
equations.
•
•Thus, these signals settle to their steady-state value after the propagation through their respective gates.
•
•Computed values of all the Pi’s are valid one XOR-gate delay after the operands A and B are made valid.
•
•Computed values of all the Gi’s are valid one AND-gate delay after the operands A and B are made valid.
•
• The Boolean expression of the carry outputs of various stages can be
written as follows:
• C1 = G0 + P0C0
• C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0)

• = G1 + P1G0 + P1P0C0

• C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3

• = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

•In general, the ith. carry output is expressed in the form Ci = Fi (P’s, G’s , C0).
•In other words, each carry signal is expressed as a direct SOP function of C0 rather than its preceding carry
signal.
•
•Since the Boolean expression for each output carry is expressed in SOP form, it can be implemented in
two-level circuits.
•
•The 2-level implementation of the carry signals has a propagation delay of 2 gates, i.e., 2 
Carry look ahead adder
•First level: Generates all the P & G signals. Four sets of P & G logic (each consists of an XOR gate and an
AND gate). Output signals of this level (P’s & G’s) will be valid after 1 .
•
•Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-level implementation logic
circuits. It generates the carry signals (C1, C2, C3, and C4) as defined by the above expressions. Output signals
of this level (C1, C2, C3, and C4) will be valid after 3 .
•
Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi Ci). Output signals of this level (S0,
S1, S2, and S3) will be valid after 4 .
•Thus, the 4 Sum signals (S0, S1, S2 & S3) will all be valid after a total delay of 4 compared to a delay of
(2n+1) for Ripple Carry adders.
•
•For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9 .
•
•The disadvantage of the CLA adders is that the carry expressions (and hence logic) become quite complex for
more than 4 bits.
•
•Thus, CLA adders are usually implemented as 4-bit modules that are used to build larger size adders.
•