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Lecture 4

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18 views

Lecture 4

Uploaded by

solomon
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© © All Rights Reserved
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Lecture 4: Karnaugh Maps, Timing Diagrams, Combinational-Circuit Building Blocks

I. Karnaugh Examples
A. f1 = m0 + m1 + m4 + m5 +m7 = (0, 1, 4, 5, 7) = 𝑥̅ 2 + x1x3
x1x2
00 01 11 10
0 1 0 0 1
x3
1 1 0 1 1

B. f2 = (6, 8, 9, 10, 11, 12, 13, 14) = x1𝑥̅ 3 + x1𝑥̅ 2 + x2x3𝑥̅ 4


x 1x 2
00 01 11 10
00 0 0 1 1
01 0 0 1 1
x 3x 4
11 0 0 0 1
10 0 1 1 1

C. Some companies may want to have special output that is set whenever an illegal input is seen.
II. Timing Diagrams are visual representations of truth tables at different parts of DLCs (digital logic circuits). Like a
truth table, the initial values of the inputs iterate through all of the possible combinations, and then the truth
values at later points in the circuit are shown based on each of those combinations.
A. Example using our DLC for XOR using only AND, OR, and NOT gates: A  B = A * ~B + ~A * B

III. Multiplexers select one output from multiple inputs. If a multiplexer has n data inputs, then it has |S| = ⌈log 2 𝑛⌉ select
inputs. There are n AND gates, with each having one data input, and |S| select inputs. The select inputs are all
true for only one AND gate at time. The one OR gate has n inputs from the AND gates.
A 2-to-1 Multiplexer
B. Multiplexers are used to control signal and data routing.
C. We can use a n-input MUX to implement any Boolean equation of log2(n) variables by feeding the variables to the
select inputs, and setting the data inputs to the expected values for the equation.
1. For the following 4-to1 MUX, what are the constant voltages (high = true, low = false) applied to the four Data
inputs to implement XOR based the select inputs?

IV. Decoders s are combinational circuits that convert binary information from n input lines to a maximum of 2n unique
output lines.
D. For many designs, only one output is asserted at a time, which is called one-hot encoded. This type is extremely
important in memory circuits, since you give an address that is encoded and one of the spots in the memory
has to be selected. Most kinds of random-access memory use a n-to-2n decoder to convert the selected
address on the address bus to one of the row address select lines.

E. An additional input that is attached to all of the AND gates can be used in two ways.
1. If data is fed to that input, then the decoder can be used a s demultiplexer that guides the data to a specific
output, i.e. a 2n-to-1 demultiplexer.
2. If the additional input line is thought of as a separate enabling input, then it is a way to turn the decoder on or
off.
V. Adder = a digital circuit that adds two numbers.
F. Half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).

G. Full adder adds binary numbers and accounts for values carried in as well as out. Notice that the longest path (A to
Cout) goes through three gates. This will be involved in determining the clock speed.
H. Two types of multiple-bit adders.
1. Ripple-carry adder = an adder in which each full adder uses Cout of the previous bit as its Cin. This causes a
delay as the signal propagates through the gates of each full adder.

2. Carry-lookahead adder = They work by creating two signals (p and g) for each bit position, based on if a carry is
propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit
position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, p is
simply the sum output of a half-adder and g is the carry output of the same adder. After p and g are generated
the carries for every bit position are created. (Wikipedia) This permits the adders to work simultaneously.
3. ci+1 = gi + pici, where gi = xiyi, and pi = xi  yi.
a. Thus ci+1 = gi + pgi-1 + pipi-1gi-2 +…+ pipi-1…p2p1g0 + pipi-1…p1p0c0. This expression represents a two-level
AND-OR circuit in which ci+1 is evaluated very quickly.

This is design easily adapts to negative numbers if they are represented in 2’s complement form with the addition of a
MUX and an inverter. Noting that A – B = A + (-B), and –B = ~B + 1.

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