Physical Design of CMOS Integrated

Circuits

Dae Hyun Kim

EECS
Washington State University
References
• John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002.
– Chapter 5
Goal
• Understand how to physically design (manually draw) CMOS
integrated circuits (ICs)
Custom Design Flow
Design specification An inverter (spec: width, height, ...)

Schematic design
𝑥𝑥 𝑓𝑓 = 𝑥𝑥̅
(Transistor-level netlist)

Layout (physical) design

DRC (Design Rule Check)

LVS (Layout vs. Schematic)

RC extraction SPICE-level netlist

Characterization Timing/power info.

Library
Schematic Editor
• Cadence Virtuoso

Source: https://www.semiwiki.com/forum/attachments/content/attachments/
4467d1343409050-schematic-jpg?s=a9af157432886096c1b713b17c65f4be
Layout Editor
• Cadence Virtuoso

Source: https://www.cadence.com/content/dam/cadence-www/global/en_US/diagrams/
tools/custom-ic-analog-rf-design/virtuoso-zambebi-xl-600px.jpg/_jcr_content/renditions/original.img.png
Layout Design
• Draw polygons (rectilinear objects) in each layer
– Rectangles
– Paths
• Layers (Real)
– n-well
– p-well
– Active (n+ = ndiff) +
– Active (p+ = pdiff) +
– Poly
– Contact
– Metal (m1, m2, m3, ...) Metal 1
– Via (v12, v23, v34, ...)
• Layers (Virtual)
– Cell boundary
– Labels VDD, VSS, A, Z
– Pins
Inverter
Substrate contact

M3

M2

M1

p+ n+ n+ p+ p+ n+
n-well
p-epi

substrate

Substrate contact
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Poly
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Implant
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Active
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Contact
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Metal 1
Design Rules
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
• Via12
Layouts
• INV_X1, INV_X2, INV_X4, INV_X8
Layouts
• INV_X8, INV_X16, INV_X32
Layouts
• NAND2_X1, NOR2_X1
Layouts
• BUF_X1, BUF_X2, BUF_X4
Layouts
• AND2_X1, AND3_X1, AND4_X1
Layouts
• XOR2_X1, XNOR2_X1
Layouts
• MUX2_X1
Layouts
• FA_X1 (Full adder)
Layouts
• DFF_X1 (D F/F)
Transistor Folding (A Layout Technique)
• INV_X16
Layout Generation
• Draw a layout.
– Output: GDSII format
• Design rule check (DRC)
• Prepare a schematic (netlist).
– A text file
• Layout vs. Schematic (LVS)
– Layout → netlist 1
– Schematic → netlist 2
– LVS checks whether netlist 1 is equal to netlist 2.
• Parasitic RC extraction
– Output: A SPICE netlist with parasitic RC
• Timing/power simulation and characterization
Channel Length and Width
• 𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒 = 𝐿𝐿 − ∆𝐿𝐿
– 𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒 : effective channel length
– 𝐿𝐿: drawn channel length
• 𝑊𝑊𝑒𝑒𝑒𝑒𝑒𝑒 = 𝑊𝑊 − ∆𝑊𝑊

Poly 𝐿𝐿

G
𝑊𝑊
(Drawn) n+ n+

𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒 𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒 p

𝐿𝐿
(Drawn)
Terminologies
• Twin-tub technology
– Two separate wells are created.
• n-well for pFETs
• p-well for nFETs
• Latch-up

Source: http://vlsi-soc.blogspot.com/2014/10/latch-up-in-cmos.html
Digital VLSI Design
• Placement
– Places transistors in a layout.
• Routing
– Power/Ground
• Connect all the 𝑉𝑉𝐷𝐷𝐷𝐷 lines to 𝑉𝑉𝐷𝐷𝐷𝐷 .
• Connect all the 𝑉𝑉𝑆𝑆𝑆𝑆 lines to 𝑉𝑉𝑆𝑆𝑆𝑆 .
• Reduce IR drop.
– Clock
• Connect all the clock sinks to a main clock source pin.
• Achieve zero skew.
– Signal
Standard Cell-Based Digital VLSI Design
• Power/Ground routing
Die area (Layout)

I/O cells

Core area
Power (Outer ring)
Ground (Inner ring)
Metal 1
Metal 2

Gound

Power
Standard Cell-Based Digital VLSI Design

Via1
Standard Cell-Based Digital VLSI Design
• Standard cells
– have a fixed height.
– have different widths.
– have ports (input/output pins) generally in the Metal 1 layer.
– have some obstacles in the Metal 1 layer (for internal routing).

• Routing
– uses only metal and via layers (doesn’t use any other layers).
– routes the standard cell ports and primary I/O ports based on a given
netlist.
Standard Cell-Based Digital VLSI Design
• BUF_X1
VDD port

Cell boundary

Obstruction (M1)

A (input, M1)

Z (output, M1)

VSS port

Layout
Automatic Placement
Automatic Routing
FET Sizing
• Theory
𝑾𝑾
– 𝑰𝑰 ≈ 𝝁𝝁 ∙ 𝒄𝒄𝒐𝒐𝒐𝒐 ∙ ∙ (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 ) ∙ 𝑽𝑽𝑫𝑫𝑫𝑫
𝑳𝑳
𝟏𝟏 𝑳𝑳
– 𝑹𝑹 = ∝
𝜷𝜷∙(𝑽𝑽𝑮𝑮 −𝑽𝑽𝑻𝑻 ) 𝑾𝑾
• Motivation 1
– pFETs and nFETs have different mobility values.
• 𝜇𝜇𝑛𝑛 > 𝜇𝜇𝑝𝑝
– Thus, if an nFET and a pFET networks have the same transistor sizes, their
delay values are different.
• Motivation 2
– Minimum-size FETs might not provide enough drive strength.
• Goal
– Achieve perfectly-balanced delay values (from Motivation 1).
– Satisfy delay constraints (from Motivation 2).
• Mobility ratio
– 𝝁𝝁𝒏𝒏 = 𝒓𝒓 ∙ 𝝁𝝁𝒑𝒑 (𝒓𝒓 > 𝟏𝟏)
– 𝑹𝑹𝒑𝒑 = 𝒓𝒓 ∙ 𝑹𝑹𝒏𝒏
FET Sizing
• Theory
𝑾𝑾
– 𝑰𝑰 ≈ 𝝁𝝁 ∙ 𝒄𝒄𝒐𝒐𝒐𝒐 ∙ ∙ (𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻 ) ∙ 𝑽𝑽𝑫𝑫𝑫𝑫
𝑳𝑳
𝟏𝟏 𝑳𝑳
– 𝑹𝑹 = ∝
𝜷𝜷∙(𝑽𝑽𝑮𝑮 −𝑽𝑽𝑻𝑻 ) 𝑾𝑾
– The drive strength (current) is
• proportional to 𝑊𝑊
• inversely proportional to 𝐿𝐿
– The input capacitance is proportional to 𝐿𝐿 and 𝑊𝑊.
– If 𝐿𝐿 increases
• The input capacitance goes up.
• The drive strength goes down (or the output resistance goes up).
• The cell area goes up.
• Thus, do not increase 𝐿𝐿 (i.e., use the minimum channel length).
– If 𝑊𝑊 increases
• The input capacitance goes up.
• The drive strength goes up (or the output resistance goes down).
• The cell area goes up.
• If the input capacitance overhead is small, upsizing FETs reduces the delay of the
downstream net.
FET Sizing
• Theory
– The FET width cannot be reduced infinitely (design rules).
– Suppose the minimum transistor length and width are 𝐿𝐿0 and 𝑊𝑊0 ,
respectively.
– Then,
𝑊𝑊0
• Minimum-size nFET = : This is a 1X nFET.
𝐿𝐿0 𝑛𝑛
– Resistance: 𝑅𝑅𝑛𝑛
𝑊𝑊0
• Minimum-size pFET = : This is a 1X pFET.
𝐿𝐿0 𝑝𝑝
– Resistance: 𝑅𝑅𝑝𝑝
• Transistor upsizing
𝑘𝑘∙𝑊𝑊0
– If the size of an nFET is 𝐿𝐿0 𝑛𝑛
, it is a 𝑘𝑘X nFET.
𝑅𝑅𝑛𝑛
• Resistance:
𝑘𝑘
𝑘𝑘∙𝑊𝑊0
– If the size of a pFET is , it is a 𝑘𝑘X pFET.
𝐿𝐿0 𝑝𝑝
𝑅𝑅𝑝𝑝
• Resistance:
𝑘𝑘
FET Sizing (Matching)
• Example: Inverter
– 𝜇𝜇𝑛𝑛 = 𝟐𝟐 ∙ 𝜇𝜇𝑝𝑝 (i.e., 𝑅𝑅𝑝𝑝 = 2𝑅𝑅𝑛𝑛 )

1X 𝑅𝑅 = 𝑅𝑅𝑝𝑝 = 2𝑅𝑅𝑛𝑛
𝑉𝑉𝑖𝑖𝑖𝑖 = 1 𝑉𝑉𝑖𝑖𝑖𝑖 = 0
𝑉𝑉𝑖𝑖𝑖𝑖
1X 𝐶𝐶 𝑅𝑅 = 𝑅𝑅𝑛𝑛 𝐶𝐶 𝐶𝐶

Time constant 𝜏𝜏 = 𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶 𝜏𝜏 = 2𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶

𝑅𝑅𝑝𝑝
2X 𝑅𝑅 = = 𝑅𝑅𝑛𝑛
𝑉𝑉𝑖𝑖𝑖𝑖 = 1 𝑉𝑉𝑖𝑖𝑖𝑖 = 0 2
𝑉𝑉𝑖𝑖𝑖𝑖
1X 𝐶𝐶 𝑅𝑅 = 𝑅𝑅𝑛𝑛 𝐶𝐶 𝐶𝐶

Minimum-size inverter 𝜏𝜏 = 𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶 𝜏𝜏 = 𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶

FET Sizing (Delay Reduction)
• Example: Inverter
– 𝜇𝜇𝑛𝑛 = 𝟐𝟐 ∙ 𝜇𝜇𝑝𝑝 (i.e., 𝑅𝑅𝑝𝑝 = 2𝑅𝑅𝑛𝑛 )

𝑅𝑅𝑝𝑝
2X 𝑅𝑅 = = 𝑅𝑅𝑛𝑛
𝑉𝑉𝑖𝑖𝑖𝑖 = 1 𝑉𝑉𝑖𝑖𝑖𝑖 = 0 2
𝑉𝑉𝑖𝑖𝑖𝑖
1X 𝐶𝐶 𝑅𝑅 = 𝑅𝑅𝑛𝑛 𝐶𝐶 𝐶𝐶

1X inverter 𝜏𝜏 = 𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶 𝜏𝜏 = 𝑅𝑅𝑛𝑛 ∙ 𝐶𝐶

𝑅𝑅𝑝𝑝 𝑅𝑅𝑛𝑛
4X 𝑅𝑅 = =
𝑉𝑉𝑖𝑖𝑖𝑖 = 1 𝑉𝑉𝑖𝑖𝑖𝑖 = 0 4 2
𝑉𝑉𝑖𝑖𝑖𝑖
2X 𝐶𝐶 𝑅𝑅𝑛𝑛 𝐶𝐶 𝐶𝐶
𝑅𝑅 =
2

2X inverter 𝑅𝑅𝑛𝑛 𝑅𝑅𝑛𝑛

𝜏𝜏 = ∙ 𝐶𝐶 𝜏𝜏 = ∙ 𝐶𝐶
2 2
FET Sizing
• NAND2_X1, NOR2_X1

𝑎𝑎 2X 𝑏𝑏 2X 𝑎𝑎 4X

𝑎𝑎 2X 𝑏𝑏 4X

𝑏𝑏 2X 𝑎𝑎 1X 𝑏𝑏 1X

FETs are sized for the worst-case signal path.

FET Sizing
• 𝑓𝑓 = 𝑎𝑎 + 𝑏𝑏 ∙ 𝑐𝑐 (1X)

𝑏𝑏 4X 𝑐𝑐 4X

𝑎𝑎 4X

𝑏𝑏 2X
𝑎𝑎 1X
𝑐𝑐 2X
FET Sizing – Analytical Approach
• NAND2_X1
– pFETs: Each should be 2X.
– nFETs
• If 𝑎𝑎 is upsized to 𝑥𝑥1 X and 𝑏𝑏 is upsized to 𝑥𝑥2 X (𝑥𝑥1 , 𝑥𝑥2 > 1)
𝑅𝑅𝑛𝑛
– Resistance of 𝑎𝑎:
𝑥𝑥1
𝑅𝑅𝑛𝑛
– Resistance of 𝑏𝑏:
𝑥𝑥2
𝑎𝑎 2X 𝑏𝑏 2X
• The total resistance should be 𝑅𝑅𝑛𝑛 .
𝑅𝑅𝑛𝑛 𝑅𝑅𝑛𝑛 1 1
–
𝑥𝑥1
+
𝑥𝑥2
= 𝑅𝑅𝑛𝑛 ⇒
𝑥𝑥1
+
𝑥𝑥2
=1 𝑎𝑎 𝑥𝑥1 X
3 4
• For instance, 𝑥𝑥1 , 𝑥𝑥2 = 2,2 , 3, , 4, ,…
2 3 𝑏𝑏 𝑥𝑥2 X
• We want to minimize the total area.
– Min. 𝑥𝑥1 + 𝑥𝑥2
FET Sizing – Analytical Approach
• Problem
– Minimize 𝑓𝑓 𝑥𝑥1 , 𝑥𝑥2 = 𝑥𝑥1 + 𝑥𝑥2 under the following constraints.
• 𝑥𝑥1 , 𝑥𝑥2 > 1
1 1
• + =1
𝑥𝑥1 𝑥𝑥2

– Solve
1 1 𝑥𝑥1
• + = 1 ⇒ 𝑥𝑥2 =
𝑥𝑥1 𝑥𝑥2 𝑥𝑥1 −1
𝑥𝑥1 𝑥𝑥1 2
• 𝑓𝑓 𝑥𝑥1 , 𝑥𝑥2 = 𝑥𝑥1 + 𝑥𝑥2 = 𝑥𝑥1 + = 𝑓𝑓 𝑥𝑥1 =
𝑥𝑥1 −1 𝑥𝑥1 −1

′ 2𝑥𝑥1 𝑥𝑥1 −1 −𝑥𝑥1 2 𝑥𝑥1 2 −2𝑥𝑥1

• 𝑓𝑓 𝑥𝑥1 = =
(𝑥𝑥1 −1)2 (𝑥𝑥1 −1)2
• Thus, 𝑓𝑓 is minimized when 𝑥𝑥1 = 2. In this case, 𝑥𝑥2 is also 2.
FET Sizing – Analytical Approach
• NAND_X𝑛𝑛 (𝑛𝑛-input NAND gate)
– pFETs: Each should be 2X.
– nFETs
• If 𝑎𝑎𝑖𝑖 is upsized to 𝑥𝑥𝑖𝑖 X (𝑥𝑥𝑖𝑖 > 1)
– Resistance of 𝑎𝑎𝑖𝑖 :
𝑅𝑅𝑛𝑛 𝑎𝑎1 2X 𝑎𝑎2 2X … 𝑎𝑎𝑛𝑛 2X
𝑥𝑥𝑖𝑖

• The total resistance should be 𝑅𝑅𝑛𝑛 .

– ∑𝑛𝑛𝑖𝑖=1
𝑅𝑅𝑛𝑛
= 𝑅𝑅𝑛𝑛 ⇒
1
+
1
+ ⋯+
1
=1
𝑎𝑎1 𝑥𝑥1 X
𝑥𝑥𝑖𝑖 𝑥𝑥1 𝑥𝑥2 𝑥𝑥𝑛𝑛

• We want to minimize the total area.

𝑎𝑎2 𝑥𝑥2 X
– Min. ∑𝑛𝑛𝑖𝑖=1 𝑥𝑥𝑖𝑖 = 𝑥𝑥1 + 𝑥𝑥2 + ⋯ + 𝑥𝑥𝑛𝑛

…
𝑎𝑎𝑛𝑛 𝑥𝑥𝑛𝑛 X
FET Sizing – Analytical Approach
• Problem
– Minimize 𝑓𝑓 𝑥𝑥1 , 𝑥𝑥2 , … , 𝑥𝑥𝑛𝑛 = 𝑥𝑥1 + 𝑥𝑥2 + ⋯ + 𝑥𝑥𝑛𝑛 under the following constraints.
• 𝑥𝑥𝑖𝑖 > 1
1 1 1
• + + ⋯+ =1
𝑥𝑥1 𝑥𝑥2 𝑥𝑥𝑛𝑛
– Solve
1
• Let = 𝑦𝑦𝑖𝑖 . Then, the problem becomes as follows:
𝑥𝑥𝑖𝑖
1 1
– Minimize 𝑓𝑓 𝑦𝑦1 , … , 𝑦𝑦𝑛𝑛 = 𝑦𝑦 + ⋯ + 𝑦𝑦
1 𝑛𝑛
– 𝑦𝑦𝑖𝑖 < 1
– 𝑦𝑦1 + ⋯ 𝑦𝑦𝑛𝑛 = 1
• 𝑦𝑦𝑛𝑛 = 1 − (𝑦𝑦1 + ⋯ + 𝑦𝑦𝑛𝑛−1 )
1 1 1 1 1
• 𝑓𝑓 𝑦𝑦1 , … , 𝑦𝑦𝑛𝑛 = + ⋯+ = 𝑓𝑓 𝑦𝑦1 , … , 𝑦𝑦𝑛𝑛−1 = + ⋯+ +
𝑦𝑦1 𝑦𝑦𝑛𝑛 𝑦𝑦1 𝑦𝑦𝑛𝑛−1 1−(𝑦𝑦1 +⋯+𝑦𝑦𝑛𝑛−1 )
𝜕𝜕𝑓𝑓 𝜕𝜕𝜕𝜕
• Solve = 0, … , = 0.
𝜕𝜕𝑦𝑦1 𝜕𝜕𝑦𝑦𝑛𝑛−1
𝜕𝜕𝜕𝜕 1 1
• =− + 2 =0
𝜕𝜕𝑦𝑦𝑖𝑖 𝑦𝑦𝑖𝑖 2 1− 𝑦𝑦1 +⋯+𝑦𝑦𝑛𝑛−1
– 𝑦𝑦𝑖𝑖 = 1 − (𝑦𝑦1 + ⋯ + 𝑦𝑦𝑛𝑛−1 ) ⇒ 𝑦𝑦𝑖𝑖 = 𝑦𝑦𝑛𝑛
• Thus, 𝑓𝑓 is minimized when 𝑦𝑦1 = 𝑦𝑦2 = ⋯ = 𝑦𝑦𝑛𝑛 , i.e., 𝑥𝑥1 = 𝑥𝑥2 = ⋯ = 𝑥𝑥𝑛𝑛 .
• As a result, 𝑥𝑥1 = 𝑥𝑥2 = ⋯ = 𝑥𝑥𝑛𝑛 = 𝑛𝑛.