Chapter 5

Input/Output Organization
 Outline
Accessing I / O Devices
Interrupts
Direct Memory Access
Buses
Interface Circuits
Standard I / O Interfaces

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 Content Coverage
Main Memory System

Address Data/Instruction

Central Processing Unit (CPU)

Operational
Registers Instruction
Cache Arithm Sets
memory etic
and
Logic Unit
Program
Counter

Control Unit

Input/Output System

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 Accessing I/O Devices
Single-bus structure
◆ The bus enables all the devices connected to it to
exchange information
◆ Typically, the bus consists of three sets of lines used to
carry address, data, and control signals
◆ Each I / O device is assigned a unique set of addresses

Processor Memory

Bus

I/O device 1 I/O device n

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1.Single-bus Structure:
1. In computer architecture, a bus is a
communication system that transfers data
between components such as the CPU,
memory, and I/O devices.
2. A single-bus structure refers to a system
where all components share a common bus for
communication.
2.Bus Functionality:
1. The bus serves as a communication pathway,
enabling devices connected to it to exchange
information.
2. This communication involves the transfer of
data, addresses, and control signals.
3. Three Sets of Lines:
1. Typically, a bus consists of three sets of lines:
1. Address Lines: These lines carry information about the
location in memory or I/O space that the data should be read
from or written to.
2. Data Lines: These lines carry the actual data being
transferred between the devices.
3. Control Lines: These lines carry signals that control the
operation of the bus, indicating actions such as read, write, or
interrupt.
4. Unique Set of Addresses for I/O Devices:
2. In a computer system, each I/O device is assigned a unique set
of addresses.
3. These addresses are used to identify and communicate with
specific I/O devices on the bus.
4. When the CPU wants to communicate with a particular I/O
device, it sends the device's address on the address lines of the
bus.
In a single-bus structure, the bus facilitates
communication between the CPU, memory, and
I/O devices. The address lines help identify
specific devices, the data lines transfer the actual
information, and the control lines manage the
overall operation of the bus. This organization
allows for a structured and efficient exchange of
information within the computer system.
 I/O Mapping
There are two different approaches of mapping input/output
(I/O) devices in a computer system: Memory-mapped I/O and
Isolated I/O.
Memory mapped I / O
◆ Devices and memory share an address space
◆ I / O looks just like memory read / write
◆ No special commands for I/ O
□ Large selection of memory access commands available
Isolated I / O
◆ Separate address spaces
◆ Need I / O or memory select lines
◆ Special commands for I /O
□ Limited set
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• In summary, the main distinction lies in how the CPU communicates

with I/O devices.

• Memory-mapped I/O integrates I/O devices into the regular memory

address space, making I/O operations resemble memory operations.

• In isolated I/O, memory and I/O have separate address spaces, and

special commands are used for I/O operations, requiring additional

select lines to differentiate between memory and I/O transactions.

• The choice between these approaches depends on factors like

system design goals, complexity, and performance considerations.

 Memory-Mapped I/O
When I / O devices and the memory share the same
address space, the arrangement is called memory-
mapped I / O
With memory-mapped I / O, any machine instruction that can
access memory can be used to transfer data to or from an I / O
device
Most computer systems use memory-mapped I / O.
Some processors have special IN and OUT instructions to
perform I / O transfers
◆ When building a computer system based on these processors, the
designer has the option of connecting I / O devices to use the special I
/ O address space or simply incorporating them as part of the memory
address space

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Memory-Mapped I/O:
1. Shared Address Space:
In memory-mapped I/O, devices and memory share a common address space.
This means that I/O devices are assigned addresses in the same address
range as regular memory locations.
2. I/O Resembles Memory Operations:
I/O operations (read/write) are performed using the same instructions as
memory operations. From the CPU's perspective, reading from or writing to an
I/O device looks similar to reading from or writing to memory.
3. No Special Commands:
There are no special commands or instructions dedicated solely to I/O
operations. The CPU uses regular memory read and write instructions for both
memory and I/O.
4. Extensive Memory Access Commands:
Since I/O and memory share the same address space, the CPU can use the
full range of memory access commands for both I/O and memory operations.
The I/O interface for an input device involves a combination of
hardware components, including an address decoder to interpret
addresses, data and status registers for data exchange and status
information, and control circuitry to coordinate the flow of
information.
This interface is crucial for enabling effective communication
and control between the CPU and the input device in the context
of I/O operations.
 I/O Interface for an Input
Device
The address decoder, the data and status registers,
and the control circuitry required to coordinate
I / O transfers constitute the device’s interface
circuit Address
lines Data
Bus
lines Control
lines

Addres Control Data and status

s circuits registers
decoder

Input device

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 I/O Techniques
Programmed

Interrupt driven

Direct Memory Access (DMA)

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 Program-Controlled I/O
Consider a simple example of I / O operations involving a
keyboard and a display device in a computer system. The
four registers shown below are used in the data transfer
operations
◆ The two flags KIRQ(Keyboard Interrupt Request) and DIRQ in
STATUS register are used in conjunction with interrupts

DATAIN

DATAOU
T
STATU
DIRQ KIRQ SOUT SIN

S
DEN KEN

CONTROL 7 6 5 4 3 2 1 0
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 An Example
A program that reads one line from thekeyboard,
stores it in memory buffer, and echoes it back to the
display
Move #LINE, R0 Initialize memory pointer
WAITK TestBit #0,STATUS Test SIN
Branch=0 WAITK Wait for character to be entered
Move DATAIN,R1 Read character
WAITD TestBit #1,STATUS Test SOUT
Branch=0 WAITD Wait for display to become ready
Move R1,DATAOUT Send character to display
Move R1,(R0)+ Store character and advance pointer
Compare #$0D,R1 Check if Carriage Return
Branch=0 WAITK If not, get another character
Move #$0A,DATAOUT Otherwise, send Line Feed
Call PROCESS Call a subroutine to process the
input line

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 Program-Controlled I/O
The example described above illustrates program-
controlled I / O, in which the processor repeatedly
checks a status flag to achieve the required
synchronization between the processor and an input or
output device. We say that the processor polls the
devices
There are two other commonly used mechanisms for
implementing I / O operations: interrupts and direct
memory access
◆ Interrupts: Synchronization is achieved by having the I / O
device send a special signal over the bus whenever it is ready
for a data transfer operation
◆ Direct memory access: It involves having the device
interface transfer data directly to or from the memory
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 Interrupts
To avoid the processor being not performing any
useful computation, a hardware signal called an
interrupt to the processor can do it. At least one of
the bus control lines, called an interrupt-request line,
is usually dedicated for this purpose
An interrupt-service routine usually is needed and is
executed when an interrupt request is issued
On the other hand, the processor must inform the
device that its request has been recognized so that it
may remove its interrupt-request signal. An
interrupt-acknowledge signal serves this function.

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 Example

Program 1 Program 2
COMPUTE PRINT
routine routine

1
2

Interrupt i
occurs
here i+1

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Interrupt-Service Routine & Subroutine
Treatment of an interrupt-service routine is very
similar to that of a subroutine
An important departure from the similarity should be
noted
◆ A subroutine performs a function required by the program
from which it is called.
◆ The interrupt-service routine may not have anything in
common with the program being executed at the time the
interrupt request is received. In fact, the two programs often
belong to different users
Before executing the interrupt-service routine, any
information that may be altered during the execution of
that routine must be saved. This information must be
restored before the interrupted program is resumed
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Interrupt Latency: Interrupt Latency
1. Definition: Interrupt latency is the delay between when a device
sends an interrupt request and when the processor actually starts
running the code to handle that interrupt.
2. Cause: One reason for this delay is the time it takes to save and
restore important information when an interrupt occurs.
Information Saved and Restored:
1. What is saved: When an interrupt happens, certain critical
information is saved to ensure that the interrupted program can
resume correctly later.
2. Typically saved: This often includes things like flags that represent
the condition of the processor and the contents of registers used by
both the interrupted program and the interrupt-service routine (the
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3. Delay and Saving Registers:
1. Why delay occurs: The process of saving these registers adds a
delay between the time the interrupt is triggered and the start of
the interrupt-service routine.
2. Interrupt Latency: This delay is what we call interrupt latency.
4. Processor's Default Saving:
3. What the processor saves by default: Usually, the processor
automatically saves only the program counter (which keeps track
of where the program is) and the processor status register (which
contains flags indicating the state of the processor).
4. Additional information: If there's other information that needs to
be saved, the program handling the interrupt must take care of it.
5. Saving and Restoring Additional Information:
1. How to handle more information: If there's extra information
that needs saving, the interrupt-service routine needs to have
instructions to do this. It saves what's necessary at the beginning
and restores it at the end to make sure everything continues
smoothly.
In essence, interrupt latency is the delay caused by the time it takes to
save and restore important information when an interrupt occurs. The
processor typically takes care of saving some basic information
automatically, but if more details need to be preserved, the
interrupt-service routine needs to handle that.
 Interrupt Hardware
An equivalent circuit for an open-drain bus used to
implement a common interrupt-request line
V
dd

Processor
R
INTR INTR

INTR1 INTR2 INTRn

INTR=INTR1+INTR2+…+INTRn

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 Handling MultipleDevices
Handling multiple devices gives rise to a number of
questions:
◆ How can the processor recognize the device requesting an
interrupt?
◆ Given that different devices are likely to require different
interrupt-service routines, how can the processor obtain the
starting address of the appropriate routine in each case?
◆ Should a device be allowed to interrupt the processor while
another interrupt is being serviced?
◆ How should two or more simultaneous interrupt request be
handled?
The information needed to determine whether a
device is requesting an interrupt is available in its
status register
◆ When a device raises an interrupt request, it sets to 1 one of 25
 Identify the Interrupting Device
The simplest way to identify the interrupting device is
to have the interrupt-service routine poll all the
I / O devices connected to the bus
◆ The polling scheme is easy to implement. Its main
disadvantage is the time spent interrogating all the devices
A device requesting an interrupt may identify itself
directly to the processor. Then, the processor can
immediately start executing the corresponding
interrupt-service routine. This is called vectored
interrupts
An interrupt request from a high-priority device
should be accepted while the processor is servicing
another request from a lower-priority device
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 Interrupt Priority
The processor’s priority is usually encoded in a few bits of
the processor status word. It can be changed by program
instructions that write into the program status register (PS).
These are privileged instructions, which can be executed only
while the processor is running in the supervisor mode
The processor is in the supervisor mode only when
executing operating system routines. It switches to the
user mode before beginning to execute application program
An attempt to execute a privileged instruction while in the
user mode leads to a special type of interrupt called a
privilege exception

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Implementation of Interrupt Priority
An example of the implementation of a multiple-
priority scheme

INTR1 INTRp

Device Device 2 Device p

Processo

1
INTA1
INTAp
r

Priority
arbitration
circuit

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 Simultaneous Requests
Consider the problem of simultaneous arrivals of
interrupt requests from two or more devices. The
processor must have some means of deciding
which request to service first
Interrupt priority scheme with daisy chain

INTR
Processo

Device 1 Device 2 Device n

r

INT
A

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 Priority Group
Combination of the interrupt priority scheme with
daisy chain and with individual interrupt- request
and interrupt-acknowledge lines
INTR1

Device Device Device

INTA1
Processo

INTRp
r

Device Device Device

INTAp

Priority
arbitration
circuit 30
 Direct Memory Access
To transfer large blocks of data at high speed, a
special control unit may be provided between an
external device and the main memory, without
continuous intervention by the processor. This
approach is called direct memory access (DMA)
DMA transfers are performed by a control circuit that is
part of the I / O device interface. We refer to this circuit
as a DMA controller.
Since it has to transfer blocks of data, theDMA
controller must increment the memory address for
successive words and keep track of the number
of transfers
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 DMA Controller
Although a DMA controller can transfer data
without intervention by the processor, its operation
must be under the control of a program executed
by theprocessor
An example
31 30 1 0
Status and control
IRQ
IE Done
R/W

Starting address

Word count

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DMA Controller in a Computer System

Main
Processor memory

System bus

Disk/DMA DMA Printer Keyboar

controller controller d

Disk Network
Disk
Interface

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 Memory Access Priority
Memory accesses by the processor and the DMA
controllers are interwoven. Request by DMA devices
for using the bus are always given higherpriority than
processor requests.
Among different DMA devices, top priority is given to
high-speed peripherals such as a disk, a high- speed
network interface, etc.
Since the processor originates most memory access
cycles, the DMA controller can be said to “steal”
memory cycles from the processor. Hence, this
interweaving technique is usually called cycle stealing
The DMA controller may transfer a block of data
without interruption. This is called block/burst mode
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 Bus Arbitration
A conflict may arise if both the processor and a DMA
controller or two DMA controllers try to use the bus at
the same time to access the main memory. To resolve
this problem, an arbitration procedure on bus is needed
The device that is allowed to initiate data transfer on
the bus at any given time is called the bus master. When
the current master relinquishes control of the bus,
another device can acquire this status
Bus arbitration is the process by which the next
device to become the bus master take into account
the needs of various devices by establishing a
priority system for gaining access to the bus

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 Bus Arbitration
There are two approaches to bus arbitration
◆ Centralized and distributed
In centralized arbitration, a single bus arbiter
performs the required arbitration
In distributed arbitration, all devices participate in
the selection of the next bus master

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 Centralized Arbitration
BBSY

Processo BR

DMA DMA
r

BG1 Controller 1 BG2 Controller 2

BR
BG1

BG2

BBSY

Processor DMA controller Processor

2
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 Buses
A bus protocol is the set of rules that govern the
behavior of various devices connected to the bus as
to when to place information on the bus, assert
control signals, and so on
In a synchronous bus, all devices derive timing
information from a common clock line. Equal
spaced pulses on this line define equal time
intervals
In the simplest form of a synchronous bus, each of
these intervals constitutes a bus cycle during
which one data transfer can take place

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 Interface Circuits
Keyboard to processor connection
◆ When a key is pressed, the Valid signal changes from 0 o 1,
causing the ASCII code to be loaded into DATAIN and SIN
to be set to 1
◆ The status flag SIN is cleared to 0 when the processor
reads the contents of the DATAIN register

Data

DATAIN Data
Address
Encoder
SIN Keyboar
Processor and
R/W Debouncing d
circuit switches
Master-ready Valid
Input
Slave-ready Interfac
e

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 Printer to Processor Connection
The interface contains a data register, DATAOUT,
and a status flag, SOUT
◆ The SOUT flag is set to 1 when the printer is ready to accept
another character, and it is cleared to 0 when a new character is
loaded into DATAOUT by the processor
◆ When the printer is ready to acce pt a character, it asserts its
idle signal
Data

DATAOUT Data
Address
SOUT
Processor R/W Printer
Valid
Master-ready
Output Idle
Slave-ready Interface

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 Serial Port
A serial port is used to connect the processorto
I / O devices that require transmission of data one
bit at a time
The key feature of an interface circuit for a serial
port is that it is capable of communicating in a
bit-serial fashion on the device side and in a bit-
parallel fashion on the bus side
The transformation between the parallel and serial
formats is achieved with shift registers that have
parallel access capability

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 A Serial Interface
Input shift register Serial input

DATAIN

D7

D0

DATAOUT

Output shift register Serial

output

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 Standard I/O Interfaces
The processor bus is the bus defined by the signals on the
processor chip itself. Devices that require a veryhigh speed
connection to the processor, such as the main memory, may
be connected directly to this bus
The motherboard usually provides another bus that can
support more devices.
The two buses are interconnected by a circuit, which we
called a bridge, that translates the signals and protocols of
one bus into those of the other
It is impossible to define a uniform standards for the
processor bus. The structure of this bus is closely tied to the
architecture of the processor
The expansion bus is not subject to these limitations, and
therefore it can use a standardized signaling structure
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Peripheral Component Interconnect Bus
Use of a PCI bus in a computer system

Host

PCI Main
bridge memor
y
PCI
Bus

Etherne
Disk Printer
t
interfac
e
44
 PCI Bus
The bus support three independent address spaces:
memory, I / O, and configuration.
The I / O address space is intended for use with
processors, such Pentium, that have a separate I / O
address space.
However, the system designer may choose to use
memory-mapped I / O even when a separate I / O
address space is available
The configuration space is intended to give the PCI its
plug-and-play capability.
◆ A 4-bit command that accompanies the address identifies
which of the three spaces is being used in a given data
transfer operation
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 Universal Serial Bus (USB)
The USB has been designed to meet several key
objectives
◆ Provide a simple, low-cost, and easy to use
interconnection system thatovercomes the difficulties due
to the limited number of I / O ports available on a
computer
◆ Accommodate a wide range of data transfer
characteristics for I / O devices, including telephone and
Internet connections
◆ Enhance user convenience through a “plug-and-play”
mode of operation

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 USB Structure
A serial transmission format has been chosen for the USB
because a serial bus satisfies the low-cost and flexibility
requirements
Clock and data information are encoded together and
transmitted as a single signal
◆ Hence, there are no limitations on clock frequency or distance
arising from data skew
To accommodate a large number of devices that can be
added or removed at any time, the USB has the tree
structure
◆Each node of the tree has a device called a hub, which acts as an
intermediate control point between the host and the I / O device
◆ At the root of the tree, a root hub connects the entire tree to the
host computer

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 USB Tree Structure
Host Computer

Root
hub

Hub Hub

I/O I/O I/O I/O

Hub device device device device

I/O I/O
device device

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 USB Tree Structure
The tree structure enables many devices to be connected
while using only simple point-to-point serial links
Each hub has a number of ports where devices may be
connected, including other hubs
In normal operation, a hub copies a message that it
receives from its upstream connection to all its
downstream ports
◆ As a result, a message sent by th e host computer is broadcast to all I /
O devices, but only the addresse d device will respond to that message
A message sent from an I / O de vice is sent only upstream
towards the root of the tree and is not seen byother devices
◆ Hence, USB enables the host to communicate with the I / O devices,
but it does not enable these devices to communicate with each other

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 USB Protocols
All information transferred over the USB is
organized in packets, where a packet consists of
one or more bytes of information
The information transferred on the USB can be
divided into two broad categories: control and
data
◆ Control packets perform such tasks as addressing a device
to initiate data transfer, acknowledging that data have been
received correctly, or indicating anerror
◆ Data packets carry informatio n that is delivered to a
device. For example, input and output data are
transferred inside data packets

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