Differential/Single-Ended Input, Dual

1 MSPS, 12-Bit, 3-Channel SAR ADC

Data Sheet AD7265
FEATURES FUNCTIONAL BLOCK DIAGRAM
REF SELECT DCAPA AVDD DVDD
Dual 12-bit, 3-channel ADC
Throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V REF BUF
AD7265
Power consumption
VA1
7 mW at 1 MSPS with 3 V supplies VA2
17 mW at 1 MSPS with 5 V supplies VA3
12-BIT
SUCCESSIVE OUTPUT
Pin-configurable analog inputs VA4
MUX T/H APPROXIMATION DRIVERS DOUTA
ADC
12-channel single-ended inputs VA5
6-channel fully differential inputs VA6
SCLK
CS
6-channel pseudo differential inputs RANGE
70 dB SINAD at 50 kHz input frequency CONTROL SGL/DIFF
LOGIC A0
Accurate on-chip reference: 2.5 V A1
±0.2% maximum at 25°C, 20 ppm/°C maximum VB1 A2

Dual conversion with read 875 ns, 16 MHz SCLK VB2

VDRIVE
High speed serial interface VB3
MUX 12-BIT
VB4
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible T/H
SUCCESSIVE
APPROXIMATION
OUTPUT
DRIVERS DOUTB
−40°C to +125°C operation VB5 ADC
VB6
Shutdown mode: 1 µA maximum
32-lead LFCSP and 32-lead TQFP BUF

2 MSPS version, AD7266

04674-001
AGND AGND AGND DCAPB DGND DGND
GENERAL DESCRIPTION
Figure 1.
The AD7265 1 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V PRODUCT HIGHLIGHTS
power supply and features throughput rates of up to 1 MSPS. The
1. Two Complete ADC Functions Allow Simultaneous
device contains two ADCs, each preceded by a 3-channel
Sampling and Conversion of Two Channels.
multiplexer, and a low noise, wide bandwidth track-and-hold
Each ADC has three fully/pseudo differential pairs, or six
amplifier that can handle input frequencies in excess of 30 MHz.
single-ended channels, as programmed. The conversion
The conversion process and data acquisition use standard result of both channels is simultaneously available on
control inputs allowing easy interfacing to microprocessors or separate data lines, or in succession on one data line if only
DSPs. The input signal is sampled on the falling edge of CS; one serial port is available.
conversion is also initiated at this point. The conversion time is 2. High Throughput with Low Power Consumption.
determined by the SCLK frequency. The AD7265 uses advanced The AD7265 offers a 1 MSPS throughput rate with 9 mW
design techniques to achieve very low power dissipation at high maximum power dissipation when operating at 3 V.
throughput rates. With 5 V supplies and a 1 MSPS throughput rate,
the part consumes 4 mA maximum. The part also offers flexible 3. The AD7265 offers both a standard 0 V to VREF input range
power/throughput rate management when operating in normal and a 2 × VREF input range.
mode, because the quiescent current consumption is so low. 4. No Pipeline Delay.
The analog input range for the part can be selected to be a 0 V The part features two standard successive approximation
to VREF (or 2 × VREF) range, with either straight binary or twos ADCs with accurate control of the sampling instant via a CS
complement output coding. The AD7265 has an on-chip 2.5 V input and once off conversion control.
reference that can be overdriven when an external reference is
1
Protected by U.S. Patent No. 6,681,332.
preferred. This external reference range is 100 mV to VDD. The
AD7265 is available in 32-lead LFCSP and 32-lead TQFP.

Rev. C Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD7265 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Digital Inputs .............................................................................. 18
General Description ......................................................................... 1 VDRIVE ............................................................................................ 18
Functional Block Diagram .............................................................. 1 Modes of Operation ....................................................................... 19
Product Highlights ........................................................................... 1 Normal Mode.............................................................................. 19
Revision History ............................................................................... 2 Partial Power-Down Mode ....................................................... 19
Specifications..................................................................................... 3 Full Power-Down Mode ............................................................ 20
Timing Specifications .................................................................. 5 Power-Up Times ......................................................................... 21
Absolute Maximum Ratings............................................................ 6 Power vs. Throughput Rate ....................................................... 21
ESD Caution .................................................................................. 6 Serial Interface ................................................................................ 22
Pin Configurations and Function Descriptions ........................... 7 Microprocessor Interfacing ........................................................... 23
Typical Performance Characteristics ............................................. 9 AD7265 to ADSP-2181 .............................................................. 23
Terminology .................................................................................... 11 AD7265 to ADSP-BF531 ........................................................... 24
Theory of Operation ...................................................................... 13 AD7265 to TMS320C541 .......................................................... 24
Circuit Information .................................................................... 13 AD7265 to DSP563xx ................................................................ 25
Converter Operation .................................................................. 13 Application Hints ........................................................................... 26
Analog Input Structure .............................................................. 13 Grounding and Layout .............................................................. 26
Analog Inputs .............................................................................. 14 PCB Design Guidelines for LFCSP .......................................... 26
Analog Input Selection .............................................................. 17 Evaluating the AD7265 Performance ...................................... 26
Output Coding ............................................................................ 17 Outline Dimensions ....................................................................... 27
Transfer Functions...................................................................... 18 Ordering Guide .......................................................................... 27

REVISION HISTORY
1/2018—Rev. B to Rev. C 11/2006—Rev. 0 to Rev. A
Changed CP-32-7 to CP-32-2 ...................................... Throughout Changes to Format ............................................................. Universal
Changes to Figure 2 .......................................................................... 7 Changes to Reference Input/Output Section .................................4
Changed AD7265 to ADSP-218x Section Heading to AD7265 to Changes to Table 4.............................................................................7
ADSP-2181 Section Heading ........................................................ 23 Changes to Terminology Section ................................................. 11
Changes to AD7265 to ADSP-2181 Section and Figure 43 ...... 23 Changes to Figure 24 and Differential Mode Section ............... 15
Changed AD7265 to ADSP-BF53x Section Heading to AD7265 Changes to Figure 29...................................................................... 16
to ADSP-BF532 Section Heading ................................................. 24 Changes to AD7265 to ADSP-BF53x Section ............................ 24
Changes to AD7265 to ADSP-BF532 Section and Figure 44 ... 24 Updated Outline Dimensions ....................................................... 27
Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27
Changes to Ordering Guide .......................................................... 27
4/2005—Revision 0: Initial Version
1/2017—Rev. A to Rev. B
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 2 .......................................................................... 7
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27

Rev. C | Page 2 of 27
Data Sheet AD7265

SPECIFICATIONS
TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, fSCLK = 16 MHz, fS = 1 MSPS, VDRIVE = 2.7 V to 5.25 V; specifications apply using internal
reference or external reference = 2.5 V ± 1%, unless otherwise noted. 1

Table 1.
Parameter Specification Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 2 71 dB min fIN = 50 kHz sine wave; differential mode
69 dB min fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Signal-to-Noise + Distortion Ratio (SINAD)2 70 dB min fIN = 50 kHz sine wave; differential mode
68 dB min fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Total Harmonic Distortion (THD)2 –77 dB max fIN = 50 kHz sine wave; differential mode
–73 dB max fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Spurious-Free Dynamic Range (SFDR)2 –75 dB max fIN = 50 kHz sine wave
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz
Second-Order Terms –88 dB typ
Third-Order Terms –88 dB typ
Channel-to-Channel Isolation –88 dB typ
SAMPLE AND HOLD
Aperture Delay 3 11 ns max
Aperture Jitter3 50 ps typ
Aperture Delay Matching3 200 ps max
Full Power Bandwidth 33/26 MHz typ at 3 dB, VDD = 5 V/VDD = 3 V
3.5/3 MHz typ at 0.1 dB, VDD = 5 V/VDD = 3 V
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity2 ±1 LSB max ±0.5 LSB typ; differential mode
±1.5 LSB max ±0.5 LSB typ; single-ended and pseudo
differential modes
Differential Nonlinearity2,4 ±0.99 LSB max Differential mode
−0.99/+1.5 LSB max Single-ended and pseudo differential modes
Straight Binary Output Coding
Offset Error ±6 LSB max
Offset Error Match ±2 LSB typ
Gain Error ±2.5 LSB max
Gain Error Match ±0.5 LSB typ
Twos Complement Output Coding
Positive Gain Error ±2 LSB max
Positive Gain Error Match ±0.5 LSB typ
Zero Code Error ±5 LSB max
Zero Code Error Match ±1 LSB typ
Negative Gain Error ±2 LSB max
Negative Gain Error Match ±0.5 LSB typ
ANALOG INPUT 5
Single-Ended Input Range 0 V to VREF V RANGE pin low
0 V to 2 × VREF RANGE pin high
Pseudo Differential Input Range: VIN+ − VIN− 6 0 to VREF V RANGE pin low
2 × VREF V RANGE pin high
Fully Differential Input Range: VIN+ and VIN− VCM ± VREF/2 V VCM = common-mode voltage 7 = VREF/2
VIN+ and VIN− VCM ± VREF V VCM = VREF

Rev. C | Page 3 of 27
AD7265 Data Sheet
Parameter Specification Unit Test Conditions/Comments
DC Leakage Current ±1 µA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT
Reference Output Voltage 8 2.5 V min/V max ±0.2% max at 25°C
Long-Term Stability 150 ppm typ For 1000 hours
Output Voltage Hysteresis2 50 ppm typ
Reference Input Voltage Range 0.1/VDD V min/V max See Typical Performance Characteristics section
DC Leakage Current ±2 µA max External reference applied to Pin DCAPA/Pin DCAPB
Input Capacitance 25 pF typ
DCAPA, DCAPB Output Impedance 10 Ω typ
Reference Temperature Coefficient 20 ppm/°C max
10 ppm/°C typ
VREF Noise 20 µV rms typ
LOGIC INPUTS
Input High Voltage, VINH 2.8 V min
Input Low Voltage, VINL 0.4 V max
Input Current, IIN ±15 nA typ VIN = 0 V or VDRIVE
Input Capacitance, CIN3 5 pF typ
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE − 0.2 V min
Output Low Voltage, VOL 0.4 V max
Floating State Leakage Current ±1 µA max
Floating State Output Capacitance3 7 pF typ
Output Coding Straight (natural) binary SGL/DIFF = 1 with 0 V to VREF range selected
Twos complement SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range
CONVERSION RATE
Conversion Time 14 SCLK cycles 875 ns with SCLK = 16 MHz
Track-and-Hold Acquisition Time3 90 ns max Full-scale step input; VDD = 5 V
110 ns max Full-scale step input; VDD = 3 V
Throughput Rate 1 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/V max
VDRIVE 2.7/5.25 V min/V max
IDD Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static) 2.3 mA max VDD = 5.25 V
Operational, fS = 1 MSPS 4 mA max VDD = 5.25 V; 3.5 mA typ
fS = 1 MSPS 3.2 mA max VDD = 3.6 V; 2.7 mA typ
Partial Power-Down Mode 500 µA max Static
Full Power-Down Mode (VDD) 1 µA max TA = −40°C to +85°C
2.8 µA max TA > 85°C to 125°C
Power Dissipation
Normal Mode (Operational) 21 mW max VDD = 5.25 V
Partial Power-Down (Static) 2.625 mW max VDD = 5.25 V
Full Power-Down (Static) 5.25 µW max VDD = 5.25 V, TA = −40°C to +85°C
1
Temperature range is −40°C to +125°C.
2
See Terminology section.
3
Sample tested during initial release to ensure compliance.
4
Guaranteed no missed codes to 12 bits.
5
VIN− or VIN+ must remain within GND/VDD.
6
VIN− = 0 V for specified performance. For full input range on VIN− pin, see Figure 28 and Figure 29.
7
For full common-mode range, see Figure 24 and Figure 25.
8
Relates to Pin DCAPA or Pin DCAPB.

Rev. C | Page 4 of 27
Data Sheet AD7265
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted 1.

Table 2.
Parameter Limit at TMIN , TMAX Unit Description
fSCLK 2 1 MHz min TA = −40°C to +85°C
4 MHz min TA > 85°C to 125°C
16 MHz max
tCONVERT 14 × tSCLK ns max tSCLK = 1/fSCLK
875 ns max fSCLK = 16 MHz
tQUIET 30 ns min Minimum time between end of serial read and next falling edge of CS
t2 15/20 ns min VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C
20/30 ns min VDD = 5 V/3 V, CS to SCLK setup time, TA > 85°C to 125°C
t3 15 ns max Delay from CS until DOUTA and DOUTB are three-state disabled
t4 3 36 ns max Data access time after SCLK falling edge, VDD = 3 V
27 ns max Data access time after SCLK falling edge, VDD = 5 V
t5 0.45 tSCLK ns min SCLK low pulse width
t6 0.45 tSCLK ns min SCLK high pulse width
t7 10 ns min SCLK to data valid hold time, VDD = 3 V
5 ns min SCLK to data valid hold time, VDD = 5 V
t8 15 ns max CS rising edge to DOUTA, DOUTB, high impedance
t9 30 ns min CS rising edge to falling edge pulse width
t10 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance
50 ns max SCLK falling edge to DOUTA, DOUTB, high impedance
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
Interface section and Figure 41 and Figure 42.
2
Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.

Rev. C | Page 5 of 27
AD7265 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VDD to AGND −0.3 V to +7 V stress rating only; functional operation of the product at these
DVDD to DGND −0.3 V to +7 V or any other conditions above those indicated in the operational
VDRIVE to DGND −0.3 V to DVDD section of this specification is not implied. Operation beyond
VDRIVE to AGND −0.3 V to AVDD the maximum operating conditions for extended periods may
AVDD to DVDD −0.3 V to +0.3 V affect product reliability.
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
ESD CAUTION
Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except
Supplies 1 ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP/TQFP
θJA Thermal Impedance 108.2°C/W (LFCSP)
55°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec) 255°C
ESD 1.5 kV
1
Transient currents of up to 100 mA do not cause SCR latch up.

Rev. C | Page 6 of 27
Data Sheet AD7265

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDRIVE
DOUTA

DOUTB

DOUTA

DOUTB
VDRIVE
DGND

DGND
SCLK

SCLK
DVDD

DVDD
CS

CS
A0

A0
29
28
27
26
25
32
31
30
32 31 30 29 28 27 26 25

DGND 1 24 A1
DGND 1 24 A1
PIN 1
REF SELECT 2 23 A2 REF SELECT 2 23 A2
AV DD 3 22 SGL/DIFF AVDD 3 22 SGL/DIFF
DCAPA 4 AD7265 21 RANGE AD7265
AGND 5 TOP VIEW 20 DCAPB DCAP A 4 21 RANGE
TOP VIEW
AGND 6 (Not to Scale) 19 AGND AGND 5 (Not to Scale) 20 DCAP B
VA1 7 18 VB1
VA2 AGND 6 19 AGND
8 17 VB2
VA1 7 18 VB1
VA2 8 17 VB2
11
9
10

12
13
14
15
16
VA3
VA4
VA5
VA6
VB6
VB5
VB4
VB3

9 10 11 12 13 14 15 16

04674-041
VA3
VA4
VA5
VA6
VB6
VB5
VB4
VB3
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE

04674-002
UNDERSIDE OF THE PACKAGE. CONNECT THE EPAD TO
THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS.

Figure 2. 32-Lead CP-32-2 Figure 3. 32-Lead SU-32-2

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
2 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used
as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to
decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the
AD7265 through the DCAPA pin and/or the DCAPB pin.
3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The
AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
4, 20 DCAPA, DCAPB Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference
can be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect
to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
7 to 12 VA1 to VA6 Analog Inputs of ADC A. These can be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
13 to 18 VB6 to VB1 Analog Inputs of ADC B. These can be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog
input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic
high when CS goes low, the analog input range is 2 × VREF. See the Analog Input Selection section for details.
22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A
logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected can be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265
and framing the serial data transfer.

Rev. C | Page 7 of 27
AD7265 Data Sheet
Pin No. Mnemonic Description
27 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This
clock is also used as the clock source for the conversion process.
28, 30 DOUTB, DOUTA Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears
on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros
followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles
rather than 14, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a
simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one
serial port. See the Serial Interface section.
31 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin can be different than that at AVDD and DVDD but
should never exceed either by more than 0.3 V.
32 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DVDD
and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a
transient basis. This supply should be decoupled to DGND.
EPAD Exposed Pad. The exposed pad is located on the underside of the package. Connect the exposed pad to the
ground plane of the PCB using multiple vias.

Rev. C | Page 8 of 27
Data Sheet AD7265

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.
–60
4096 POINT FFT
INTERNAL REFERENCE
–10 VDD = 5V, VDRIVE = 3V
FSAMPLE = 1MSPS
–70 FIN = 26kHz
SINAD = 71.4dB
–30 THD = –84.42dB
–80 DIFFERENTIAL MODE
EXTERNAL REFERENCE
PSRR (dB)

–50

(dB)
–90

–70
–100

–110 –90
100mV p-p SINE WAVE ON AVDD
NO DECOUPLING
SINGLE-ENDED MODE
–120 –110

04674-006
04674-003
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 50 100 150 200 250 300 350 400 450 500
SUPPLY RIPPLE FREQUENCY (kHz) FREQUENCY (kHz)

Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 7. FFT

–50 1.0
VDD = 5V VDD = 5V, VDRIVE = 3V
DIFFERENTIAL MODE
–55 0.8

–60 0.6

–65 0.4
DNL ERROR (LSB)
ISOLATION (dB)

–70 0.2

–75 0

–80 –0.2

–85 –0.4

–90 –0.6

–95 –0.8

–100 –1.0

04674-007
04674-004

0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000
NOISE FREQUENCY (kHz) CODE

Figure 5. Channel-to-Channel Isolation Figure 8. Typical DNL

74 1.0
RANGE = 0 TO VREF VDD = 5V, VDRIVE = 3V
DIFFERENTIAL MODE
0.8

VDD = 5V 0.6
72 DIFFERENTIAL MODE
0.4
INL ERROR (LSB)

0.2
SINAD (dB)

70 0

–0.2
VDD = 3V
DIFFERENTIAL MODE
–0.4
68
–0.6

–0.8

66 –1.0
04674-008
04674-005

0 500 1000 0 500 1000 1500 2000 2500 3000 3500 4000
INPUT FREQUENCY (kHz) CODE

Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 9. Typical INL

Rev. C | Page 9 of 27
AD7265 Data Sheet
1.0 10000
VDD = 3V/5V INTERNAL 10000
DIFFERENTIAL
DIFFERENTIAL MODE REFERENCE MODE
0.8 9000 CODES

0.6 POSITIVE DNL 8000

LINEARITY ERROR (LSB)

0.4 7000

NO. OF OCCURRENCES
POSITIVE INL
0.2 6000

0 5000

–0.2 4000
NEGATIVE INL
–0.4 3000

–0.6 NEGATIVE DNL 2000

–0.8 1000

–1.0 0

04674-009

04674-012
0 0.5 1.0 1.5 2.0 2.5 2046 2047 2048 2049 2050
VREF (V) CODE

Figure 10. Linearity Error vs. VREF Figure 13. Histogram of Codes for 10k Samples in Differential Mode

12.0 10000
INTERNAL 9984 SINGLE-ENDED
REFERENCE CODES MODE
11.5 9000

11.0 8000
EFFECTIVE NUMBER OF BITS

VDD = 5V
7000
NO. OF OCCURRENCES
10.5 SINGLE-ENDED MODE
10.0 6000

9.5 VDD = 3V 5000

SINGLE-ENDED MODE
9.0 4000

8.5 VDD = 3V VDD = 5V

3000
DIFFERENTIAL MODE DIFFERENTIAL MODE
8.0 2000

7.5 1000
5 CODES 11 CODES
7.0 0

04674-042
04674-010

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2046 2047 2048 2049 2050
VREF (V) CODE

Figure 11. Effective Number of Bits vs. VREF Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode

2.5010 –60
DIFFERENTIAL MODE
VDD = 3V/5V
–65
2.5005
–70

2.5000
–75
CMRR (dB)
VREF (V)

2.4995 –80

–85
2.4990
–90

2.4985
–95

2.4980 –100
04674-040
04674-011

0 20 40 60 80 100 120 140 160 180 200 0 200 400 600 800 1000 1200
CURRENT LOAD (µA) RIPPLE FREQUENCY (kHz)

Figure 12. VREF vs. Reference Output Current Drive Figure 15. CMRR vs. Common-Mode Ripple Frequency

Rev. C | Page 10 of 27
Data Sheet AD7265

TERMINOLOGY
Differential Nonlinearity (DNL) Signal-to-(Noise + Distortion) Ratio (SINAD)
Differential nonlinearity is the difference between the measured SINAD is the measured ratio of signal-to-(noise + distortion) at
and the ideal 1 LSB change between any two adjacent codes in the output of the ADC. The signal is the rms amplitude of the
the ADC. fundamental. Noise is the sum of all non-fundamental signals
Integral Nonlinearity (INL) up to half the sampling frequency (fS/2), excluding dc. The ratio is
Integral nonlinearity is the maximum deviation from a straight dependent on the number of quantization levels in the digitization
line passing through the endpoints of the ADC transfer function. process; the more levels, the smaller the quantization noise. The
The endpoints of the transfer function are zero scale with a theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
single (1) LSB point below the first code transition, and full scale converter with a sine wave input is given by
with a 1 LSB point above the last code transition. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Offset Error Therefore, for a 12-bit converter, this is 74 dB.
Offset error applies to straight binary output coding. It is the Total Harmonic Distortion (THD)
deviation of the first code transition (00 . . . 000) to (00 . . . 001) Total harmonic distortion is the ratio of the rms sum of harmonics
from the ideal (AGND + 1 LSB). to the fundamental. For the AD7265, it is defined as
Offset Error Match
Offset error match is the difference in offset error across all V 2 2 + V3 2 + V 4 2 + V5 2 + V 6 2
THD (dB) = 20 log
12 channels. V1

Gain Error where:

Gain error applies to straight binary output coding. It is the V1 is the rms amplitude of the fundamental.
deviation of the last code transition (111 . . . 110) to (111 . . . V2, V3, V4, V5, and V6 are the rms amplitudes of the second
111) from the ideal (VREF − 1 LSB) after the offset error is through the sixth harmonics.
adjusted out. Gain error does not include reference error. Peak Harmonic or Spurious Noise
Gain Error Match Peak harmonic, or spurious noise, is defined as the ratio of the
Gain error match is the difference in gain error across all rms value of the next largest component in the ADC output
12 channels. spectrum (up to fS/2, excluding dc) to the rms value of the funda-
Zero Code Error mental. Normally, the value of this specification is determined
Zero code error applies when using twos complement output by the largest harmonic in the spectrum, but for ADCs where
coding with, for example, the 2 × VREF input range as −VREF the harmonics are buried in the noise floor, it is a noise peak.
to +VREF biased about the VREF point. It is the deviation of Channel-to-Channel Isolation
the midscale transition (all 1s to all 0s) from the ideal VIN Channel-to-channel isolation is a measure of the level of crosstalk
voltage (VREF). between channels. It is measured by applying a full-scale (2 ×
Zero Code Error Match VREF when VDD = 5 V , and VREF when VDD = 3 V), 10 kHz sine
Zero code error match refers to the difference in zero code error wave signal to all unselected input channels and determining
across all 12 channels. how much that signal is attenuated in the selected channel with
a 50 kHz signal (0 V to VREF). The result obtained is the worst-
Positive Gain Error case across all 12 channels for the AD7265.
This applies when using twos complement output coding with,
for example, the 2 × VREF input range as −VREF to +VREF biased Intermodulation Distortion
about the VREF point. It is the deviation of the last code transition With inputs consisting of sine waves at two frequencies, fa and
(011…110) to (011…111) from the ideal (+VREF − 1 LSB) after fb, any active device with nonlinearities creates distortion products
the zero code error is adjusted out. at sum, and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
Track-and-Hold Acquisition Time for which neither m nor n are equal to zero. For example, the
The track-and-hold amplifier returns to track mode after the second-order terms include (fa + fb) and (fa − fb), while the
end of conversion. Track-and-hold acquisition time is the time third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
required for the output of the track-and-hold amplifier to reach (fa − 2fb).
its final value, within ±1/2 LSB, after the end of conversion.

Rev. C | Page 11 of 27
AD7265 Data Sheet
The AD7265 is tested using the CCIF standard where two input Thermal Hysteresis
frequencies near the top end of the input bandwidth are used. Thermal hysteresis is defined as the absolute maximum change
In this case, the second-order terms are usually distanced in of reference output voltage after the device is cycled through
frequency from the original sine waves, while the third-order temperature from either
terms are usually at a frequency close to the input frequencies. T_HYS+ = +25°C to TMAX to +25°C
As a result, the second-order and third-order terms are specified
separately. The calculation of the intermodulation distortion is or
as per the THD specification, where it is the ratio of the rms T_HYS− = +25°C to TMIN to +25°C
sum of the individual distortion products to the rms amplitude It is expressed in ppm by
of the sum of the fundamentals expressed in dBs.
VREF (25°C) − VREF (T _ HYS)
Common-Mode Rejection Ratio (CMRR) VHYS ( ppm) = × 10 6
CMRR is defined as the ratio of the power in the ADC output at VREF (25°C)
full-scale frequency, f, to the power of a 100 mV p-p sine wave where:
applied to the common-mode voltage of VIN+ and VIN− of VREF (25°C) is VREF at 25°C.
frequency fS as VREF (T_HYS) is the maximum change of VREF at T_HYS+ or
CMRR (dB) = 10 log(Pf/PfS) T_HYS−.
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 4).

Rev. C | Page 12 of 27
Data Sheet AD7265

THEORY OF OPERATION
CIRCUIT INFORMATION When the ADC starts a conversion (see Figure 17), SW3 opens
The AD7265 is a fast, micropower, dual, 12-bit, single-supply, and SW1 and SW2 move to Position B, causing the comparator
ADC that operates from a 2.7 V to a 5.25 V supply. When to become unbalanced. Both inputs are disconnected when the
operated from either a 3 V or a 5 V supply, the AD7265 is conversion begins. The control logic and the charge redistribution
capable of throughput rates of 1 MSPS when provided with a DACs are used to add and subtract fixed amounts of charge
16 MHz clock. from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
The AD7265 contains two on-chip, differential track-and-hold rebalanced, the conversion is complete. The control logic
amplifiers, two successive approximation ADCs, and a serial generates the ADC output code. The output impedances of the
interface with two separate data output pins. It is housed in a sources driving the VIN+ and VIN− pins must be matched;
32-lead LFCSP or a 32-lead TQFP, offering the user considerable otherwise, the two inputs have different settling times, resulting
space-saving advantages over alternative solutions. The serial in errors.
clock input accesses data from the part, but also provides the
clock source for each successive approximation ADC. The analog CAPACITIVE
DAC
input range for the part can be selected to be a 0 V to VREF input
COMPARATOR
or a 2 × VREF input, configured with either single-ended or differ- B CS
VIN+
ential analog inputs. The AD7265 has an on-chip 2.5 V reference A SW1
CONTROL
SW3
that can be overdriven when an external reference is preferred. If A
SW2 CS LOGIC
VIN–
the internal reference is to be used elsewhere in a system, then B
the output needs to be buffered first.
VREF

04674-014
CAPACITIVE
The AD7265 also features power-down options to allow power DAC

saving between conversions. The power-down feature is imple-

Figure 17. ADC Conversion Phase
mented via the standard serial interface, as described in the
Modes of Operation section. ANALOG INPUT STRUCTURE
CONVERTER OPERATION Figure 18 shows the equivalent circuit of the analog input structure
of the AD7265 in differential/pseudo differential modes. In single-
The AD7265 has two successive approximation ADCs, each
ended mode, VIN− is internally tied to AGND. The four diodes
based around two capacitive DACs. Figure 16 and Figure 17
provide ESD protection for the analog inputs. Care must be
show simplified schematics of one of these ADCs in acquisition
taken to ensure that the analog input signals never exceed the
and conversion phase, respectively. The ADC is comprised of
supply rails by more than 300 mV. This causes these diodes to
control logic, a SAR, and two capacitive DACs. In Figure 16 (the
become forward-biased and starts conducting into the substrate.
acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,
These diodes can conduct up to 10 mA without causing irreversible
the comparator is held in a balanced condition, and the sampling
damage to the part.
capacitor arrays acquire the differential signal on the input.
The C1 capacitors in Figure 18 are typically 4 pF and can primarily
CAPACITIVE be attributed to pin capacitance. The resistors are lumped compo-
DAC
nents made up of the on resistance of the switches. The value of
COMPARATOR
B CS these resistors is typically about 100 Ω. The C2 capacitors are
VIN+
A SW1 the sampling capacitors of the ADC with a capacitance of 45 pF,
CONTROL
SW2 CS
SW3
LOGIC typically.
VIN– A
B For ac applications, removing high frequency components from
VREF the analog input signal is recommended by the use of an RC low-
04674-013

CAPACITIVE
DAC pass filter on the relevant analog input pins with optimum values
of 47 Ω and 10 pF. In applications where harmonic distortion
Figure 16. ADC Acquisition Phase
and signal-to-noise ratio are critical, the analog input should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier. The choice of
the op amp is a function of the particular application.

Rev. C | Page 13 of 27
AD7265 Data Sheet
VDD
Figure 21 shows a graph of the THD vs. the analog input frequency
D
for various supplies while sampling at 1 MSPS. In this case, the
VIN+
R1 C2 source impedance is 47 Ω.
C1 D –50
FSAMPLE = 1MSPS
VDD = 3V/5V
–55 RANGE = 0 TO VREF
VDD
–60

D
R1 C2 –65 VDD = 3V
VIN– SINGLE-ENDED MODE

THD (dB)
C1 D –70 VDD = 3V
DIFFERENTIAL MODE

04674-015
–75

Figure 18. Equivalent Analog Input Circuit, –80

Conversion Phase—Switches Open, Track Phase—Switches Closed
–85 VDD = 5V
When no amplifier is used to drive the analog input, the source VDD = 5V DIFFERENTIAL MODE
SINGLE-ENDED MODE
impedance should be limited to low values. The maximum source –90

04674-018
0 100 200 300 400 500 600
impedance depends on the amount of THD that can be toler- INPUT FREQUENCY (kHz)
ated. The THD increases as the source impedance increases and Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
performance degrades. Figure 19 shows a graph of the THD vs.
the analog input signal frequency for different source impedances ANALOG INPUTS
in single-ended mode, while Figure 20 shows the THD vs. the The AD7265 has a total of 12 analog inputs. Each on-board
analog input signal frequency for different source impedances ADC has six analog inputs that can be configured as six single-
in differential mode. ended channels, three pseudo differential channels, or three
–50 fully differential channels. These can be selected as described in
FSAMPLE = 1MSPS
VDD = 3V RSOURCE = 300Ω the Analog Input Selection section.
–55 RANGE = 0V TO VREF
Single-Ended Mode
–60
The AD7265 can have a total of 12 single-ended analog input
–65 channels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input before
THD (dB)

–70
RSOURCE = 100Ω RSOURCE = 0Ω applying it to the ADC. The analog input range can be pro-
–75
RSOURCE = 47Ω
grammed to be either 0 to VREF or 0 to 2 × VREF.
–80 If the analog input signal to be sampled is bipolar, the internal
–85 RSOURCE = 10Ω
reference of the ADC can be used to externally bias up this
signal to make it correctly formatted for the ADC. Figure 22
–90
shows a typical connection diagram when operating the ADC
04674-016

0 100 200 300 400 500 600

INPUT FREQUENCY (kHz) in single-ended mode.
Figure 19. THD vs. Analog Input Frequency for +2.5V
Various Source Impedances, Single-Ended Mode R
+1.25V 0V
–60 R
FSAMPLE = 1MSPS 0V VIN
VDD = 3V RSOURCE = 300Ω
RANGE = 0V TO VREF –1.25V 3R VA1 AD72651
–65
R
RSOURCE = 0Ω VB6 DCAP A/DCAP B
–70

RSOURCE = 100Ω
THD (dB)

0.47µF
–75
04674-019

–80
RSOURCE = 47Ω
1ADDITIONAL PINS OMITTED FOR CLARITY.

–85 Figure 22. Single-Ended Mode Connection Diagram

RSOURCE = 10Ω
–90
04674-017

0 100 200 300 400 500 600

INPUT FREQUENCY (kHz)

Figure 20. THD vs. Analog Input Frequency for

Various Source Impedances, Differential Mode

Rev. C | Page 14 of 27
Data Sheet AD7265
Differential Mode 3.5
TA = 25°C

The AD7265 can have a total of six differential analog 3.0

input pairs.

COMMON-MODE RANGE (V)

2.5
Differential signals have some benefits over single-ended
signals, including noise immunity based on the common-mode 2.0
rejection and improvements in distortion performance of the
device. Figure 23 defines the fully differential analog input of 1.5

the AD7265.
1.0

VREF p-p VIN+ 0.5

COMMON AD72651
0

04674-021
MODE
VREF p-p VIN– 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOLTAGE
VREF (V)

04674-020 Figure 24. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
1ADDITIONAL PINS OMITTED FOR CLARITY.
5.0
TA = 25°C
Figure 23. Differential Input Definition 4.5

The amplitude of the differential signal is the difference between 4.0

COMMON-MODE RANGE (V)

the signals applied to the VIN+ and VIN− pins in each differential 3.5

pair (VIN+ − VIN−). VIN+ and VIN− should be simultaneously driven 3.0
by two signals each of amplitude VREF (or 2 × VREF, depending 2.5
on the range chosen) that are 180° out of phase. The amplitude
2.0
of the differential signal is therefore (assuming the 0 to VREF
range is selected) −VREF to +VREF peak-to-peak (2 × VREF), 1.5

regardless of the common mode (CM). 1.0

The common mode is the average of the two signals 0.5

0
(VIN+ + VIN−)/2

04674-022
0 0.5 1.0 1.5 2.0 2.5
VREF (V)
and is therefore the voltage on which the two inputs are
centered. Figure 25. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)

This results in the span of each input being CM ± VREF/2. This Driving Differential Inputs
voltage has to be set up externally, and its range varies with the Differential operation requires that VIN+ and VIN− be simultaneously
reference value, VREF. As the value of VREF increases, the common- driven with two equal signals that are 180° out of phase. The
mode range decreases. When driving the inputs with an amplifier, common mode must be set up externally. The common-mode
the actual common-mode range is determined by the output range is determined by VREF, the power supply, and the particular
voltage swing of the amplifier. amplifier used to drive the analog inputs. Differential modes of
Figure 24 and Figure 25 show how the common-mode range operation with either an ac or dc input provide the best THD
typically varies with VREF for a 5 V power supply using the 0 to performance over a wide frequency range. Because not all appli-
VREF range or 2 × VREF range, respectively. The common mode cations have a signal preconditioned for differential operation,
must be in this range to guarantee the functionality of the AD7265. there is often a need to perform single-ended-to-differential
conversion.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the
2 × VREF range is used, then the input signal amplitude extends
from −2 VREF to +2 VREF after conversion.

Rev. C | Page 15 of 27
AD7265 Data Sheet
Using an Op Amp Pair Pseudo Differential Mode
An op amp pair can be used to directly couple a differential The AD7265 can have a total of six pseudo differential pairs. In
signal to one of the analog input pairs of the AD7265. The this mode, VIN+ is connected to the signal source that must have
circuit configurations illustrated in Figure 26 and Figure 27 an amplitude of VREF (or 2 × VREF, depending on the range chosen)
show how a dual op amp can be used to convert a single-ended to make use of the full dynamic range of the part. A dc input is
signal into a differential signal for both a bipolar and unipolar applied to the VIN− pin. The voltage applied to this input provides
input signal, respectively. an offset from ground or a pseudo ground for the VIN+ input.
The voltage applied to Point A sets up the common-mode The benefit of pseudo differential inputs is that they separate
voltage. In both diagrams, it is connected in some way to the the analog input signal ground from the ADC’s ground allowing
reference, but any value in the common-mode range can be dc common-mode voltages to be cancelled. The typical voltage
input here to set up the common mode. The AD8022 is a range for the VIN− pin, while in pseudo differential mode, is
suitable dual op amp that can be used in this configuration to shown in Figure 28 and Figure 29. Figure 30 shows a connection
provide differential drive to the AD7265. diagram for pseudo differential mode.
1.0
TA = 25°C
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives. 0.8

The driver circuits in Figure 26 and Figure 27 are optimized for

0.6
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 26 converts a unipolar, 0.4

VIN– (V)
single-ended signal into a differential signal. 0.2

The differential op amp driver circuit shown in Figure 27 is

0
configured to convert and level shift a single-ended, ground-
referenced (bipolar) signal to a differential signal centered at the –0.2
VREF level of the ADC.
–0.4

04674-043
2 × VREF p-p 220Ω 3.75V 0 0.5 1.0 1.5 2.0 2.5 3.0
2.5V VREF (V)
440Ω V+
VREF 1.25V
27Ω
GND
VIN+
AD72651 Figure 28. VIN− Input Voltage Range vs. VREF in
V– Pseudo Differential Mode with VDD = 3 V
220Ω 2.5
3.75V TA = 25°C
220Ω
2.5V
V+ 2.0
1.25V
27Ω
VIN– DCAP A/DCAP B
A
V– 1.5
10kΩ
0.47µF
VIN– (V)

1.0
04674-023

0.5
1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

0
into a Differential Signal
2 × VREF p-p 220Ω 3.75V
–0.5
04674-044

2.5V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
440Ω V+
GND 1.25V VREF (V)
27Ω
1
VIN+ AD7265
Figure 29. VIN− Input Voltage Range vs. VREF in
V–
Pseudo Differential Mode with VDD = 5 V
220kΩ 220Ω
220Ω 3.75V
VREF
2.5V p–p AD72651
V+ VIN+
1.25V
27Ω
VIN– DCAP A/DCAP B
A
V–
10kΩ VIN–
0.47µF DC INPUT VREF
20kΩ VOLTAGE

0.47µF
04674-024

1ADDITIONAL PINS OMITTED FOR CLARITY.

04674-025

Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal 1ADDITIONAL PINS OMITTED FOR CLARITY.
into a Differential Unipolar Signal
Figure 30. Pseudo Differential Mode Connection Diagram

Rev. C | Page 16 of 27
Data Sheet AD7265
ANALOG INPUT SELECTION The channels used for simultaneous conversions are selected via
The analog inputs of the AD7265 can be configured as single- the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition time;
ended or true differential via the SGL/DIFF logic pin, as shown
however, they can change during the conversion time, provided
in Figure 31. If this pin is tied to a logic low, the analog input
that the mode is not changed. If the mode is changed from fully
channels to each on-chip ADC are set up as three true differen-
differential to pseudo-differential, for example, then the acquisition
tial pairs. If this pin is at logic high, the analog input channels to
time starts again from this point. The selected input channels are
each on-chip ADC are set up as six single-ended analog inputs.
decoded as shown in Table 6.
The required logic level on this pin needs to be established prior
to the acquisition time and remain unchanged during the con- The analog input range of the AD7265 can be selected as 0 V to
version time until the track-and-hold has returned to track. The VREF or 0 V to 2 × VREF via the RANGE pin. This selection is made
track-and-hold returns to track on the 13th rising edge of SCLK in a similar fashion to that of the SGL/DIFF pin by setting the
after the CS falling edge (see Figure 41). If the level on this pin logic state of the RANGE pin a time tacq prior to the falling edge
is changed, it is recognized by the AD7265; therefore, it is of CS. Subsequent to this, the logic level on this pin can be altered
necessary to keep the same logic level during acquisition and after the third falling edge of SCLK. If this pin is tied to a logic
conversion to avoid corrupting the conversion in progress. low, the analog input range selected is 0 V to VREF. If this pin is
tied to a logic high, the analog input range selected is 0 V to
For example, in Figure 31, the SGL/DIFF pin is set at logic high
2 × VREF.
for the duration of both the acquisition and conversion times
so the analog inputs are configured as single ended for that OUTPUT CODING
conversion (Sampling Point A). The logic level of the SGL/DIFF The AD7265 output coding is set to either twos complement or
changed to low after the track-and-hold returned to track and straight binary, depending on which analog input configuration
prior to the required acquisition time for the next sampling is selected for a conversion. Table 5 shows which output coding
instant at Point B; therefore, the analog inputs are configured as scheme is used for each possible analog input configuration.
differential for that conversion.
A B
Table 5. AD7265 Output Coding
tACQ Range Output Coding
CS SGL/DIFF
1 14 1 14 DIFF 0 V to VREF Twos complement
SCLK
DIFF 0 V to 2 × VREF Twos complement
04674-026

SGL/DIFF SGL 0 V to VREF Straight binary

SGL 0 V to 2 × VREF Twos complement
Figure 31. Selecting Differential or Single-Ended Configuration
PSEUDO DIFF 0 V to VREF Straight binary
PSEUDO DIFF 0 V to 2 × VREF Twos complement

Table 6. Analog Input Type and Channel Selection

ADC A ADC B
SGL/DIFF A2 A1 A0 VIN+ VIN− VIN+ VIN− Comment
1 0 0 0 VA1 AGND VB1 AGND Single ended
1 0 0 1 VA2 AGND VB2 AGND Single ended
1 0 1 0 VA3 AGND VB3 AGND Single ended
1 0 1 1 VA4 AGND VB4 AGND Single ended
1 1 0 0 VA5 AGND VB5 AGND Single ended
1 1 0 1 VA6 AGND VB6 AGND Single ended
0 0 0 0 VA1 VA2 VB1 VB2 Fully differential
0 0 0 1 VA1 VA2 VB1 VB2 Pseudo differential
0 0 1 0 VA3 VA4 VB3 VB4 Fully differential
0 0 1 1 VA3 VA4 VB3 VB4 Pseudo differential
0 1 0 0 VA5 VA6 VB5 VB6 Fully differential
0 1 0 1 VA5 VA6 VB5 VB6 Pseudo differential

Rev. C | Page 17 of 27
AD7265 Data Sheet
TRANSFER FUNCTIONS DIGITAL INPUTS
The designed code transitions occur at successive integer LSB The digital inputs applied to the AD7265 are not limited by the
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB maximum ratings that limit the analog inputs. Instead, the digital
size is VREF/4096 when the 0 V to VREF range is used, and the LSB inputs can be applied up to 7 V and are not restricted by the
size is 2 × VREF/4096 when the 0 V to 2 × VREF range is used. In VDD + 0.3 V limit, as are the analog inputs. See the Absolute
differential mode, the LSB size is 2 × VREF/4096 when the 0 V to Maximum Ratings section for more information. Another
VREF range is used, and the LSB size is 4 × VREF/4096 when the advantage of the SCLK, RANGE, A0 to A2, and CS pins not
0 V to 2 × VREF range is used. The ideal transfer characteristic being restricted by the VDD + 0.3 V limit is that power supply
for the AD7265 when straight binary coding is output is shown sequencing issues are avoided. If one of these digital inputs is
in Figure 32, and the ideal transfer characteristic for the AD7265 applied before VDD, there is no risk of latch-up, as there would
when twos complement coding is output is shown (with the 2 × be on the analog inputs if a signal greater than 0.3 V were
VREF range) in Figure 33. applied prior to VDD.
VDRIVE
111...111 The AD7265 also has a VDRIVE feature to control the voltage at
111...110 which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
111...000 the AD7265 was operated with a VDD of 5 V, the VDRIVE pin can
ADC CODE

1LSB = VREF/4096 be powered from a 3 V supply, allowing a large dynamic range

011...111 with low voltage digital processors. Therefore, the AD7265 can
be used with the 2 × VREF input range, with a VDD of 5 V while
000...010
still being able to interface to 3 V digital parts.
000...001
000...000
0V 1LSB VREF – 1LSB
ANALOG INPUT
04674-027

NOTE
1. VREF IS EITHER VREF OR 2 × VREF.

Figure 32. Straight Binary Transfer Characteristic

1LSB = 2  VREF/4096

011...111
011...110

000...001
ADC CODE

000...000
111...111

100...010
100...001
100...000
04674-028

–VREF + 1LSB VREF – 1LSB +VREF – 1 LSB

ANALOG INPUT

Figure 33. Twos Complement Transfer Characteristic with

VREF ± VREF Input Range

Rev. C | Page 18 of 27
Data Sheet AD7265

MODES OF OPERATION
The mode of operation of the AD7265 is selected by controlling When 32 SCLK cycles have elapsed, the DOUT line returns to three-
the (logic) state of the CS signal during a conversion. There are state on the 32nd SCLK falling edge. If CS is brought high prior
three possible modes of operation: normal mode, partial power- to this, the DOUT line returns to three-state at that point. There-
down mode, and full power-down mode. After a conversion is fore, CS can idle low after 32 SCLK cycles until it is brought
initiated, the point at which CS is pulled high determines which high again sometime prior to the next conversion (effectively
power-down mode, if any, the device enters. Similarly, if already idling CS low), if so desired, because the bus still returns to
in a power-down mode, CS can control whether the device returns three-state upon completion of the dual result read.
to normal operation or remains in power-down. These modes When a data transfer is complete and DOUTA and DOUTB have
of operation are designed to provide flexible power management returned to three-state, another conversion can be initiated after
options. These options can be chosen to optimize the power the quiet time, tQUIET, has elapsed by bringing CS low again
dissipation/throughput rate ratio for differing application (assuming the required acquisition time is allowed).
requirements.
PARTIAL POWER-DOWN MODE
NORMAL MODE
This mode is intended for use in applications where slower
This mode is intended for applications that need the fastest throughput rates are required. Either the ADC is powered down
throughput rates because the user does not have to worry about between each conversion, or a series of conversions can be
any power-up times with the AD7265 remaining fully powered performed at a high throughput rate, and the ADC is then
at all times. Figure 34 shows the general diagram of the operation powered down for a relatively long duration between these
of the AD7265 in this mode. bursts of several conversions. When the AD7265 is in partial
CS power-down, all analog circuitry is powered down except for
1 10 14
the on-chip reference and reference buffer.
SCLK To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the
04674-029

DOUTA
DOUTB LEADING ZEROS + CONVERSION RESULT second falling edge of SCLK and before the 10th falling edge of
SCLK, as shown in Figure 35. When CS is brought high in this
Figure 34. Normal Mode Operation
window of SCLKs, the part enters partial power-down, the
The conversion is initiated on the falling edge of CS, as described conversion that was initiated by the falling edge of CS is
in the Serial Interface section. To ensure that the part remains terminated, and DOUTA and DOUTB go back into three-state. If
fully powered up at all times, CS must remain low until at least CS is brought high before the second SCLK falling edge, the
10 SCLK falling edges have elapsed after the falling edge of CS. part remains in normal mode and does not power down. This
If CS is brought high any time after the 10th SCLK falling edge avoids accidental power-down due to glitches on the CS line.
but before the 14th SCLK falling edge, the part remains powered
up, but the conversion is terminated and DOUTA and DOUTB go CS

back into three-state. Fourteen serial clock cycles are required 1 2 10 14

to complete the conversion and access the conversion result. The SCLK

DOUT line does not return to three-state after 14 SCLK cycles have

04674-030
elapsed, but instead does so when CS is brought high again. If DOUTA THREE-STATE
DOUTB
CS is left low for another 2 SCLK cycles (for example, if only a
Figure 35. Entering Partial Power-Down Mode
16 SCLK burst is available), two trailing zeros are clocked out
after the data. If CS is left low for a further 14 (or 16) SCLK cycles,
the result from the other ADC on board is also accessed on the
same DOUT line, as shown in Figure 42 (see the Serial Interface
section).

Rev. C | Page 19 of 27
AD7265 Data Sheet
To exit this mode of operation and power up the AD7265 again, When the AD7265 is in full power-down, all analog circuitry is
a dummy conversion is performed. On the falling edge of CS, powered down. Full power-down is entered in a similar way as
the device begins to power up and continues to power up as partial power-down, except the timing sequence shown in
long as CS is held low until after the falling edge of the 10th Figure 35 must be executed twice. The conversion process must
SCLK. The device is fully powered up after approximately 1 μs be interrupted in a similar fashion by bringing CS high anywhere
has elapsed, and valid data results from the next conversion, as after the second falling edge of SCLK and before the 10th falling
shown in Figure 36. If CS is brought high before the second edge of SCLK. The device enters partial power-down at this
falling edge of SCLK, the AD7265 again goes into partial point. To reach full power-down, the next conversion cycle
power-down. This avoids accidental power-up due to glitches must be interrupted in the same way, as shown in Figure 37.
on the CS line. Although the device can begin to power up on When CS is brought high in this window of SCLKs, the part
the falling edge of CS, it powers down again on the rising edge completely powers down.
of CS. If the AD7265 is already in partial power-down mode Note that it is not necessary to complete the 14 SCLKs when CS
and CS is brought high between the second and 10th falling is brought high to enter a power-down mode.
edges of SCLK, the device enters full power-down mode. To exit full power-down and power up the AD7265, a dummy
FULL POWER-DOWN MODE conversion is performed, as when powering up from partial
This mode is intended for use in applications where throughput power-down. On the falling edge of CS, the device begins to
rates slower than those in the partial power-down mode are power up and continues to power up, as long as CS is held low
required, as power-up from a full power-down takes until after the falling edge of the 10th SCLK. The required power-
substantially longer than that from partial power-down. This up time must elapse before a conversion can be initiated, as
mode is more suited to applications where a series of shown in Figure 38. See the Power-Up Times section for the
conversions performed at a relatively high throughput rate are power-up times associated with the AD7265.
followed by a long period of inactivity and thus power-down.

THE PART IS FULLY

THE PART BEGINS POWERED UP; SEE
TO POWER UP. POWER-UP TIMES
tPOWER-UP1 SECTION.

CS

1 10 14 1 14
SCLK

04674-031
DOUTA
INVALID DATA VALID DATA
DOUTB

Figure 36. Exiting Partial Power-Down Mode

THE PART ENTERS THE PART BEGINS THE PART ENTERS

PARTIAL POWER DOWN. TO POWER UP. FULL POWER DOWN.

CS

1 2 10 14 1 2 10 14
SCLK
04674-032

DOUTA THREE-STATE THREE-STATE

DOUTB INVALID DATA INVALID DATA

Figure 37. Entering Full Power-Down Mode

Rev. C | Page 20 of 27
Data Sheet AD7265
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
THE PART BEGINS
TO POWER UP. tPOWER-UP2
CS

1 10 14 1 14
SCLK

04674-033
DOUTA
INVALID DATA VALID DATA
DOUTB

Figure 38. Exiting Full Power-Down Mode

POWER-UP TIMES However, the AD7265 quiescent current is low enough that even
As described in detail, the AD7265 has two power-down modes, without using the power-down options, there is a noticeable
partial power-down and full power-down. This section explains variation in power consumption with sampling rate. This is true
the power-up time required when coming out of either of these whether a fixed SCLK value is used or if it is scaled with the
modes. Note that the power-up times, as explained in this section, sampling rate. Figure 39 and Figure 40 show plots of power vs.
apply with the recommended capacitors in place on the DCAPA the throughput rate when operating in normal mode for a fixed
and DCAPB pins. maximum SCLK frequency, and an SCLK frequency that scales
with the sampling rate with VDD = 3 V and VDD = 5 V, respectively.
To power up from full power-down (whether using an internal In all cases, the internal reference was used.
or external reference), approximately 1.5 ms should be allowed 10.0
TA = 25°C
from the falling edge of CS, shown as tPOWER-UP2 in Figure 38.
9.5
Powering up from partial power-down requires much less time.
9.0
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must 8.5

be in partial power-down for at least 67 μs in order for this 8.0

POWER (mW)

power-up time to apply. 7.5

When power supplies are first applied to the AD7265, the ADC 7.0
VARIABLE SCLK 16MHz SCLK
can power up in either of the power-down modes or normal mode. 6.5
Because of this, it is best to allow a dummy cycle to elapse to 6.0
ensure that the part is fully powered up before attempting a
5.5
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are 5.0

04674-045
0 100 200 300 400 500 600 700 800 900 1000
applied, then two dummy cycles must be initiated. The first THROUGHPUT (kSPS)

dummy cycle must hold CS low until after the 10th SCLK falling Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
edge (see Figure 34); in the second cycle, CS must be brought 25
TA = 25°C
high before the 10th SCLK edge but after the second SCLK 23
falling edge (see Figure 35). Alternatively, if it is intended to 21
place the part in full power-down mode when the supplies are
19
applied, then three dummy cycles must be initiated. The first VARIABLE SCLK
17
dummy cycle must hold CS low until after the 10th SCLK falling
POWER (mW)

15
edge (see Figure 34); the second and third dummy cycles place
16MHz SCLK
the part in full power-down (see Figure 37). 13

When supplies are applied to the AD7265, enough time must be 11

allowed for any external reference to power up and charge the 9

various reference buffer decoupling capacitors to their final values. 7

POWER vs. THROUGHPUT RATE 5

04674-046

0 100 200 300 400 500 600 700 800 900 1000
The power consumption of the AD7265 varies with throughput THROUGHPUT (kSPS)

rate. When using very slow throughput rates and as fast an Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
SCLK frequency as possible, the various power-down options
can be used to make significant power savings.

Rev. C | Page 21 of 27
AD7265 Data Sheet

SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter- A minimum of 14 serial clock cycles are required to perform
facing to the AD7265. The serial clock provides the conversion the conversion process and to access data from one conversion
clock and controls the transfer of information from the AD7265 on either data line of the AD7265. CS going low provides the
during conversion. leading zero to be read in by the microcontroller or DSP. The
The CS signal initiates the data transfer and conversion process. remaining data is then clocked out by subsequent SCLK falling
The falling edge of CS puts the track-and-hold into hold mode, edges, beginning with a second leading zero. Therefore, the first
falling clock edge on the serial clock has the leading zero pro-
at which point the analog input is sampled and the bus is taken
vided and also clocks out the second leading zero. The 12-bit
out of three-state. The conversion is also initiated at this point
result then follows with the final bit in the data transfer valid on
and requires a minimum of 14 SCLKs to complete. When
the 14th falling edge, having being clocked out on the previous
13 SCLK falling edges have elapsed, the track-and-hold goes
(13th) falling edge. It can also be possible to read in data on each
back into track on the next SCLK rising edge, as shown in
SCLK rising edge depending on the SCLK frequency or the
Figure 41 at Point B. If a 16-SCLK transfer is used, then two
supply voltage. The first rising edge of SCLK after the CS falling
trailing zeros appear after the final LSB. On the rising edge of CS,
edge would have the second leading zero provided, and the 13th
the conversion is terminated and DOUTA and DOUTB go back into
rising SCLK edge would have DB0 provided.
three-state. If CS is not brought high but is instead held low for
a further 14 (or 16) SCLK cycles on DOUTA, the data from Note that with fast SCLK values, and thus short SCLK periods,
Conversion B is output on DOUTA (followed by 2 trailing zeros). to allow adequately for t2, an SCLK rising edge can occur before
the first SCLK falling edge. This rising edge of SCLK can be
Likewise, if CS is held low for a further 14 (or 16) SCLK cycles
ignored for the purposes of the timing descriptions in this section.
on DOUTB, the data from Conversion A is output on DOUTB. This
If a falling edge of SCLK is coincident with the falling edge of
is illustrated in Figure 42 where the case for DOUTA is shown. In
CS, then this falling edge of SCLK is not acknowledged by the
this case, the DOUT line in use goes back into three-state on the
AD7265, and the next falling edge of SCLK is the first registered
32nd SCLK falling edge or the rising edge of CS, whichever
after the falling edge of CS.
occurs first.

CS
t9
t2 t6 B
SCLK 1 2 3 4 5 13

t5 t8 tQUIET
t7
t3 t4
DOUTA
0 0 DB11 DB10 DB9 DB8 DB2 DB1 DB0
DOUTB THREE- THREE-STATE
STATE 04674-034
2 LEADING ZEROS

Figure 41. Serial Interface Timing Diagram

CS

t2 t6
SCLK 1 2 3 4 5 14 15 16 17 32
t5 t10
t3 t4 t7
DOUTA 0 ZERO DB11A DB10A DB9A ZERO ZERO ZERO ZERO DB11B ZERO ZERO
THREE- THREE-
04674-035

STATE 2 LEADING 2 TRAILING ZEROS 2 TRAILING ZEROS STATE

ZEROS 2 LEADING ZEROS

Figure 42. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs

Rev. C | Page 22 of 27
Data Sheet AD7265

MICROPROCESSOR INTERFACING
The serial interface on the AD7265 allows the part to be directly The connection diagram is shown in Figure 43. The ADSP-2181
connected to a range of many different microprocessors. This has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1
section explains how to interface the AD7265 with some of the tied together. TFS0 is set as an output, and both RFS0 and RFS1
more common microcontroller and DSP serial interface are set as inputs. The DSP operates in alternate framing mode,
protocols. and the SPORT control register is set up as described. The frame
AD7265 TO ADSP-2181 synchronization signal generated on the TFS is tied to CS, and,
as with all signal processing applications, equidistant sampling
The ADSP-2181 family of DSPs interface directly to the AD7265 is necessary. However, in this example, the timer interrupt is
without any glue logic required. The VDRIVE pin of the AD7265 used to control the sampling rate of the ADC and, under certain
takes the same supply voltage as that of the ADSP-218x. This conditions, equidistant sampling may not be achieved.
allows the ADC to operate at a higher supply voltage than its
serial interface and, therefore, the ADSP-2181, if necessary. This AD72651 ADSP-21811
example shows both DOUTA and DOUTB of the AD7265 connected SCLK SCLK0

to both serial ports of the ADSP-2181. The SPORT0 and SCLK1

SPORT1 control registers should be set up as shown in Table 7 CS TFS0

and Table 8. RFS0

RFS1
Table 7. SPORT0 Control Register Setup
DOUTA DR0
Setting Description
DOUTB DR1
TFSW = RFSW = 1 Alternate framing
VDRIVE
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
SLEN = 1111 16-bit data-word (or can be set to 1101

04674-036
VDD
for 14-bit data-word)
ISCLK = 1 Internal serial clock 1ADDITIONAL PINS OMITTED FOR CLARITY.

TFSR = RFSR = 1 Frame every word Figure 43. Interfacing the AD7265 to the ADSP-2181
IRFS = 0 The timer registers are loaded with a value that provides an
ITFS = 1 interrupt at the required sample interval. When an interrupt is
Table 8. SPORT1 Control Register Setup received, a value is transmitted with TFS/DT (ADC control word).
The TFS is used to control the RFS, and hence, the reading of data.
Setting Description
The frequency of the serial clock is set in the SCLKDIV register.
TFSW = RFSW = 1 Alternate framing
When the instruction to transmit with TFS is given (AX0 = TX0),
INVRFS = INVTFS = 1 Active low frame signal
the state of the SCLK is checked. The DSP waits until the SCLK
DTYPE = 00 Right justify data
has gone high, low, and high again before transmission starts. If
SLEN = 1111 16-bit data-word (or can be set to 1101
for 14-bit data-word) the timer and SCLK values are chosen such that the instruction
ISCLK = 0 External serial clock to transmit occurs on or near the rising edge of SCLK, then the
TFSR = RFSR = 1 Frame every word data may be transmitted or it may wait until the next clock edge.
IRFS = 0 For example, the ADSP-2111 has a master clock frequency of
ITFS = 1 16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
To implement the power-down modes, SLEN should be set to periods elapse for every one SCLK period. If the timer registers
1001 to issue an 8-bit SCLK burst. are loaded with the value 803, then 100.5 SCLKs occur between
interrupts and, subsequently, between transmit instructions. This
situation yields sampling that is not equidistant, as the transmit
instruction is occurring on a SCLK edge. If the number of SCLKs
between interrupts is a whole integer figure of N, then equidistant
sampling is implemented by the DSP.

Rev. C | Page 23 of 27
AD7265 Data Sheet
AD7265 to ADSP-BF531 AD7265 TO TMS320C541
The ADSP-BF531 interfaces directly to the AD7265 without any The serial interface on the TMS320C541 uses a continuous
glue logic required. The availability of secondary receive registers serial clock and frame synchronization signals to synchronize
on the serial ports of the Blackfin® DSPs means only one serial the data transfer operations with peripheral devices like the
port is necessary to read from both DOUT pins simultaneously. AD7265. The CS input allows easy interfacing between the
Figure 44 shows both DOUTA and DOUTB of the AD7265 connected TMS320C541 and the AD7265 without any glue logic required.
to Serial Port 0 of the ADSP-BF531. The SPORT0 Receive The serial ports of the TMS320C541 are set up to operate in
Configuration 1 register and SPORT0 Receive Configuration 2 burst mode with internal CLKX0 (TX serial clock on Serial
register should be set up as outlined in Table 9 and Table 10. Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial
port control registers (SPC) must have the following setup.
AD72651 SERIAL
ADSP-BF5311
DEVICE A
(PRIMARY)
SPORT0
Table 11. Serial Port Control Register Setup
DOUT A DR0PRI
SPC FO FSM MCM TXM
SCLK RCLK0
SPC0 0 1 1 1
CS RFS0 SPC1 0 1 0 0
DOUTB DR0SEC
SERIAL
VDRIVE DEVICE B The format bit, FO, can be set to 1 to set the word length to
(SECONDARY)
8 bits to implement the power-down modes on the AD7265.
The connection diagram is shown in Figure 45. For signal proce-
04674-037

VDD
ssing applications, it is imperative that the frame synchronization
1ADDITIONAL PINS OMITTED FOR CLARITY.
signal from the TMS320C541 provide equidistant sampling. The
Figure 44. Interfacing the AD7265 to the ADSP-BF531
VDRIVE pin of the AD7265 takes the same supply voltage as that
Table 9. The SPORT0 Receive Configuration 1 Register of the TMS320C541. This allows the ADC to operate at a higher
(SPORT0_RCR1) voltage than its serial interface, and therefore, the TMS320C541, if
Setting Description necessary.
RCKFE = 1 Sample data with falling edge of RSCLK TMS320C5411
AD72651
LRFS = 1 Active low frame signal SCLK CLKX0
RFSR = 1 Frame every word CLKR0
IRFS = 1 Internal RFS used CLKX1
RLSBIT = 0 Receive MSB first
CLKR1
RDTYPE = 00 Zero fill
DOUTA DR0
IRCLK = 1 Internal receive clock
DOUTB DR1
RSPEN = 1 Receive enabled
CS FSX0
16-bit data-word (or can be set to 1101
SLEN = 1111 for 14-bit data-word) FSR0

TFSR = RFSR = 1 VDRIVE FSR1

Table 10. The SPORT0 Receive Configuration 2 Register 04674-038

VDD
(SPORT0_RCR2)
1ADDITIONAL PINS OMITTED FOR CLARITY.
Setting Description
RXSE = 1 Secondary side enabled Figure 45. Interfacing the AD7265 to the TMS320C541
SLEN = 1111 16-bit data-word (or can be set to 1101
for 14-bit data-word)
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
AD7265 is available to download at www.analog.com.

Rev. C | Page 24 of 27
Data Sheet AD7265
AD7265 TO DSP563xx In the example shown in Figure 46, the serial clock is taken from
The connection diagram in Figure 46 shows how the AD7265 the ESSI0 so the SCK0 pin must be set as an output, SCKD = 1,
can be connected to the ESSI (synchronous serial interface) of while the SCK1 pin is set as an input, SCKD = 0. The frame sync
the DSP563xx family of DSPs from Motorola. There are two signal is taken from SC02 on ESSI0, so SCD2 = 1, while on ESSI1,
on-board ESSIs, and each operates in synchronous mode SCD2 = 0; therefore, SC12 is configured as an input. The VDRIVE pin
(Bit SYN = 1 in CRB register) with internally generated word of the AD7265 takes the same supply voltage as that of the
length frame sync for both TX and RX (Bit FSL1 = 0 and DSP563xx. This allows the ADC to operate at a higher voltage
Bit FSL0 = 0 in CRB). than its serial interface and therefore the DSP563xx, if necessary.

Normal operation of the ESSI is selected by making MOD = 0 AD72651 DSP563xx1

in the CRB. Set the word length to 16 by setting Bit WL1 = 1 SCLK SCK0

and Bit WL0 = 0 in CRA. SCK1

DOUTA SRD0
To implement the power-down modes on the AD7265, the word
DOUTB SRD1
length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 CS SC02

so the frame sync is negative. It is imperative for signal processing VDRIVE SC12

applications that the frame synchronization signal from the

DSP563xx provides equidistant sampling.

04674-039
VDD

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Interfacing the AD7265 to the DSP563xx

Rev. C | Page 25 of 27
AD7265 Data Sheet

APPLICATION HINTS
GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP
The analog and digital supplies to the AD7265 are independent The lands on the chip scale package (CP-32-2) are rectangular.
and separately pinned out to minimize coupling between the The PCB pad for these should be 0.1 mm longer than the
analog and digital sections of the device. The printed circuit package land length, and 0.05 mm wider than the package land
board (PCB) that houses the AD7265 should be designed so width, thereby having a portion of the pad exposed. To ensure
that the analog and digital sections are separated and confined that the solder joint size is maximized, the land should be
to certain areas of the board. This design facilitates the use of centered on the pad.
ground planes that can be easily separated. The bottom of the chip scale package has a thermal pad. The
To provide optimum shielding for ground planes, a minimum thermal pad on the PCB should be at least as large as the
etch technique is generally best. All three AGND pins of the exposed pad. On the PCB, there should be a clearance of at least
AD7265 should be sunk in the AGND plane. Digital and analog 0.25 mm between the thermal pad and the inner edges of the
ground planes should be joined in only one place. If the AD7265 pad pattern to ensure that shorting is avoided.
is in a system where multiple devices require an AGND to DGND To improve thermal performance of the package, use thermal
connection, the connection should still be made at one point vias on the PCB incorporating them in the thermal pad at
only, a star ground point that should be established as close as 1.2 mm pitch grid. The via diameter should be between 0.3 mm
possible to the ground pins on the AD7265. and 0.33 mm, and the via barrel should be plated with 1 oz.
Avoid running digital lines under the device as this couples copper to plug the via. The user should connect the PCB
noise onto the die. However, the analog ground plane should be thermal pad to AGND.
allowed to run under the AD7265 to avoid noise coupling. The EVALUATING THE AD7265 PERFORMANCE
power supply lines to the AD7265 should use as large a trace as
The recommended layout for the AD7265 is outlined in the
possible to provide low impedance paths and reduce the effects
evaluation board documentation. The evaluation board package
of glitches on the power supply line.
includes a fully assembled and tested evaluation board, docu-
To avoid radiating noise to other sections of the board, fast mentation, and software for controlling the board from the PC
switching signals, such as clocks, should be shielded with digital via the evaluation board controller. The evaluation board con-
ground, and clock signals should never run near the analog troller can be used in conjunction with the AD7265 evaluation
inputs. Avoid crossover of digital and analog signals. To reduce board, as well as many other Analog Devices, Inc. evaluation
the effects of feedthrough within the board, traces on opposite boards ending in the CB designator, to demonstrate/evaluate
sides of the board should run at right angles to each other. A the ac and dc performance of the AD7265.
microstrip technique is the best method but is not always
The software allows the user to perform ac (fast Fourier
possible with a double-sided board. In this technique, the
transform) and dc (histogram of codes) tests on the AD7265.
component side of the board is dedicated to ground planes,
The software and documentation are on a CD shipped with the
while signals are placed on the solder side.
evaluation board.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and ESI capacitors provide a low impedance path to ground at
high frequencies to handle transient currents due to internal
logic switching.

Rev. C | Page 26 of 27
Data Sheet AD7265

OUTLINE DIMENSIONS
5.10
5.00 SQ
0.60 MAX
4.90
0.60 MAX
25 32 PIN 1
24 1
INDICATOR
0.50
PIN 1 4.75 BSC 3.25
INDICATOR BSC SQ EXPOSED 3.10 SQ
PAD
2.95

17 8

16 9
0.50 0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
12° MAX 0.80 MAX 0.30 3.50 REF
1.00
0.65 TYP
0.85 FOR PROPER CONNECTION OF
0.05 MAX THE EXPOSED PAD, REFER TO
0.80
0.02 NOM THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
SEATING 0.30 SECTION OF THIS DATA SHEET.
0.08
PLANE 0.25 0.20 REF

11-10-2017-B
0.18
PKG-001050

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.85 mm Package Height
(CP-32-2)
Dimensions shown in millimeters

0.75 1.20
MAX 9.00 BSC SQ
0.60
0.45
32 25
1 24

PIN 1

7.00
TOP VIEW BSC SQ
0° MIN (PINS DOWN)
1.05 0.20
1.00 0.09
0.95 7°
3.5° 8 17
0.15 0° 9 16
SEATING
0.05 0.08 MAX
PLANE COPLANARITY VIEW A 0.80 0.45
BSC
LEAD PITCH 0.37
VIEW A 0.30
ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD7265BCPZ –40°C to +125°C 32-Lead LFCSP CP-32-2
AD7265BCPZ-REEL7 –40°C to +125°C 32-Lead LFCSP CP-32-2
AD7265BSUZ –40°C to +125°C 32-Lead TQFP SU-32-2
AD7265BSUZ-REEL7 –40°C to +125°C 32-Lead TQFP SU-32-2
AD7265BSUZ-REEL –40°C to +125°C 32-Lead TQFP SU-32-2
EVAL-AD7265EDZ Evaluation Board
1
Z = RoHS Compliant Part.

©2005–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04674-0-1/18(C)

Rev. C | Page 27 of 27