A

PRACTICAL FILE

OF

DIGITAL ELECTRONICS LAB (ESC-304)

BACHELOR OF TECHNOLOGY

IN

COMPUTER SCIENCE ENGINEERING

Submitted To: Submitted By:

Ms. BHAWANA GUPTA

(ASSISTANT PROFESSOR)
 Digital Electronics Lab (ESC-304) 2024

LIST OF EXPERIMENTS

S. Name of Experiment Page Date of Signature

No. No. Experiment

1 Study of TTL gates – AND, OR, NOT,

NAND, NOR, EX-OR, EX-NOR.
Design and realize a given function
2
using K-maps and verify its
performance
3 To study and verify the truth table of
half adder and full adder circuit.

4 To verify the truth table of a 4-bit

comparator.

(a) To demonstrate the functioning of

5 8:1 Multiplexer and verify its truth
table.
(b) To verify the truth table of 1:8
Demultiplexer.

To verify the operation of flip flops (S-R.

6
J-K and D-Type using ICs 7476, 7474)

7 To verify the operation of Bi-

directional shift register.

8 To design and Verify the operation of

3- Bit Synchronous Counter

9 To design a decade counter and verify

its truth table.

10
To verify the operation of ring counter.
Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 1

AIM: - Study of TTL gates – AND; OR; NOT; NAND; NOR; EX-OR; EX-NOR
APPARATUS REQUIRED: Power Supply, Digital Trainer Kit., Connecting Leads,
IC’s (7400, 7402, 7404, 7408, 7432, and 7486)
BRIEF THEORY:
AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs
are (1) one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y is the Output
terminal.
Y = A.B

Input A Input B Output Q

0 0 0
0 1 0
1 0 0
1 1 1
Traditional symbol Truth Table

Fig 1. IC configuration for AND gate

In AND gate circuit it has n input and only one output. Digital signals are applied in

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input terminal. In the AND gate operation is „t‟ if and only if all the input are „1‟ otherwise
zero.
Mathematically :The output Q is true if input A AND input B are both true: Q = A
AND B
An AND gate can have two or more inputs, its output is true if all inputs are true.

OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are
(1) one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y is the Output
terminal.
Y=A+B

Input A Input B Output Q

0 0 0
0 1 1
1 0 1
1 1 1
Traditional symbol Truth Table

Fig 2. IC configuration for OR gate

In OR-Gate operation it has also n input and only one output. In OR operation output is

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one if and only if one or more input are ‘1’.

Mathematically
The output Q is true if input A OR input B is true (or both of them are true):
Q = A OR B

An OR gate can have two or more inputs, its output is true if at least one input istrue.

NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output
(Y). IC No. is 7404. Its logical equation is,
Y = A NOT B, Y = A’

Input A Output Q
0 1
1 0

Truth Table Traditional symbol

Fig 3. IC configuration for NOT gate

It is also known as inverter. It has only one input and one output. Mathematically,
The output Q is true when the input A is NOT true, the output is the inverse of the input: Q
= NOT A. A NOT gate can only have one input. A NOT gate is also called an inverter.
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as

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NAND operation. If all inputs are 1 then output produced is 0. NAND gate is inverted
AND gate.
Y = (A. B)’

Traditional symbol Truth Table

Fig 4. IC configuration for NAND gate

NOR GATE: The NOR gate has two or more input signals but only one output signal. IC
7402 is two I/P IC. The NOT- OR operation is known as NOR operation. If all the inputs
are 0 then the O/P is 1. NOR gate is inverted OR gate.

Y = (A+B)’

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Traditional symbol

Fig 5. IC configuration for NOR gate

EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486
is two inputs IC. EX-OR gate is not a basic operation & can be performed using basic gates.

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Fig 6. IC configuration for Ex-OR gate

PROCEDURE:
1. Take the corresponding IC for which the gate is to be studied.
2. Connect the 7th pin to ground of the power supply (which means 0 in binary language).
3. Connect the 14th pin to +5V of the power supply (which means 1 in binary language).
4. Give the inputs and check the output as per the truth table.
5. Perform the above steps to study all the gates by using their corresponding IC’s
6. Check the supply before switching on the assembly circuit, it should not exceed +5V.
7. In case if the result is not verified, then repeat the steps from 1 to 4.

PRECAUTIONS:
1. Connection should be neat and clean.
2. Vcc should not exceed +5V.
3. IC’s should be handled carefully.

RESULT:-

………………………………..
Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 2

AIM: Design and realize a given function using K-maps and verify its performance.
To demonstrate that the performance of the given Boolean expression
Y = A’B’C’ + A’B’C + A’BC’+ A’BC
and its reduced version using K-map are same.
APPARATUS REQUIRED: Power Supply, Digital Trainer, IC’s (7404, 7408, 7432)
Connecting leads.
BRIEF THEORY: Karnaugh maps are the most extensively used tool for simplification of
Boolean functions. It is mostly used for functions having up to six variables beyond which it
becomes very cumbersome. In an n-variable K-map there are 2n cells. Each cell corresponds to
one of the combination of n variable, since there are 2n combinations of n-variables. Gray
code has been used for the identification of cells.
B’ B
A’ 0 2

1 3
A

K map for two variables has four squares i.e. 22 squares. A Boolean function of ‘N’ variables
will require 2N squares map is found very useful in simplifying logic expressions before
translating them into logic circuits. For a SOP solution, it is required developed product terms 4
which we may proceed as follows:
 If the starting point is a Boolean expression exam in each of the equation has all the
variables. If not expand the expression.
 If the starting point is a truth table, developed all the product terms.
 Construct a SOP expression containing those product terms which correspond to logic
one state.
 Now draw a k map having 2N square, where 'N' is the number of variable and enter 1 in
those square in the map, which correspond to the product terms.
 Now form groups of ones.

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 The next step is to take all the non-variables corresponding to the a enclosures and write
the SOP expression by oring the reduced terms.

The realisation by k map is given for the following function:-

Y = A’B’C’ + A’B’C + A’BC’+ A’BC

K MAP REDUCTION

After solving the k map the output is:

Y= A’
PROCEDURE:
1. Meet the connections on the breadboard using various ICS as per the given Boolean
expression Y.
2. Connect vcc and ground pins of the IC to the power supply according to pin layout for all
ICs.
3. Check the output for various combinations of input using logic probe.
4. Prepare the truth table for the same.
5. Simplify the given equation using k map.
6. Make the new connections as per the reduced expression using various IC's.
7. Verify the output for the same.
8. Prepare the truth table for the same.
9. Inke, if the result is not verified then repeat the steps from 1 to 6.

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Truth Table I for Y= A’B’C’ + A’B’C + A’BC’ + A’BC

Decimal No. A B C A’ B’ C’ A’B’C’ A’B’C A’BC’ A’BC Y

0 0 0 0 1 1 1 1 0 0 0 1
1 0 0 1 1 1 0 0 1 0 0 1
2 0 1 0 1 0 1 0 0 1 0 1
3 0 1 1 1 0 0 0 0 0 1 1
4 1 0 0 0 1 1 0 0 0 0 0
5 1 0 1 0 1 0 0 0 0 0 0
6 1 1 0 0 0 1 0 0 0 0 0
7 1 1 1 0 0 0 0 0 0 0 0

Truth Table II for Y= A’

Decimal
No. A B C Y= A’
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 0
6 1 1 0 0
7 1 1 1 0
PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
RESULT/CONCLUSION:

………………………………..
Signature of Staff in charge

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EXPERIMENT NO: 3

AIM: - To study and verify the truth table of half adder and full adder circuit.

APPARATUS REQUIRED: IC 7408, 7486, 7432, dc supply (+5V), breadboard, logic

probe.

THEORY: A half adder is a logic circuit that adds two binary bits. The inputs to the circuit
are two bits say A and B and output of the circuit are Sum (S) and Carry (C). The truth table
for half adder can be shown using the addition table for binary numbers.

Table 1: Truth table for Half Adder

The Boolean expression for half adder with the above truth table can be written using K-
map for S and C as

S = A’B + AB’ or S=A⊕B

C = AB

Using the above expression the function can be realize as shown in fig.1

Fig.1: Logic diagram of Half Adder

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Full Adder: We can add more than two binary digits. We cannot use half adder for this
purpose as it does not have any input to handle carry bits. Hence we need a circuit
which takes the bit of the augend, addend and carry, adds them and represents sum (S)
and carry (C) and such a circuit is called a full adder, it has the provision for handling
carries as well as addend and augend bits. Full adder has three inputs , the two inputs
corresponds to the bits to be added (A,B) and one for any carry (Co) that has been
generated from the previous stage.

The truth table for the same is given below:

Using K- map the reduced expression for S and C are as shown:

S = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin

Co = AB + BCin + ACin

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Using the above expression the logic diagram for full adder can be drawn as shown in
fig 2.

Fig 2. Logic Diagram for Full Adder

PROCEDURE:

Half Adder:

1. Insert the IC (7408 i.e. AND gate and 7486 i.e. EX-OR).

2. Make the connections on the breadboard as per figure 1.

3. Connect Vcc to pin 14 and ground to Pin 7 as per the pin diagram of the IC.

4. To verify the truth table gives various combinations of A and B i.e. inputs and checks the
values of Sum and Carry generated.

5. In case the truth table is not verified repeat the steps from 1 to 4.

Full Adder:

1. Insert IC (7408 i.e. AND gate and 7486 i.e. EX-OR and 7432 i.e. OR gate).

2. Make the connections on the breadboard as per figure2.

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3. Single 7408 IC is made up of four AND gates so connections are made according to pin
layout of the IC. Use only three AND gates as per the logic diagram. Connect the output
of IC 7408 to input of IC 7432 generate the carry.

4. Connect Vcc to pin 14 and ground to Pin 7 as per the pin diagram of the IC.

5. To verify the truth table gives various combinations of A, B and Cin i.e. inputs and check
the values of Sum and Carry generated.

6. In case the truth table is not verified repeat the steps from 1 to 5.

PRECAUTIONS:

1. Check whether the connections are tight.

2. Handle IC with care and voltage should not exceed 5 volt.

3. Make sure that there is no short circuit.

RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 4

AIM: To verify the truth table of a 4-Bit comparator.

APPARATUS REQUIRED: Breadboard, power supply (5V), logic probe, connecting wires,
IC7485.

THEORY:
Comparators are designed for comparing multi-bit numbers. In the n-bit comparator, it receives
two n-bit numbers. A and B as inputs and the outputs are A>B, A=B, A<B. Depending upon the
relative magnitude of two numbers, one of the outputs will be high. however, in a 4-bit
comparator available in MSI (7485) which can compare straight binary and natural BCD. These
IC’s can be cascaded to compare bits of greater lengths without external inputs.

Truth Table:

Table 1: Truth table for 4-bit comparator (IC7485)

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Pin Configuration of IC 7485:

PROCEDURE:

1. Insert the IC in the breadboard according to the pin diagram as shown in the figure above.

2. Connect the pin 8 to the ground and pin 16 to the +5V of power supply.

3. Connect the first number to A0, A1, A2, A3 and second number to B0, B1, B2, B3.

4. With the help of a logic probe check the output at pin no. 5, 6, 7 and verify the truth table.

5. Pin 2,3 and 4 are left open and are to be connected if the number to be compared is bigger
than 4-bit, they are called cascading inputs.

6. In case, the result is not verified then repeat the steps from 1 to 5.

PRECAUTIONS:

1. Check that the connections are right and tight.

2. Handle ICs with care and voltage should not exceed 5V.

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3. Check the output with a probe carefully.

RESULT:

…..…………………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 5(A)

To verify the operation of a Multiplexer.

AIM: To demonstrate the functioning of 8:1 MUX and verify its truth table.

APPARATUS REQUIRED: Breadboard, IC 74151, connecting wires, dc power supply (15V),

and logic probe.

THEORY: A Multiplexer (or a data selector) is a logic circuit that accepts several data inputs
and allows only one of them at a time to get through to the output. The selection of the desired
data input is controlled by the SELECT (or ADDRESS) INPUTS. Multiplexer means
transmitting a large number of information units over a smaller number of channels or lines. A
digital multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input line and n selection lines whose
bit combination determine which input is selected. Figure below shows the block diagram of a
Multiplexer

Block Diagram:-

Fig.1: 8:1 MUX

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Pin configuration of 74151:

Fig.2: Pin Diagram

Table 1:Truth Table

Enable Select Inputs Output

E' S2 S1 S0 Y
1 X X X 0
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7

PROCEDURE:
1. Take the breadboard and insert IC 74151 in it.
2. Apply +5V to pin 24 and GND to pin 12 as shown in the pin layout.
3. To get the selected data line (D0 ………..D7) at the output the pin E has to be grounded.
4. With select lines (S0, S1, S2), select one of the data inputs (D0 ………..D7) and connect
it to either low (logic 0 or ground) or to high (logic 1 or Vcc), check the output Y’ and

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verify it with the truth table.

5. In case, if the result is not verified then repeat the steps from 1 to 4.

PRECAUTIONS:
1. Insert and remove ICs carefully, otherwise its legs will break.
2. Power supply voltage should not exceed 5V.
3. Connections should be neat and tight.

RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 5(B)

AIM: To demonstrate the functioning of 1:8 DEMUX and verify its truth table.

APPARATUS REQUIRED: Breadboard, IC 74138, connecting wires, dc power supply (5V),

and logic probe.

THEORY: The demultiplexer performs the reverse operation of a multiplexer. It accepts single
input and distributes at several outputs. The select input code determines to which output the data
input will be transmitted. The number of output line is n. The number of select line is m, where n
= 2m. This circuit is also used as binary to decimal decoder with binary input applied at select
input lines and the output will be obtained on corresponding line. The data input line is to be
connected to logic 1 level. The device is very useful if multiple output combinational circuits are
to be designed. The output at most of these devices are active low, also there is an active low
enable data input terminal available. It requires some gates in order to realize Boolean expression
in standard SOP form.

Pin Configuration:

Fig 1: Pin Diagram

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Block Diagram for 1:8 DEMUX:

Fig. 2: 1:8 DEMUX

Truth Table:

PROCEDURE:
1. Make the connections on breadboard according to the pin diagram and block diagram of
IC 74154.
2. Both strobe and enable (G2A’, G2B’) should be kept low to select one of the eight inputs

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with the select input lines (A, B, C), verify the output line (0-7) as low (Logic 0) as
shown in truth table.
3. In case, if the result is not verified then repeat the steps from 1 to 2.

PRECAUTIONS:
1. Connections should be tight.
2. IC pins should not be shorted.
3. Supply voltage should not exceed +5V.

RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 6

AIM: To verify the operation of flip flops (S-R. J-K and D-Type using ICs 7476, 7474)

APPARATUS REQUIRED: Breadboard, Connecting wires, ICs 7476 and 7474, logic probe,
function generator, power supply (5V).

THEORY:

S-R Flip-flop:-
In order to set or reset the memory cell in synchronization with train of pulses, we use clocked
set-reset flip-flop.
In the circuit if a clock pulse is present i.e. clk=1, Its operation is as follows.
 If the clock in the circuit is low i.e. S=R=0, then the output is same as the output of the
previous state.
 When S=0 and R=1, then we obtain the output = 0 or we can say that the output is reset.
 When S=1 and R=0, the output Q=1.
 When S=R=1, then this is inconsistent with our assumption of complimentary output.
The logic diagram using Nand gates is shown in Fig1, pin configuration, truth table and
symbol are also shown below.

For S-R and J-K flip-flop the IC used is same i.e. IC 7476

Fig1: Logic diagram of S-R flip-flop

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Symbol:-

Truth Table:-

Pin Configuration (7476):-

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J-K Flip-flop:-
The uncertainty in the state of SR flip-flop when S=R=1 can be eliminated by converting it in J-
K flip-flop respectively to obtain S-R input i.e.
S = J𝑄, R = KQ
The truth table of J-K flip-flop is made from all possible combinations of the inputs to J-K flip-
flop. For each combination both the states of the output have been considered.

Fig 2: Logic diagram of J-K flip-flop

Symbol:-

Truth Table:-

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D-type Flip-flop:-
The D flip-flop ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1.
The Delay flip-flop is designed using a gated SR flip-flop with an inverter connected between
the inputs allowing for a single input D (Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop
is constructed from a level-sensitive SR flip flop.

Fig 3: Logic diagram of D- flip-flop

Symbol:-

Truth Table:-

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Pin Configuration (7476):-

PROCEDURE (7476):-
1. To verify the truth table of S-R flip-flop and J-K flip-flop insert the 7476 IC on the
breadboard and make connections according to the pin layout.
2. Apply 5V to pin 5 and 0 V (ground) to pin 13.
3. Apply clock pulse at pin 1 using function generator.
4. Now according to the locations of S, R, J and K provide the desired input as per the truth
table and check the output (Q) using logic probe.
5. In case required output is not verified repeat steps 1 to 4.

PROCEDURE (7474):-
1. To verify the truth table of D flip-flop insert the 7474 IC on the breadboard and make
connections according to the pin layout.
2. Apply 5V to pin 14 and 0 V (ground) to pin 7.
3. Apply clock pulse at pin 3 using function generator.
4. Now according to the location of D, provide the desired input as per the truth table and
check the output (Q) using logic probe.
5. In case required output is not verified repeat steps 1 to 4.

PRECAUTIONS:-
1. Don’t exceed voltage more than 5 V.
2. Insert IC carefully

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RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 7

AIM: To verify the operation of Bi-directional shift register.

APPARATUS REQUIRED: Breadboard, Connecting wires, IC 7495, power supply (5V).

THEORY:

An array of flip-flops that can store binary information is called a register. A register in which
data is entered or taken out in serial form is called shift register. In bi-directional shift register,
data can be shifted from left to right and vice versa. IC 7495 is a 4-bit bi-directional shift
register. A to D are the input pins and QA to QD are used as the output pins. CLK R and CLK
L are the clock inputs used for right shift and left shift operations respectively. MC is mode
control pin. When MC is high, loading of data takes place and when it is low shifting of data can
be performed.

Pin Configuration (7495):-

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Block Diagram (7495):-

The data is stored after each flip-flop on the ‘Q’ output, so there are four storage ‘slots’ available
in this arrangements, hence it is a 4-bit Register. To give an idea of the shifting pattern, imagine
that the register holds 0000 (so all storage slots are empty). As ‘Data In’ presents 1, 1, 0, 1, 0, 0,
0, and 0 (in that order, with a pulse at ‘Data Advance’ each time. This is called clocking or
strobing) to the register, this is the result. The left hand column corresponds to the left most flip-
flop output pin and so on.

So the serial output of the entire register is 00001101 (not counting the final step). As you can
see if we were to continue to input the data, we would get exactly what was put in, but offset by
four ‘Data Advance’ cycles. This arrangement is the hardware equivalent of a queue. Also, at
any time, the whole register can be set to zero by bringing the reset pins high.

PROCEDURE:-
1. Mount the IC 7495 on the breadboard.
2. Connect pin 14 to Vcc and pin 7 to GND.
3. Apply data through pins A,B,C and D (pins 2,3,4,5).
4. Apply logic 1 at pin number 6.
5. As soon as the clock is applied to pin 8 (CLK L), the data present at the input is loaded
and appears at the output.
6. For shifting the data to the left, QA is to be connected to A, QB to B and QC to C and
data is to be entered though input D.

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7. For shifting the data to the right , pin 6 (MC) should be low and data is to be applied
through QA (pin 13), make sure that while entering the data through QA, pin 1 (DS/SI)
should have the same condition as the pin 13 (QA).
8. In case if the result is not verified then check the connections and repeat the steps from 1
to 7.

Truth table for left shift operation:-

Truth table for right shift operation:-

PRECAUTIONS :-
1. Connections should be made properly.
2. Don’t exceed voltage more than 5 V.
3. IC should be place carefully
RESULT:-

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT No: 8

AIM: To design and verify the operation of 3 bit synchronous counter.

APPARATUS REQUIRED: J-K flip-flop (IC 7476), AND gate (IC 7408), LED’s, Breadboard,
Connecting wires, power supply (5V).

THEORY: When all the flip-flops are clocked simultaneously the resulting circuit is known as
the synchronous counter. Synchronous counter can be designed for any count sequence. Consider
the count sequence given in the table of fig2, the number of states in this sequence is 8 which
requires 3 flip-flops and Q2,Q1 & Q0 are the outputs of these flip-flops.

Flip-Flop Input Output

FF0 J0, K0 Q0
FF1 J1, K1 Q1
FF2 J2, K2 Q2

Fig1. Input & output flip-flops

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Now using K maps, we find the values of J0, K0, J1, K1, J2 and K2.

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First clock pulse is applied Q0 = 0 and it is required to be 1 at the end of the first clock pulse.
Therefore, to achieve this condition the values of J0 and K0 are 1 and X respectively (from
excitation map, when the second clock pulse is applied Q0 is to change from 1 to 0, therefore the
required inputs are J0=X and K0=1. In this manner inputs of each FF are determined. The final
synchronous counter can be designed using minimized K map expressions:
J0 = 1, K0 = 1
J1 = Q0, K1= Q0
J2 = Q0Q1, K2 = Q0Q1

Fig3. Circuit Diagram for 3-bit synchronous counter (Mod 8 counter)

PROCEDURE:-
1. Inset IC 7474 and IC 7408 on the bread board.
2. Make connections according to Fig. 3.
3. Connect the Vcc and ground of the ICs as per the pin diagram.
4. Give the clock with the help of function generator and initially clear all the flip-flops.
5. Verify the output as shown in the count sequence at Q0, Q1 and Q2.
6. In case if the result is not verified then repeat the steps from 1 to 3.

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PRECAUTIONS:-
1. Connections should be made properly.
2. Don’t exceed voltage more than 5 V.
3. IC should be place carefully

RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 9

AIM: To design a decade counter and verify its truth table.

APPARATUS REQUIRED: IC 7490, Bread Board, connecting wires, logic probe, dc power
supply, function generator, LED( 4 no.), current limiting resistance 330 ohm( 4 no.).

THEORY: A circuit is used for counting the number of pulses is called as counter. A binary
mod 10 counter is very useful counter as it provides means to change binary count to its
equivalent count in the decimal mode.
IC 7490 consists of four flip flops internally connected to provide a mod-2 counter and a mod-5
counter. The Mod-2 and mod-5 counters can be used independently or in combination. Flip flop
FF1 operates as a mod-2 counter whereas the combination of flip flops FF1, FF3 and FF4 form a
mod-5 counter. There are two reset inputs R and R2 both of which have to be connected to logic
1 level for clearing all the flip flops. That two set inputs S1 and S2 when connected to logic level
1 are used for setting the counter to 1001. The basic internal structure of IC 7490 is as shown in
figure 1.

Fig. 1 Internal structure of IC 7490

From the figure above we see that each section has a separate clock input to initiate state change
of the counter on the high to low clock transition. The clock 1 input receives the incoming count
producing a BCD count sequence. The pin diagram of IC 7490 is shown below in Figure 2.

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Digital Electronics Lab (ESC-304) 2024

Counter sequence can be obtained as:

PROCEDURE:
1) Insert the IC 7490 on the breadboard.

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2) Apply vcc(+5V) to pin 5 and ground (0V) to pin 10.

3) Using function generator give the external clock pulse to clock 1, which is pin 14.
4) Connect Q1 (pin 12) to clock2 (pin 1) externally.
5) As per the pin diagram the output pin Q1 Q2 Q3 and q4 are connected to one end of 330
ohm resistor and the other end of resistor is connected to positive lag of LED. (It is
shown only for Q3 same is to be done for Q1 Q2 and Q4). Connect LED's properly, with
its negative ( longer leg) end grounded and positive end ( smaller leg) connected to one
end of the resistance.
6) The values of reset pins i.e. pin 2,3,6 and 7 should be kept high to begin the counting.
7) If the LED's are not glowing in the proper sequence then check the connections and
repeat the steps from 1 to 6.

RESULT:

……….……………………….

Signature of Staff in charge

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Digital Electronics Lab (ESC-304) 2024

EXPERIMENT NO: 10

AIM: To demonstrate the operation and verify the truth table of n5 bit ring counter.

APPARATUS REQUIRED: LED’s (5), Breadboard, Connecting wires, power supply (5V),
current limiting resistors for LEDs (330 Ω), function generator, IC 7496 (shift register).

THEORY: The circuit of a ring counter is shown in fig1. using D flip-flops. The output Q0 sets
the first flip-flop, Q1 sets the second flip-flop, Q2 sets the third flip-flop, Q3 sets the fourth flip-
flop and Q4 is fed back to the first flip-flop. Based on these connections the bits are shifted left
one position per positive edge of the clock cycle and fed back to the input. All the flip-flops are
clocked together. When Cr goes low then back to high, the output is Q=00000. The first positive
clock edge shift the MSB to LSB position and other bits to one position left so that the output
becomes Q = 00010, then the process continues till we have 10000. The next positive edge of the
clock cycle again will have Q = 00001, the stored one bit moves left through all the flip-flops
and final flip-flop sends it back to the first flip-flop. This action is the reason it is given the name
of ring counter.
It is used to control the sequence of operations in a sequence (For ex: control of stepper motor,
which requires sequential pulses to rotate it from one position to another).

Fig1. Circuit diagram for ring counter

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Digital Electronics Lab (ESC-304) 2024

Pin diagram of 7496:-

Fig2. Timing diagram of ring counter

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Digital Electronics Lab (ESC-304) 2024

Functional Table:-

PROCEDURE:-

1. Insert the IC 7496 on th3e3 breadboard and make connection as per the given circuit.
2. Apply +5 V to pin 5and GND to pin 12.
3. Clock is provided to the pin 1 through the function generator.
4. Input A, B, C, D and E (Pin 2, 3, 4, 5, 6 and 7) are connected to ground.
5. PE (Pin 8) should be kept high.
6. S & Q0 (Pin 9 and 10) should be connected externally.
___ ___
7. MR (Pin 16 ) should be kept high, then to reset all the flip flops MR should be grounded.
___
To begin counting MR should be given high again.
8. All the outputs Q0, Q1, Q2, Q3 and Q4 (Pin 10, 11, 13, 14 & 15) should be connected
through current limiting resistor of 330 Ω to LEDs to display the output.
9. In case, if the result is not verified then repeat the steps from 1 to 8.

PRECAUTIONS:

1. Don’t exceed voltage greater than 5 V

2. Connections must be proper
3. Make sure that there is no short circuit.

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RESULT:

……………….……………………….

Signature of Staff in charge

42