Computer Interfacing(CSE)

Lecture 3
Basic I/O Interface (Part 2)

Dr. Adel Agamy

[email protected]
Assistant Professor
Electrical Engineering Department
Faculty of Engineering
Aswan University
 Administration
• Instructor
Dr. Adel Agamy
• Teaching Assistant
Eng. Fatma Gamel
• References
[1] THE INTEL MICROPROCESSORS Architecture,
Programming, and Interfacing, by BARRY B. BREY
[2] Embedded System Interfacing by Marilyn Wolf
[3] Brain-Computer Interface Using Deep Learning Applications
M.G. Sumithra, Rajesh Kumar Dhanaraj, et all
 Grading System

Lecture activities 10

Section activities, performance, etc 10

Project 10

Midterms 20

Final 100

Total 150

Dr. Understanding
Adel Agamy Computers: Today and Tomorrow, 13th Edition
 Course Contents
1. Chapter 2 [2]: Standard Interfaces
2. √Chapter 10 [1]: Memory Interface
3. Chapter 11 [1]: Basic I/O Interface
4. Chapter 12 & 13 [1]:Interrupts &DMA
5. Chapter 1 [3] : introduction to BCI
8254 PROGRAMMABLE INTERVAL TIMER

• The 8254 consists of three independent

16-bit programmable counters (timers).
• Each counter is capable of counting in binary
or binary-coded decimal (BCD).
– maximum allowable input frequency to any
counter is 10 MHz
• Useful where the microprocessor must
control real-time events.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
8254 PROGRAMMABLE INTERVAL TIMER

• Usage includes real-time clocks, event

counters, and motor speed/direction control.
• Timer appears in the PC decoded at ports
40H–43H to do the following:
– 1. Generate a basic timer interrupt that occurs
at approximately 18.2 Hz
– 2. Cause the DRAM memory system to be
refreshed
– 3. Provide a timing source to the internal
speaker and other devices.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
8254 Functional Description
• Each timer contains:
– a CLK input which provides the basic operating
frequency to the timer
– a gate input pin which controls the timer in some
modes
– an output (OUT) connection to obtain the output
of the timer.
– The signals that connect to the processor are the
data bus pins (D7–D0), RD, WR, CS, and address
inputs A1 and A0.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The 8254 programmable interval timer. (a) Internal structure and (b) pin-out. (Courtesy
of Intel Corporation.)

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• Timer zero generates an 18.2 Hz signal that
interrupts the microprocessor at interrupt
vector 8 for a clock tick.
– often used to time programs and events in DOS
• Timer 1 is programmed for 15 µs, used on
the PC to request a DMA action used to
refresh the dynamic RAM.
• Timer 2 is programmed to generate a tone
on the PC speaker.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Definitions for 8254
A0, A1
• The address inputs select one of four internal
registers within the 8254. See Table 11–4 for
the function of the A1 and A0 address bits.
CLK
• The clock input is the timing source for each
of the internal counters. This input is often
connected to the PCLK signal from the
microprocessor system bus controller.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
CS
• Chip select enables 8254 for programming
and reading or writing a counter.
G
• The gate input controls the operation of the
counter in some modes of operation
GND
• Ground connects to the system ground bus.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
OUT
• A counter output is where the waveform
generated by the timer is available.
RD
• Read causes data to be read from the 8254
and often connects to the IORC signal.
Vcc
• Power connects to the +5.0 V power supply.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
WR
• Write causes data to be written to the 8254
and often connects to write strobe IOWC.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Programming the 8254
• Each counter is programmed by writing a
control word, followed by the initial count.
– fig 11–34 lists the program control word structure
• The control word allows the programmer to
select the counter, mode of operation, and
type of operation (read/write).
– also selects either a binary or BCD count

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The control word for the 8254-2 timer.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• Each counter may be programmed with a
count of 1 to FFFFH; A count of 0 is equal
to FFFFH+l (65,536) or 10,000 in BCD.
• Timer 0 is used in the PC with a divide-by
count of 64K (FFFFH) to generate the
18.2 Hz (18.196 Hz) interrupt clock tick.
– timer 0 has a clock input frequency of
4.77 MHz + 4 or 1.1925 MHz
• The order of programming is important for
each counter, but programming of different
counters may be interleaved for better control.
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Modes of Operation
– Six modes (0–5) of
available to each of
the 8254 counters
– Each mode functions
with the CLK input,
the gate (G) control
signal, and OUT
signal

The six modes of operation for the 8254-2 programmable interval timer. The G input
stops the count when 0 in modes 2, 3, and 4.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 0
• Allows 8254 to be used as an events counter.
• Output becomes logic 0 when the control
word is written and remains until N plus the
number of programmed counts.
• Note that gate (G) input must be logic 1 to
allow the counter to count.
• If G becomes logic 0 in the middle of the
count, the counter will stop until G again
becomes logic 1.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 1
• Causes function as a retriggerable,
monostable multivibrator (one-shot).
• G input triggers the counter so it develops a
pulse at the OUT connection that becomes
logic 0 for the duration of the count.
– if the count is 10, the OUT connection goes
low for 10 clocking periods when triggered
• If G input occurs within the output pulse, the
counter is reloaded and the OUT connection
continues for the total length of the count.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Mode 2
• Allows the counter to generate a series of
continuous pulses one clock pulse wide.
– pulse separation is determined by the count
• For a count of 10, output is logic 1 for nine
clock periods and low for one clock period.
• The cycle is repeated until the counter is
programmed with a new count or until the G
pin is placed at logic 0.
– G input must be logic 1 for this mode to
generate a continuous series of pulses
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Mode 3
• Generates a continuous square wave at the
OUT connection, provided the G pin is logic 1.
• If the count is even, output is high for one half
of the count and low for one half of the count.
• If the count is odd, output is high for one
clocking period longer than it is low.
– if the counter is programmed for a count of 5,
the output is high for three clocks and low for
two clocks

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 4
• Allows a single pulse at the output.
• If count is programmed as 10, output is high
for 10 clocking periods and low for one period.
– the cycle does not begin until the counter
is loaded with its complete count
• Operates as a software triggered one-shot.
• As with modes 2 and 3, this mode also uses
the G input to enable the counter.
– G input must be logic 1 for the counter to
operate for these three modes
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Mode 5
• A hardware triggered one-shot that functions
as mode 4.
– except it is started by a trigger pulse on the
G pin instead of by software
• This mode is also similar to mode 1 because
it is retriggerable.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
DC Motor Speed and Direction Control

• An application of 8254 is as a motor speed controller for a DC

motor.
• The interconnection of the 8254, a flip-flop, and the motor and
its driver.
• if Q output of the 74ALS112 is logic 1, the motor spins in its
forward direction
• if logic 0, the motor spins in reverse
• if flip-flop output alternates between
logic 1 and 0, the motor spins in either direction at various speeds
• if the duty cycle of the Q output is 50%, the motor will not spin at
all and exhibits some holding torque

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
16550 PROGRAMMABLE COMMUNICATIONS
INTERFACE

• National Semiconductor Corp’s PC16550D

is a programmable communications interface
designed to connect to virtually any type of
serial interface.
• 16550 is a universal asynchronous
receiver/transmitter (UART) fully compatible
with Intel microprocessors.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• 16550 operates at 0–1.5 M baud.
– baud rate is bps (bits transferred per second)
including start, stop, data, and parity
– bps are bits per second; Bps is bytes per second
• 16550 also includes a programmable baud
rate generator and separate FIFOs for input
and output data to ease the load on the
microprocessor.
• Each FIFO contains 16 bytes of storage.
• The most common communications interface
found in the PC and many modems.
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Asynchronous Serial Data
• Asynchronous serial data are transmitted and
received without a clock or timing signal.
– shown here are two frames of asynchronous
serial data
– each frame contains a start bit, seven data bits,
parity, and one stop bit

Asynchronous serial data.

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Barry B. Brey
• Dial-up communications systems of the past,
such as CompuServe, Prodigy, and America
Online, used 10 bits for asynchronous serial
data with even parity.
• Most Internet and BBS services use 10 bits,
but normally do not use parity.
– instead, eight data bits are transferred, replacing
parity with a data bit
• This makes byte transfers of non-ASCII data
much easier to accomplish.

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Barry B. Brey
16550 Functional Description
• The device is available as a 40-pin DIP
(dual in-line package) or as a 44-pin PLCC
(plastic leadless chip carrier).
• Two completely separate sections are
responsible for data communications.
– the receiver and the transmitter
• Because each sections is independent, 16550
is able to function in simplex, half-duplex, or
full-duplex modes.

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Barry B. Brey
The pin-out of the 16550 UART.

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Barry B. Brey
• A major feature of the 16550 is its internal
receiver and transmitter FIFO (first-in, first-
out) memories.
• Because each is 16 bytes deep, the UART
requires attention from the processor only
after receiving 16 bytes of data.
– also holds 16 bytes before the processor
must wait for the transmitter
• The FIFO makes this UART ideal when
interfacing to high-speed systems because
less time is required to service it.
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Barry B. Brey
• A simplex system is one in which the
transmitter or receiver is used by itself.
– such as in an FM (frequency modulation)
radio station
• A half-duplex system is a CB (citizens
band) radio.
– transmit and receive, but not at the same time
• A full-duplex system allows transmission
and reception in both directions
simultaneously.
– the telephone is a full-duplex system
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Barry B. Brey
• The 16550 can control a modem
(modulator/demodulator), a device that
converts TTL serial data into audio tones
that can pass through the telephone system.
• Six pins on 16650 are for modem control:
DSR (data set ready), DTR (data terminal
ready), CTS (clear-to-send), RTS (request-
to-send), RI (ring indicator), and DCD (data
carrier detect).
• The modem is referred to as the data set and
the 16550 is referred to as the data terminal.
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
16550 Pin Functions
A0, A1, A2
• The address inputs are used to select an
internal register for programming and also
data transfer.

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Barry B. Brey
ADS
• The address strobe input is used to latch
the address lines and chip select lines.
• If not needed (as in the Intel system),
connect this pin to ground.
• The ADS pin is designed for use with
Motorola microprocessors.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
BAUDOUT
• The baud out pin is where the clock signal
generated by the baud rate generator from
the transmitter section is made available.
• It is most often connected to the RCLK input
to generate a receiver clock that is equal to
the transmitter clock.

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CS0, CS1, CS2
• The chip select inputs must all be active to
enable the 16550 UART.
CTS
• The clear-to-send (if low) indicates that the
modem or data set is ready to exchange
information.
• This pin is often used in a half-duplex system
to turn the line around.

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D0–D7
• The data bus pins are connected to the
microprocessor data bus.
DCD
• Data carrier detect input is used by the
modem to signal the 16550 that a carrier
is present.

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DTR
• Data terminal ready is an output that
indicates that the data terminal (16550)
is ready to function.
INTR
• Interrupt request is an output to the
microprocessor used to request an interrupt
(INTR=1) when the 16550 has a receiver
error, it has received data, and the
transmitter is empty.
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Barry B. Brey
DDIS
• The disable driver output becomes logic 0
to indicate the microprocessor is reading
data from the UART.
• DDIS can be used to change the direction
of data flow through a buffer.

DSR
• Data set ready is an input to the 16550,
indicating that the modem or data set is
ready to operate.
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MR
• Master reset initializes the 16550 and should
be connected to the system RESET signal.

OUT1, OUT2
• User-defined output pins that can provide
signals to a modem or any other device as
needed in a system.
RCLCK
• Receiver clock is the clock input to the
receiver section of the UART.
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Barry B. Brey
RD, RD
• Read inputs (either may be used) cause data
to be read from the register specified by the
address inputs to the UART.
RI
• Ring indicator input is placed at logic 0 by
the modem to indicate the phone is ringing.

RTS
• Request-to-send is a signal to the modem
indicating that the UART wishes to send data.
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
SIN, SOUT
• These are the serial data pins. SIN accepts
serial data and SOUT transmits serial data.

RXRDY
• Receiver ready is a signal used to transfer
received data via DMA techniques.

TXRDY
• Transmitter ready is a signal used to
transfer transmitter data via DMA.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
WR, WR
• Write (either may be used) connects to the
microprocessor write signal to transfer
commands and data to the 16550.

XIN, XOUT
• These are the main clock connections.
• A crystal is connected across these pins to
form a crystal oscillator, or XIN is connected
to an external timing source.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Programming the 16550
• Programming is a two-part process & includes
the initialization dialog and operational dialog.
• In the PC, which uses the 16550 or its
programming equivalent, I/O port addresses
are decoded at 3F8H - 3FFH for COM port 0
and 2F8H - 2FFH for COM port 2.

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Initializing the 16550
• Initialization dialog after a hardware or
software reset, consists of two parts:
– programming the line control register
– programming the baud rate generator
• The line control register selects the number
of data bits, stop bits, and parity (whether
even or odd, or if parity is sent as a 1 or a 0)
• Baud rate generator is programmed with a
divisor that determines the baud rate of the
transmitter section.
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UART Errors
• Errors detected by 16550 are:
– parity, framing, and overrun errors
• These errors should not occur during
normal operation.
• A parity error indicates the received data
contain the wrong parity.
– if a parity error occurs, it indicates noise
was encountered during reception

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• A framing error indicates the start and stop
bits are not in their proper places.
– occurs if the receiver is receiving data at
an incorrect baud rate
• An overrun error indicates data have
overrun the internal receiver FIFO buffer.
– occurs only if the software fails to read the data
from the UART before the receiver FIFO is full

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ANALOG-TO-DIGITAL (ADC)
& DIGITAL-TO-ANALOG (DAC) CONVERTERS
• These devices are used to interface the
microprocessor to the analog world.
• Many events monitored and controlled by
the microprocessor are analog events.
• These range from monitoring all forms of
events, even speech, to controlling motors
and like devices.

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The DAC0830 Digital-to-Analog Converter

• A fairly common and low-cost digital-to-analog

converter is the DAC0830.
– a product of National Semiconductor Corp
• An 8-bit converter that transforms an 8-bit
binary number into an analog voltage.
• Other converters are available that convert
from 10-, 12-, or 16-bit binary numbers into
analog voltages.

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• The number of voltage steps generated by
the converter is equal to the number of
binary input combinations.
– an 8-bit converter generates 256 voltage levels
– a 10-bit converter generates 1024 levels
• The DAC0830 is a medium-speed converter
that transforms a digital input to an analog
output in approximately 1.0 µs.

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pin-outs of a DAC0830.
• The device has eight data bus connections
for the application of the digital input code.
• Analog outputs labeled IOUT1 & IOUT2 are
inputs to an external operational amplifier.
• Because this is an 8-bit converter, its output
step voltage is defined as –VREF (reference
voltage), divided by 255.
– the step voltage is often called the resolution
of the converter

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The pin-out of the DAC0830 digital-to-analog converter.

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Connecting the DAC0830 to the
Microprocessor.
• A PLD is used to decode the DAC0830 at I/O
port address 20H.
– when an OUT 20H,AL instruction is executed,
contents of data bus connections AD0–AD7 are
passed to the converter in the DAC0830
• The 741 operational amplifier, along with the –
12 V zener reference voltage, causes the full-
scale output voltage to equal +12 V.

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A DAC0830 interfaced to the 8086 microprocessor at 8-bit I/O location 20H.

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The ADC080X Analog-to-Digital Converter

• A common, low-cost ADC, compatible with a

wide range of microprocessors.
– while there are faster ADCs available with more
resolution, this device is ideal for applications
that do not require a high degree of accuracy
• ADC080X requires up to 100 µs to convert an
analog input voltage into a digital output code.

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The pin-out of the ADC0804 analog-to-digital converter.

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The Analog Input Signal
• Before ADC0804 can be connected, the two
analog inputs must be understood:
– VIN(+) and VIN(–)
• These differential inputs are summed by the
operational amplifier to produce a signal for
the internal analog-to-digital converter.
• These inputs are connected to an internal
operational amplifier.

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The analog inputs to the ADC0804 converter. (a) To sense a 0- to +5.0 V input. (b) To
sense an input offset from ground.

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Connecting the ADC0804 to the Microprocessor

• ADC0804 interfaced to an 8086.

– VREF is not attached to anything, which is normal
• Suppose ADC0804 is decoded at I/O port
address 40H for the data and address 42H
for INTR.

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The ADC0804 interfaced to the 8086 microprocessor.

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Using the ADC0804 and the DAC0830

• This illustrates an example using an ADC0804

and a DAC0830 to capture and replay audio
signals or speech.
– a speech synthesizer has been used in the past
to generate speech, but quality was poor
• For human quality speech, we can use an
ADC0804 to capture an audio signal and
store it for later playback through a DAC0830.

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• circuitry required to connect the ADC0804 at
I/O ports 0700H and 0702H.
• The DAC0830 is interfaced at I/O port 704H.
– These ports are in the low bank of a 16-bit
microprocessor such as the 8086/80386SX
• It reads a 1-second burst of speech and
plays it back 10 times.

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• A procedure called READS reads the speech.
• A second, PLAYS, plays it back.
• The speech is sampled and stored in a
section of memory called WORDS.
• The sample rate is chosen at 2048 samples
per second, which renders acceptable-
sounding speech.

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A circuit that stores speech and plays it back through the speaker.

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SUMMARY
• The 8254 is a programmable interval timer
with three 16-bit counters that count in
binary or binary-coded decimal (BCD).
• Each counter is independent and operates
in six different modes: (1) events counter,
(2) retriggerable, monostable multivibrator,
(3) pulse generator, (4) square-wave
generator, (5) software-triggered pulse
generator, and (6) hardware-triggered pulse
generator.
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SUMMARY
• The 16550 is a programmable
communications interface, capable of
receiving and transmitting asynchronous
serial data.
• The DAC0830 is an 8-bit digital-to-analog
converter that converts a digital signal to an
analog voltage within 1.0 µs.
• The ADC0804 is an 8-bit analog-to-digital
converter that converts an analog signal
into a digital signal within 100 µs.
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