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Congestion in VLSI Physical Design Flow: Technologies

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18 views

Congestion in VLSI Physical Design Flow: Technologies

Uploaded by

Amora Castillo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LMR

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Congestion in VLSI
Physical Design Flow

by Jarmo

May 8, 2021
1.4k
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Here let us discuss about congestion. What is Congestion? What are


the reasons for Congestion? How congestion can be fixed?

What is Congestion?
If the number of routing tracks available for routing in one particular
area is less than the required routing tracks then the area said to be
congested. There will be a limit for number of nets that can be routed
through particular area.

LiittyvätViestit
Floorplanning
Static Timing Analysis (STA) Overview
Physical Design Flow

What are the reasons for


Congestion?
 High Standard cell density in small area
 Placement of standard cells near macros
 High pin density at the edge of macro
 Bad floorplan
 During IO optimization tool does buffering, So lot of cells placed
in the core area

How congestion can be Analysed?


Congestion can be analysed by using congestion map as shown below
figure.
If the congestion is not too severe, The actual route can be detoured
around congested area. The detoured nets will have worse RC delays
than actual VR estimates.

If the congestion is too severe, the design can be un-routable. This is


really not good. It is important to minimize or eliminate the congestion
before continuing.

How to fix Congestion?


 Rerun the fast placement with Congestion driven option
(Congestion driven placement)
 Modify physical constraints such as adjust cell density in
congested areas. Because higher cell density cause for
congestion.
 Use/Modify proper blockages. i.e., Soft blockages, Hard
blockages, Macro Padding are used proper locations to minimize
the congestion near macros.
 Modify floorplaning such as moving macros, change core
shape/size, Move pins to give enough room for routing

What happens during congestion


driven placement?
As discussed earlier, Congestion driven placement is performed to
reduce the congestion. During congestion driven placement, the cells
(Higher cell density) which caused for congestion are spread apart. If
the cells along timing critical paths are spread apart to minimize
congestion, What happens?

If the cells along timing critical paths spread apart, the timing
constraints along that particular paths are not met which cause for
timing violations. But these violations can be fixed during incremental
optimization.

What are the care should be taken


using congestion driven option?
 If there is some congestion, use medium effort option
 If the congestion is bad, use high effort option
 If there is no congestion, Don’t use congestion driven option. If
we use congestion driven option in this case, It takes more rum
time for placement.

How modify physical constraints


reduce congestion?
As discussed earlier, Higher cell density can cause for congestion. By
default the cell density can be upto 95%. We can reduce the cell
density at congested areas by using coordinate option.
As shown in below figure, we can set cell density to a flexible number
to reduce the congestion by using the command.

set_congestion_options – max_util 0.6\ – coordinate {x1 y1 x2 y2}


Here we set the maximum cell density upto 60% and given the
coordinates for the particular area.

How blockages and macro


padding(Halos) reduce congestion?
By using blockages and halos, They prevent the tool placing cells in
that particular locations to give enough space for routing near the
macros. For more details, please refer Blockages halos post.
Soft Blockages created only for the channels between macros (or)
Between macro & the core boundary to give enough space for routing.
Hard blockages always created on the four sides of macro for not to
place standard cells or macros near to the macro.
Macro Padding: If the design contains macros that are not placed
near another macro (or) the edge of the core then macro
padding(Halo) is created. Standard cells cant be placed in this region
which give more routing resources to the signal routes.

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