FlexNoC Training

FLEXVERIFIER UVM

GARY GE
Solution Architect
[email protected]
+86 185-0151-0645
 FlexNoC design flow

Specification
sockets
floorplan domains traffic
outline memory map scenario

Physical FlexExplorer
Architecture use case performance
LEF/DEF, switch topology
auto pipe, QoS, buffers
placement serialization

Structure
RTL, SystemC
IP-XACT
scripts/constraints
FlexVerifier
gates testbench
P&R Synthesis tests
estimate

2
Overview

• Compliant to UVM Automatically

generated
• Multi-vendor third-party VIP support from FlexNoC

– Synopsys with VCS simulator System Supports all

Verilog Open standard
– Cadence with Ncsim simulator Configuration sockets

• Supports all standard sockets FlexVerifier

UVM
• Memory controller protocol support
User-
– Databahn, NIF, Uniquify, HIF(SNPS) Compliant to
extendable
UVM
verification
methodology
environment
• User may extend the test environment
– New tests Qualified IP
– New scoreboard checks

ARTERIS CONFIDENTIAL 3
Verification Strategy
• ARTERIS ensures correctness of delivered IP
– Unit Level Testing for each and every element of the library
– Software regression
– Integration regression using FlexVerifier environment

• Customer ensures that FlexNoC PDD configuration is implementing their specification

Customer
Specification

Customer Design Customer

Team Verification Team

Validates
Implements
Validation txt files
FlexNoC UVM RTL
Generates Testbench
configuration Design

ARTERIS CONFIDENTIAL 4
Validation files
• Generated by FlexNoC using PDD configuration in txt/ directory
– Memory Map (MemoryMap.txt)
– Register Map and reset values (RegisterAccesses.txt)
– Probing infrastructure to ATB interface (ProbeConnectivity.txt and ProbeConf.txt)
– Power Domain definition (PowerDomains.txt)

• Other PDD information are in sv/anvu_noc_definitions_pkg.sv

– Socket name, protocol, index
– User bit mapping
– OCP rtl.conf file name

• Must be replaced/validated by customer to ensure correctness of the PDD configuration versus

customer specification

ARTERIS CONFIDENTIAL 5
Testbench generation and
usage

ARTERIS CONFIDENTIAL 6
FlexNoC Integration
• A NoC Structure view is required
• A HDL export with VCS or NCSIM simulator option must be created
• Export tool command via GUI menu or batch (command line)
• Built and run from the shell
– Makefile is generated

ARTERIS CONFIDENTIAL 7
Running a test
• Building/Simulating
– make compilation
– make tests (run all tests)
– make <testname>
– ./runUvmTestEnv.sh <testname> <logfileName> “<socketName> …” (run test
limited to selected sockets or with additional options)
• Logs files
– <logfileName> default to <testname>.log. Complete log file
– <logfileName_anvu.log> default to <testname>_anvu.log. Extracted Arteris log
from complete log
• Configuration files
– anvu_build_options.mk (compilation options)
– anvu_sim_options.sh (simulation options, UVM verbosity)
– anvu_sim_waves.tcl (waveform dumping VCS only)
– anvu_build_files.base (sources files for the simulation)
– user_scoreboard_overloads.sv (User defined scoreboard override)
– user_tests_pkg.sv (User defined tests)

ARTERIS CONFIDENTIAL 8
Summary of built-in tests
Test name Description
Send a 1 word Read then Write per valid connection. Scoreboard will compute the
latency
latencies at the end of the test.
Send a 128B burst Read then Write per valid connection. Scoreboard will compute the
throughput
throughput at the end of the test.
Send a 1 word Read then Write at the beginning and at the end of each mapping defined in
connectivity
the txt/MemoryMap.txt file.
Same as connectivity with Slave VIP configured to respond in error and only testing the
connectivityWithSlvError
connection that goes out of the interconnect.
userBit Send transactions varying the user bit for each initiator.
Send transactions from each initiator to each target with varying transaction parameter to
thorough
extensively cover the protocol.
random Random transactions per initiator flow sent concurrently
Run a connectivity test while going through all the possible power state combinations
power
defined in txt/PowerDomain.txt
Configure and exercise all probes connected to an ATB output using txt/ProbeConf.txt and
probeConnectivity
txt/ProbeConnectivity.txt
Reading file txt/RegisterMap.txt, do a read-write-read-reset tests to verify configuration
registerMap
registers.
flowControl Configure VIP to do flowControl while sending transaction one initiator at a time

9
Running test with optional arguments

• ./runUvmTestEnv.sh <testname> <logfileName> “<option0> …”

– Pass option0 as argument of +anvu_test_options

• Use socketName to limit the test to those sockets

– Ex: ./runUvmTestEnv.sh anvu_throughput_test throughput “myInit0 myTarget0” only run throughput
test between myInit0 and myTarget0

• Change the timeouts for the scoreboard and VIPs

– timeout=NewTimeout change the timeout for VIP to finish their transactions before NewTimeout cycle of
slowest clock
– scTimeout=NewTimeout change the timeout for the scoreboard to be empty before NewTimeout cycle
of slowest clock
– Ex: ./runUvmTestEnv.sh anvu_throughput_test throughput “myInit0 myTarget0 timeout=200000
scTimeout=300 ”

ARTERIS CONFIDENTIAL 10
UVM classes and file hierarchy

ARTERIS CONFIDENTIAL 11
 FlexVerifier UVM test hierarchy

VIP master agent

VIP slave agent

Scoreboard and scoreboard

abstractors
SB recalls external C++
A Verilog wrapper
functions
including AIP VIF and
CM (ClkManager)

Anvu_uvmTest_Env_Top RTL
Another Verilog wrapper
including VIP VIF and ClkGen

ARTERIS CONFIDENTIAL 12
Files hierarchy
• anvu_uvmTestEnv_Top.v
– SV interfaces to anvu_bench_env
– x_Dut_x: (nocAIP) Instrumented NoC
• xUser_Tesed_NoCx: Verilog DUT
• SV interfaces to anvu_nocAIP_env

• anvu_sim_options.sh, anvu_build_options.mk
– Simulation and compilation options (waves, UVM
verbosity)

• Makefile
– Compilation and simulation of the different tests

• Sv/*: System Verilog sources

• Txt/*: Regression validation files
– Memory Map (MemoryMap.txt)
– Register Map and reset values
(RegisterAccesses.txt)
– Probing infrastructure to ATB interface
(ProbeConnectivity.txt and ProbeConf.txt)
– Power Domain definition (PowerDomains.txt)

ARTERIS CONFIDENTIAL 13
anvu_top_env

• anvu_top_env.v
– Instantiate (build_phase):
• Active bench
• anvu_bench_env
• Passive scoreboarding bench
• anvu_nocAip_env
• anvu_virtual_sequencer

• Assign VIP virtual interfaces to interfaces in Verilog modules

– SV interfaces are set in the UVM Configuration Database space
– Allow association : interfaces in verilog modules <=> interfaces in SV VIPs
`ANVU_SET_CONFIG( virtual svt_ahb_master_if , Int_In_AHB ,
"In_AHB_benchIf");
• VIP Sequencers put in the virtual sequencer arrays, for easy access
for (int i=0;i<nocAhbInitNb;i++) begin
virtual_sequencer.ahbSequencer.push_back(bench.ahbInitVip[i].sequencer);
end

ARTERIS CONFIDENTIAL 14
Clocking scheme

• Socket VIP clocks = Real NIU clocks in the NoC

• ClkGenerator instantiated in top bench module.

– Inputs : anvu_clk_if SV interfaces (Clk, Sel) driven by
anvu_clk_driver VIP

• 2 modes
– Sel==1 : Clock driven by SV anvu_clk_if.Clk
– Sel==0 : Clock driven by internal oscillator

• anvu_clk_driver (./anvu_xactors_pkg.sv)
– setFrequency(...)
– driveFromVerilog() / driveFromTestBench() : to control Sel
– startClock()
– stopClock()

• allows frequency to be changed at run time.

15
Virtual sequence synchronization
mySquence
blocked myDriver //connected to mySequencer
body()
myVirtualSquencer blocked run_phase()
`uvm_create(req)
body() get_enxt_item(req)
req.randomize()
DriveSignals
`uvm_send(req)
mySequence.start(mySequencer) item_done()
next… released
next… released next…
endtask

• item_done called by driver releases the sequencer/sequence and then the virtual sequence
• Caution : item_done() usually called by the driver when the request phase is finished (AXI,OCP...).
– a sequence can be finished but there are still responses in the NoC
top.wait_flow(flow,nbCycles);
– Waits until all transactions sent by initiator « flow » sequencer are finished
– Raise a uvm_error after nbCycles if transactions are still pending
– Uses typically events from VIPs
top.wait_flows(nbCycles);
– wait until all transactions sent by all sequencers have finished

• This works in most cases. But problems with early responses (ex : OCP WR)
– OCP Driver will consider a transaction complete at the end of the request
– It will trigger the event for wait_flow, but there are still req/rsp in NoC
top.wait_scoreboard_empty();
– Waits until the scoreboard has no pending transfers

• Need to use both synchronization methods at the end of virtual sequence

ARTERIS CONFIDENTIAL 16
End to end scoreboard
verification component

ARTERIS CONFIDENTIAL 17
Scoreboard
• Receive ByteTransfer from nocAIP initiator and target monitors

• Each ByteTransfer contains:

– StartDate/DataDate/EndDate
– Opcode/address/status/data/userBit

• When transaction ends:

– ByteTransfer is feed to the scoreboard
– InitiatorByteTransfer are predicted following MemoryMap.txt definition
– Detected initiator BT are associated with Detected target BT

ARTERIS CONFIDENTIAL 18
Scoreboard prediction
• Uses prediction mechanism
– Each initiator BT is predicted to exit NoC through a known
socket, address, …
– If a target BT matches this prediction, then association is
validated
– An initiator BT can also be predicted not to exit the NoC

• Any remaining BTs that could not be associated are

declared ″orphans″
Predicted to target T0
Initiator I0 StartTransaction BT0 BT1 BT2 BT3 EndTransaction

Association BT0
Association BT1
Association BT2
Association BT3
Send 4B
Read
Simulation time
Target T0
Receive
4B Read StartTransaction BT0 BT1 BT2 BT3 EndTransaction

ARTERIS CONFIDENTIAL 19
Scoreboard user overloads

• Stored in user_scoreboard_overloads.sv

• Allow to override default behavior of the scoreboard to accommodate with specific behavior:
– Firewalls / Transaction conversion

• userPredictAddress change prediction (Firewall, …)

– Keep the same level of verification

• userQualifyInitiatorOrphan and userQualifyTargetOrphan

– Override criteria for acceptance of Orphan
– Warning, this will lower the verification level

• Commonly used override are provided for FlexNoC interconnects:

– Stream to Stream/NonStream conversion, Byteen, …

ARTERIS CONFIDENTIAL 20
Example overload explanation
• For scoreboard helper function allowTargOrphan_TargNoByteen in
sv/anvu_scoreboard_pkg.sv
– Protocol is selected using nocSocketTypeByFlowId and the target flowId
– You can then proceed to protocol specific functions
function bit allowTargOrphan_TargNoByteen(anvu_nocAip_byteTransfer targTransfer,string targSocketName);
anvu_flow targFlow = targTransfer.m_flow;
bit targSupportBe = 1;
case (nocSocketTypeByFlowId[targFlow.id()])
OCP : begin
anvu_ocp_monitor_transaction ocpTr;
$cast(ocpTr,targTransfer.m_transaction);
targSupportBe = (ocpTr.ocpConf.byteen && nocOcpTargInfoByFlowId[targFlow.id()]==0 ) ||
ocpTr.ocpConf.mdatabyteen;
end
endcase

return (
targTransfer.m_opcode == anvu_noc_definitions_pkg::WRITE
&& !targSupportBe
&& ( targSocketName == "" || targFlow.isFrom(targSocketName) )
);
endfunction

ARTERIS CONFIDENTIAL 21
Scoreboard log analysis
Req Data Rsp
Socket name: Flow Address Opcode Status Value
time time time

[anvu_nocAip] Feeding Out_APB:00 f2cc4d40 RD V 07 [361000: 371000: 371000] –

[anvu_nocAip] Feeding In_AXI:00 f2cc4d40 RD V 07 [341000: 411000: 411000] -

User 0000000
[anvu_nocAip] Predict In_AXI:00 f2cc4d43 RD V 52 [341000: 411000: 411000] -
User 0000000 to Out_APB:00 00000000f2cc4d43 - force WrP 0
[anvu_nocAip] QualifyAssociation 1 -
In_AXI:00 f2cc4d42 RD V 85 [341000: 411000: 411000] -
User 0000000 with
Out_APB:00 f2cc4d42 RD V 85 [361000: 371000: 371000] -

ARTERIS CONFIDENTIAL 22
Thank you

23
ARTERIS CONFIDENTIAL