ADVD-CMOS Process
ADVD-CMOS Process
Electronics Engineering
Many more
under review
EEE F313
Lateral diffusion
Under cutting
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Important Milestones in IC Fabrication
Transistor
Electron Discovery Vacuum tube Elec.
Bardeen, Brattain, &
Thompson (1897) Early 20th century
Shockley (1947)
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What is an IC?
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What is an IC?
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What constitute a Silicon Chip?
• Connections from the chip to the outside world are made around the edge
of the chip to facilitate connections to other devices
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• This chapter will discuss the “making of a chip.”
• Journey of Sand (cost penny) to one of the most strategically important
components in today’s world, i.e., IC or chip.
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Fabrication Technology
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Cont..
• The most important element in any IC is the active component like BJT or
MOSFET.
• Very High Speed → BJT
• Packing Density → MOSFETs
VLSI
Technology
1. We will get familiar with all process steps needed to realize these
technologies.
2. Then we will discuss all the process steps individually in detail.
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Fabrication laboratory
Clean room
❖ Class 1000
❖ Class 100
❖ Class 10
❖ Class 1
➢ Wet bench
➢ Oxidation furnaces
➢ Glove box
➢ Lithography system
➢ Doping system
➢ Etching system
➢ Deposition system
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MOSFET
S D
S D
❖ N-well,
❖ P-well,
❖ Twin-tub process.
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Oxidation
❖ Active applications
❖ Passive applications
➢ Dry oxidation
➢ Wet oxidation
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Oxidation
XFOX
0.54 XFOX Silicon surface
0.46 XFOX
Silicon wafer
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Lithography
❖ Diazonapthaquinone ❖ SU-8
(DQ) ❖ Methyl methacrylate
❖ t-BOC
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Spin Coater
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Etching
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Doping
• Ion Implantation
• Diffusion
• In-situ doping
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Ion-implantation
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Diffusion
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Deposition Example: Sputtering
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MOS processing steps
❖ Wafer cleaning
❖ Oxidation
❖ Lithography
❖ Etching
❖ Doping (N-well, P-well, Twin-tub process)
❖ Metallization
❖ Packaging
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NMOS
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PMOS
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NMOS fabrication
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• CMOS: Putting NMOS and PMOS together.
• Individual devices should not interact with each other
except through metal interconnections.
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Isolation
• Resistivity
Spin Coating
LPCVD
Oxidation
• Substrate selection: moderately
high resistivity, (100) orientation,
P type.
• Wafer cleaning, thermal oxidation
(≈ 40 nm), nitride LPCVD
deposition (≈ 80 nm), photoresist
spinning and baking (≈ 0.5 - 1.0 µm).
Tensile strain
Compressive strain
n-well
p-type
Solution: Thinner
oxide SiO2
Poly-buffered oxide
Bird’s beak: Concerning for small active devices
Prevents oxidation
PR removal
+
Oxidation
CMP
• A crucial step in CMOS fabrication as this will affect and decide the
VTH value.
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Gate Formation: VTH adjusted
• Polysilicon is deposited
by LPCVD ( ≈ 0.5 µm). An
unmasked P+ or As+ implant
dopes the poly (typically
5 x 1015 cm-2).
𝑺𝒊𝑯𝟒 → 𝑺𝒊 + 𝟐𝑯𝟐
Poly-Si doping:
• Implantation
• In-situ doping
n-well
p-type
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LDD formation
• Ti is deposited by
sputtering (typically
100 nm).
• The Ti is reacted in an
N2 ambient, forming TiSi2
and TiN (typically 1 min
@ 600 - 700 ˚C).
• A conformal layer of
SiO2 is deposited by
LPCVD (typically 1 µm).
• CMP is used to
planarize the wafer
surface.
• Al is deposited on the
wafer by sputtering. Mask
#13 is used to pattern the
Al and plasma etching is
used to etch it.
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Current Status
Many more
under review
• There are many more fab setup (KAYNES, Suchi Semicon, etc.) missing in
the map
• Mostly OSAT.
• Aiming for 28 nm node.
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Emerging Options: More Moore &
More than Moore
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Reasons—
Output D S
GND VDD
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Positive feedback loop----
Equivalent Circuit
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Latchup in Bulk CMOS
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Sources of latchup
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Remedies
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Reduce the gain product β1 x β2
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Campus
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Standrd cell template for avoiding latchup
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• Make sure power supplies are off before plugging a board.
Avoid large transients
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Summary
• There are many variations on CMOS process flows used in industry. The
process described here is intended to be representative, although it is
simplified compared to many current process flows.
Thank You