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ADVD-CMOS Process

ADVD-CMOS Process

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0% found this document useful (0 votes)
26 views99 pages

ADVD-CMOS Process

ADVD-CMOS Process

Uploaded by

f20221197
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Department of Electrical and

Electronics Engineering

BITS Pilani Dr. Rahul Kumar,


Pilani Campus
Assistant Professor
BITS Pilani
Pilani Campus

Analog & Digital VLSI Design


CMOS Process Flow
Motivation and Relevance

Many more
under review

• Massive R&D in Semicon Tech. to attract global IC manufacturing


companies.
• Large scale education and skill development programs, such as this course,
to ready the required talent pool.
• India’s success in semicon industry depends on the availability of skilled
manpower.
EEE F313
Why should Designer know the fab?

• Design performance varies after fab.


• Due to process variations-

❖Dimensions vary due to shifting of masks,


❖Dopants diffusing beneath the masks,
❖Undercutting during wet etching.

• Hence MOS parameters like gm, W, L, ID varies . So


we have to design with sufficient margins.

EEE F313
Lateral diffusion

Under cutting

EEE F313 5
Important Milestones in IC Fabrication

Transistor
Electron Discovery Vacuum tube Elec.
Bardeen, Brattain, &
Thompson (1897) Early 20th century
Shockley (1947)

First microprocessor First IC


MOSFET (1963)
Intel 4004 (1971) Jack Kilby (1958)

Extreme and Deep


FinFETs (2010)
UV Litho (1990s)

EEE F313 6
What is an IC?

An IC can also be defined as a complex set of tiny components and


their interconnection that are imprinted on to a tiny slice of
semiconductor material.

EEE F313 7
What is an IC?

• An integrated circuit (IC, also called a chip) is a piece of


semiconductor wafer on which several smaller electronic devices such
as resistors, capacitors, diodes and transistors are fabricated.
• The interconnection of these devices inside the IC forms electrical
circuits which can altogether function as an amplifier, oscillator, timer,
counter, logic gate, computer memory, microcontroller or
microprocessor.

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EEE F313https://learn.sparkfun.com/tutorials/integrated-circuits/all
What constitute a Silicon Chip?

• A pattern of interconnected switches and gates on the surface of a crystal


of semiconductor (typically Si)

• These switches and gates are made of


-areas of n-type silicon
-areas of p-type silicon
-areas of insulator
-lines of conductor (interconnects) joining areas together
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten

• The geometry of these areas is known as the layout of the chip

• Connections from the chip to the outside world are made around the edge
of the chip to facilitate connections to other devices
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EEE F313
• This chapter will discuss the “making of a chip.”
• Journey of Sand (cost penny) to one of the most strategically important
components in today’s world, i.e., IC or chip.

EEE F313 10
Fabrication Technology

• Silicon of extremely high purity chemically purified then grown into


large crystals
• Wafers
➢ crystals are sliced into wafers
➢ wafer diameter is currently 150mm, 200mm, 300mm
➢ wafer thickness <1mm
➢ surface is polished to optical smoothness
• Wafer is then ready for processing
• Each wafer will yield many chips
➢ chip die size varies from about 5mmx5mm to 15mmx15mm
➢ A whole wafer is processed at a time

EEE F313 11 BITS Pilani, Pilani Campus


Czochralski
(Cz) process

EEE F313 https://www.mpechicago.com/high-purity-silicon-grinding/ 12 BITS Pilani, Pilani Campus


Growth of crystalline silicon
wafer: Czochralski (Cz) process

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EEE F313 BITS Pilani, Pilani Campus
Cont..
• The most important element in any IC is the active component like BJT or
MOSFET.
• Very High Speed → BJT
• Packing Density → MOSFETs
VLSI
Technology

BJT MOSFET BIMOS /


Technology Technology BICMOS

1. We will get familiar with all process steps needed to realize these
technologies.
2. Then we will discuss all the process steps individually in detail.
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EEE F313 BITS Pilani, Pilani Campus
Fabrication laboratory

Clean room
❖ Class 1000
❖ Class 100
❖ Class 10
❖ Class 1
➢ Wet bench
➢ Oxidation furnaces
➢ Glove box
➢ Lithography system
➢ Doping system
➢ Etching system
➢ Deposition system

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EEE F313 BITS Pilani, Pilani Campus
MOSFET

EEE F313 16 BITS Pilani, Pilani Campus


CMOS Process Flow

S D

S D

• Standard twin-well process includes16 photolithography and more


than 100 process steps are required to fabricate this simple circuit.
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EEE F313 BITS Pilani, Pilani Campus
Twin-well
N-well

❖ N-well,
❖ P-well,
❖ Twin-tub process.

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Oxidation

❖ Active applications
❖ Passive applications

➢ Dry oxidation

➢ Wet oxidation

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EEE F313 BITS Pilani, Pilani Campus
Oxidation

❖ LOCOS (Local oxidation


of Silicon)
❖ STI (Shallow Trench
Isolation)
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EEE F313 BITS Pilani, Pilani Campus
• Silicon oxidation is obtained by:
– Heating the wafer in a oxidizing atmosphere:
• Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)
• Oxidation consumes silicon
– SiO2 has approximately twice the volume of silicon
– The FOX recedes below the silicon surface by 0.46XFOX
Field oxide

XFOX
0.54 XFOX Silicon surface
0.46 XFOX

Silicon wafer

EEE F313 21 BITS Pilani, Pilani Campus


Oxidation

• Lower oxidation rate for dry oxidation.

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EEE F313 BITS Pilani, Pilani Campus
Lithography

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Lithography
❖ Lithography is a process to transfer the desired pattern of IC on the wafer.

❖ Diazonapthaquinone ❖ SU-8
(DQ) ❖ Methyl methacrylate
❖ t-BOC

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EEE F313 BITS Pilani, Pilani Campus
Spin Coater

Oven Optical Lithography System


EEE F313 25 BITS Pilani, Pilani Campus
Extreme UV Lithography

• Reducing the wavelength of light


used in photolithography
can improve resolution and allow
for smaller features.
• UV lithography.
• Extreme UV lithography.
• E-beam Lithography.
• X-ray Lithography.

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EEE F313 BITS Pilani, Pilani Campus
Etching

Process of removing materials from selected area of wafer.

Wet: Chemicals Dry: Plasma and Reactive ion etching

• Important factors: Degree of Anisotropy and selectivity


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Etching example

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Doping

• Ion Implantation
• Diffusion
• In-situ doping

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Ion-implantation

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Diffusion

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Deposition

➢ Metallization: Thermal evaporator, E-beam evaporator, sputtering


➢ Si3N4 growth: PECVD
➢ SiO2 growth: LPCVD
➢ Silicon growth: MOCVD, MBE
➢ Polysilicon growth: LPCVD
➢ Other deposition tools like ALD, MBE, etc.

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Deposition Example: Sputtering

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EEE F313 BITS Pilani, Pilani Campus
MOS processing steps

❖ Wafer cleaning
❖ Oxidation
❖ Lithography
❖ Etching
❖ Doping (N-well, P-well, Twin-tub process)
❖ Metallization
❖ Packaging

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EEE F313 BITS Pilani, Pilani Campus
NMOS

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PMOS

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NMOS fabrication

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• CMOS: Putting NMOS and PMOS together.
• Individual devices should not interact with each other
except through metal interconnections.

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BITS Pilani, Pilani Campus
Isolation

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This is what we will fabricate.

EEE F313 41 BITS Pilani, Pilani Campus


Step 1: Choosing a Substrate

• Doping type (n/p/semi-insulating)

• Resistivity

• Orientation: Normally Si (100) is preferred.

• Thickness: Depending on the wafer size.

• Size: Depends on process capability, economic factor.

• Wafer flatness, trace impurity level, etc.

EEE F313 42 BITS Pilani, Pilani Campus


Active Region Formation

Spin Coating
LPCVD
Oxidation
• Substrate selection: moderately
high resistivity, (100) orientation,
P type.
• Wafer cleaning, thermal oxidation
(≈ 40 nm), nitride LPCVD
deposition (≈ 80 nm), photoresist
spinning and baking (≈ 0.5 - 1.0 µm).

EEE F313 43 BITS Pilani, Pilani Campus


Active Region Formation:
Thickness selection
• Grown Si3N4 is under high tensile strain.
• If directly grown on Si, it can lead to high compressive strain in
underlying Si.
• SiO2 acts to relieve the strain.

Tensile strain
Compressive strain

EEE F313 44 BITS Pilani, Pilani Campus


Stress-relief oxide Silicon Nitride Active mask

n-well

p-type

• Mask #1 patterns the


active areas. The nitride
is dry etched.

• PR exposed using a mask.


• Exposed part is developed using a developer solution (+Ve PR).
• Si3N4 etched (Plasma etching, F plasma)
• PR removed (Sulfuric acid or stripped using O2 plasma).

EEE F313 45 BITS Pilani, Pilani Campus


LOCOS
Bird’s beak
Or
Prevents oxidation Bird’s head
PR removal
+
Oxidation

• Thick SiO2 grown locally (~500 nm).


• Si3N4 is dense enough to stop O2 and H2O diffusion.
• After LOCOS process, Si3N4 will be etched. • Field oxide is grown
using a LOCOS process.
• Hot phosphoric acid or dry etching. Typically 90 min @ 1000 ˚C
in H2O grows ≈ 0.5 µm.
• This process should be very selective.
EEE F313 46 BITS Pilani, Pilani Campus
LOCOS

Bird’s beak Lateral diffusion of


Or O2/H2O through SiO2
Prevents oxidation Bird’s head

Solution: Thinner
oxide SiO2

Poly-buffered oxide
Bird’s beak: Concerning for small active devices

EEE F313 47 BITS Pilani, Pilani Campus


Poly-buffered LOCOS

Prevents oxidation
PR removal
+
Oxidation

• Poly-buffered LOCOS: SiO2/Poly-Si/Si3N4 instead of SiO2/Si3N4.


• Thicker Si3N4 and thinner SiO2.
• SiO2/Poly-Si helps to relieve strain.

EEE F313 48 BITS Pilani, Pilani Campus


Shallow Trench Isolation (STI):
another isolation technique
Oxidation
Thin “liner” oxide
Si etching 10-20 nm

SiO2 deposition by CVD

CMP

EEE F313 49 BITS Pilani, Pilani Campus


P-well formation

• Pattern created for P-well (involves PR spin coating, lithography using


appropriate mask and PR development).
• Ion implantation of Boron.
• Acceleration must be high enough to penetrate the thin and field
oxide.
• Avoid the formation of parasitic field oxide transistor.
• PR removed (O2 Plasma or chemically).

• Mask #2 blocks a B+ implant


to form the wells for the
NMOS devices. Typically
1013 cm-2 @ 150-200 KeV.

EEE F313 50 BITS Pilani, Pilani Campus


N-well formation

• Pattern created for P-well (involves PR spin coating, lithography using


appropriate mask and PR development).
• Ion implantation of Phosphorous.
• PR removed and wafer is cleaned.

• Mask #3 blocks a P+ implant


to form the wells for the PMOS
devices. Typically 1013 cm-2
@ 300+ KeV.

EEE F313 51 BITS Pilani, Pilani Campus


N-well formation

• Annealed in a furnace in inert ambience


• Damage repair from implants.
• Diffusion of impurity to get a required depth of N-well.

• A high temperature drive-in


produces the “final” well
depths and repairs implant
damage. Typically 4-6 hours
@ 1000 ˚C - 1100 ˚C or
equivalent Dt.

EEE F313 52 BITS Pilani, Pilani Campus


Gate Formation

• A crucial step in CMOS fabrication as this will affect and decide the
VTH value.

• VTH value can be controlled by nonuniform doping under gate.

EEE F313 53 BITS Pilani, Pilani Campus


Gate Formation: VTH adjustment

• Mask #4 is used to mask


the PMOS devices. A VTH
adjust implant is done on
the NMOS devices, typically
a 1-5 x 1012 cm-2 B+ implant
@ 50 - 75 KeV.

EEE F313 54 BITS Pilani, Pilani Campus


Gate Formation: VTH adjustment

• Mask #5 is used to mask


the NMOS devices. A VTH
adjust implant is done on
the PMOS devices, typically
1-5 x 1012 cm-2 As+ implant
@ 75 - 100 KeV.

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BITS Pilani, Pilani Campus
Gate Formation: VTH adjusted

• Top oxide have gone through multiple processing steps


(implantation, etching, exposure to chemicals, etc.).
• Thickness is around 40 nm.
EEE F313 56 BITS Pilani, Pilani Campus
Gate Formation: Oxide Regrowth

• The thin oxide over the


active regions is stripped
and a new gate oxide
grown, typically 3 - 5 nm,
which could be grown in
0.5 - 1 hrs @ 800 ˚C in O2.

• Poly-Si needed on top of SiO2 to form MOS.

EEE F313 57 BITS Pilani, Pilani Campus


Gate Formation: Poly-Si Growth

• Polysilicon is deposited
by LPCVD ( ≈ 0.5 µm). An
unmasked P+ or As+ implant
dopes the poly (typically
5 x 1015 cm-2).

𝑺𝒊𝑯𝟒 → 𝑺𝒊 + 𝟐𝑯𝟐

Poly-Si doping:
• Implantation
• In-situ doping

• Gate area needed to be defined.

EEE F313 58 BITS Pilani, Pilani Campus


Gate Formation: Poly-Si patterning

• Poly-Si is also used to form local interconnects.


• Selectivity and anisotropy of etching is important
Polysilicon here.
mask
Polysilicon gate

n-well

p-type

• Mask #6 is used to protect


the MOS gates. The poly is
plasma etched using an
anisotropic etch.

• S/D diffusion needed to be defined?

EEE F313 59 BITS Pilani, Pilani Campus


Hot electron Problem

• Voltage scaling has not been as aggressive as dimension scaling.


• High electric field can lead to “hot electron” problems.
• Hot electron: high energy (velocity) carriers may lead to
• impact ionization
• Reliability issues due to carrier injection in SiO2.
• Solution: Lightly Doped Drain (LDD)

EEE F313 60
BITS Pilani, Pilani Campus
LDD formation

• Mask #7 protects the PMOS • Mask #8 protects the NMOS


devices. A P+ implant forms devices. A B+ implant forms
the LDD regions in the NMOS the LDD regions in the PMOS
devices (typically 5 x 1013 cm-2 devices (typically 5 x 1013 cm-2
@ 50 KeV). @ 50 KeV).

EEE F313 61 BITS Pilani, Pilani Campus


Sidewall Spacer

• What determines the width of this sidewall spacer?

• Conformal layer of SiO2 • Anisotropic etching leaves


is deposited (typically “sidewall spacers” along
0.5 µm). the edges of the poly gates.

• What is purpose of this sidewall spacer?


• Isolation between S/D contact metal and poly-Si.
• Essential for creation of N-/P- tip in S/D region.
EEE F313 62 BITS Pilani, Pilani Campus
Source/Drain Formation

• Why there is a thin “screen” oxide still there on top of wafer?

• Mask #9 protects the PMOS • Mask #10 protects the NMOS


devices, An As+ implant forms devices, A B+ implant forms
the NMOS source and drain the PMOS source and drain
regions (typically 2-4 x 1015 cm-2 regions (typically 1-3 x 1015 cm-2
@ 75 KeV). @ 50 KeV).
EEE F313 63 BITS Pilani, Pilani Campus
Source/Drain Formation

• A final high temperature


anneal drives-in the junctions
and repairs implant damage
(typically 30 min @ 900˚C or
1 min RTA @ 1000˚C.

EEE F313 64 BITS Pilani, Pilani Campus


Contact and Local Interconnect
Formation

• An unmasked oxide etch


allows contacts to Si and
poly regions.

EEE F313 65 BITS Pilani, Pilani Campus


Contact and Local Interconnect
Formation

• Ti is deposited by
sputtering (typically
100 nm).

EEE F313 66 BITS Pilani, Pilani Campus


Contact and Local Interconnect
Formation

• The Ti is reacted in an
N2 ambient, forming TiSi2
and TiN (typically 1 min
@ 600 - 700 ˚C).

Titanium disilicide (TiSi2): 1 Ω/sq


Titanium nitride (TiN; sometimes known as tinite): 10 Ω/sq

EEE F313 67 BITS Pilani, Pilani Campus


Contact and Local Interconnect
Formation

• Mask #11 is used to


etch the TiN, forming
local interconnects.

EEE F313 68 BITS Pilani, Pilani Campus


Multilevel Contact Formation

• A conformal layer of
SiO2 is deposited by
LPCVD (typically 1 µm).

• SiO2 is often doped with phosphorous and/or boron.


• Phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).
• Phosphorous provides protection against mobile ions (Na+, K+, etc.).
• Boron decreases the glass reflow temperature.
EEE F313 69 BITS Pilani, Pilani Campus
Multilevel Contact Formation

• CMP is used to
planarize the wafer
surface.

EEE F313 70 BITS Pilani, Pilani Campus


Multilevel Contact Formation

• Mask #12 is used to


define the contact holes.
The SiO2 is etched.

• A thin TiN barrier layer (or Ti/TiN)


is deposited by sputtering (typically
a few tens of nm), followed by W
CVD deposition.

EEE F313 71 BITS Pilani, Pilani Campus


Multilevel Contact Formation

• CMP is used to planarize


the wafer surface,
completing the damascene
process.

EEE F313 72 BITS Pilani, Pilani Campus


Multilevel Contact Formation

• Al is deposited on the
wafer by sputtering. Mask
#13 is used to pattern the
Al and plasma etching is
used to etch it.

• Al (with small % of Si and Cu) is deposited and patterned?

EEE F313 73 BITS Pilani, Pilani Campus


Multilevel Contact Formation

• Intermetal dielectric and


second level metal are
deposited and defined in
the same way as level #1.
Mask #14 is used to define
contact vias and Mask #15
is used to define metal 2.
A final passivation layer
of Si3N4 is deposited by
PECVD and patterned
with Mask #16.

EEE F313 74 BITS Pilani, Pilani Campus


EEE F313 75 BITS Pilani, Pilani Campus
Hardware is not Hard, right?

EEE F313 76 BITS Pilani, Pilani Campus


Most significant technology nodes in this century

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BITS Pilani, Pilani Campus
Current Status

Current record: Deep learning processor


Wafer Scale Engine 2 by Cerebrashaving,
2.6 Trillion transistors, TSMC 7-nm
process!

EEE F313 78 BITS Pilani, Pilani Campus


Where we are?

Many more
under review

• There are many more fab setup (KAYNES, Suchi Semicon, etc.) missing in
the map
• Mostly OSAT.
• Aiming for 28 nm node.

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EEE F437 BITS Pilani, Pilani Campus
Emerging Options: More Moore &
More than Moore

EEE F313 80 BITS Pilani, Pilani Campus


3 D integration

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BITS Pilani
Pilani Campus

LATCH-UP---- (Parasitic Effect)


Why multiple bulk contacts?
BITS Pilani, Pilani Campus
Why multiple bulk contacts?

Reasons—

• To ensure guaranteed connection to Ground/ Vdd

• To ground stray currents/ voltages to prevent Latch-up

• What is Latch up phenomena?

BITS Pilani, Pilani Campus


Latch-up
i/p i/p

Output D S
GND VDD

BITS Pilani, Pilani Campus


Latch-Up

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BITS Pilani, Deemed to be University under Section 3 of UGC
BITS Pilani, PilaniAct, 1956
Campus
Positive feedback loop----
Equivalent Circuit

87
BITS Pilani, Deemed to be University under Section 3 of UGC
BITS Pilani, PilaniAct, 1956
Campus
Latchup in Bulk CMOS

• A byproduct of the Bulk CMOS structure is a pair of parasitic


bipolar transistors.
• The collector of each BJT is connected to the base of the
other transistor in a positive feedback structure.

• A phenomenon called latchup can occur when ---

• (1) both BJT's conduct, creating a low resistance path


between Vdd and GND and

• (2) the product of the gains of the two transistors in the


feedback loop, (β1 x β2), is just greater than one..
• Means sustained latch-up 88
BITS Pilani, Pilani Campus
Trigger of latch up

The result of latch-up is at the

minimum--- a circuit malfunction,

in the worst case---- the destruction of the


device

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BITS Pilani, Pilani Campus
Sources of latchup

Latch-up may begin when Vout swings due to a


noise spike or an improper circuit hookup

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BITS Pilani, Pilani Campus
Remedies

91
BITS Pilani, Deemed to be University under Section 3 of UGC
BITS Pilani, PilaniAct, 1956
Campus
Reduce the gain product β1 x β2

– move n-well and n+ source/drain farther apart,

– increases width of the base of Q2 reduces gain beta2

– Reduces circuit density

– buried n+ layer in well reduces gain of Q1

BITS Pilani, Pilani Campus


• Reduce the well and substrate resistances, producing lower voltage
drops

– higher substrate doping level reduces Rsub

– reduce Rwell by making low resistance contact to VDD /GND

– guard rings around p- and/or n-well, with frequent contacts to


the rings, reduces the parasitic resistances.

• CMOS transistors with guard rings with multiple bulk contacts

BITS Pilani, Pilani Campus


CMOS transistors with guard
rings to ground stray currents

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BITS Pilani, Deemed to be University under Section 3 of UGC
BITS Pilani, PilaniAct, 1956
Campus
95
BITS Pilani, Pilani Campus
Standrd cell template for avoiding latchup

96
BITS Pilani, Pilani Campus
• Make sure power supplies are off before plugging a board.
Avoid large transients

• A "hot plug in" of an un-powered circuit board or module may


cause signal pins to see surge voltages greater than 0.7 V
higher than Vdd, which rises more slowly to is peak value.

• When the chip comes up to full power, sections of it could be


latched.

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BITS Pilani, Pilani Campus
Summary

• CMOS technology has been introduced.

• We learnt how individual technologies like oxidation and ion implantation


are actually used.

• There are many variations on CMOS process flows used in industry. The
process described here is intended to be representative, although it is
simplified compared to many current process flows.

• We also covered some process options.

• Emerging trends in IC industries discussed.

• Latch-Up origin and remedies have been discussed.

EEE F313 98 BITS Pilani, Pilani Campus


BITS Pilani
Pilani Campus

Thank You

BITS Pilani, Pilani Campus

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