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An Investigation on the Optimization and Scaling of Complementary SiGe

HBTs

Article in IEEE Transactions on Electron Devices · January 2013

DOI: 10.1109/TED.2012.2225838

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34 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013

An Investigation on the Optimization and

Scaling of Complementary SiGe HBTs
Partha Sarathi Chakraborty, Student Member, IEEE, Kurt A. Moen, Student Member, IEEE, and
John D. Cressler, Fellow, IEEE

Abstract—We use predictive technology computer-aided design

to investigate the device design challenges and optimization issues
that will be necessarily encountered in scaling of complementary
silicon–germanium (C-SiGe) heterojunction bipolar transistors
(HBTs). A fully integrated simulation framework was developed
to design and optimize device doping and Ge profiles for any given
target performance, using important circuit-relevant figures-
of-merit. This methodology was successfully utilized to realize
device profiles for multiple C-SiGe technology nodes within the
context of a C-SiGe scaling roadmap. A method for optimizing the
ac performance of SiGe HBTs geared for both high-performance
and low-power applications is also presented. The performance
metrics of the optimized profiles presented here are then compared
with those of existing fabricated devices reported in the literature.
Index Terms—Bipolar junction transistor (BJT), comple-
mentary bipolar, complementary silicon–germanium (C-SiGe),
heterojunction bipolar transistor (HBT), scaling roadmap,
silicon–germanium (SiGe), technology computer-aided design
(TCAD). Fig. 1. Two-dimensional cross-section of the simulated and parameterized
device structure. Parameters shown here were used for tuning the physical
I. I NTRODUCTION device structure (both vertical and lateral).

C OMPLEMENTARY bipolar technology [npn + pnp bipo-

lar junction transistors (BJTs)] has been long considered
the “gold standard” for analog applications requiring flexibility
C-SiGe HBT technology for high-frequency operation [8]–[15].
The present investigation leverages technology computer-aided
in designing circuits with high speed, low power, low noise, design (TCAD) and presents, for the first time, a comprehen-
high linearity, large bandwidth, large voltage swing, and out- sive study of the device design challenges and optimization
put drive [1]–[4]. Introducing graded Ge into the base of the issues that are unavoidable in designing and scaling C-SiGe
Si BJTs to build band-gap-engineered complementary (npn + HBTs for high-performance analog and radio-frequency
pnp) silicon–germanium (C-SiGe) heterojunction bipolar tran- applications.
sistors (HBTs) can provide significant leverage in the tradeoffs An earlier TCAD-based study of C-SiGe HBTs was limited
involved in designing npn and pnp BJTs with matched perfor- to drift–diffusion transport models, 1-D hypothetical doping
mance (e.g., comparable fT ) and reliability [5]–[7]. However, profiles, and devices with much lower peak fT and fMAX
the inherent minority-carrier transport issues that stem from [16]. It gave no consideration to the SiGe layer stability or the
the Ge-induced valence-band offset and lower minority carrier impact of simultaneously changing multiple device parameters.
mobility associated with the pnp SiGe HBT device design Although there have been studies on self-heating effects in
need to be carefully addressed in order to successfully scale trench-isolated SiGe HBTs on silicon-on-insulator (SOI) [17],
[18], SiGe HBTs on thick-film SOI substrates with peak fT >
100 GHz have shown operational voltage constraints resulting
Manuscript received March 10, 2012; revised October 5, 2012; accepted
from strong electrothermal effects leading to thermal runaway
October 11, 2012. Date of publication December 7, 2012; date of current [19]. Consequently, in this C-SiGe scaling study, we utilize the
version December 19, 2012. This work was supported by the Semiconductor commercially available Sentaurus Workbench (SWB) TCAD
Research Corporation under Global Research Collaboration Task 1965.001.
The review of this paper was arranged by Editor G. Niu.
environment and its entire suite of simulation tools [20] to
P. S. Chakraborty and J. D. Cressler are with the School of Electrical and investigate 2-D SiGe HBT device structures on bulk Si, using
Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 both shallow trench (STI) and deep trench (DT) for isolation
USA (e-mail: [email protected]).
K. A. Moen was with the School of Electrical and Computer Engineering, (see Fig. 1). This approach provides a more relevant plat-
Georgia Institute of Technology, Atlanta, GA 30332 USA. He is now with form from a technology development perspective for the high-
TowerJazz Semiconductor, Newport Beach, CA 92660 USA. performance mixed-signal semiconductor industry.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. An earlier initial study illustrated some of the issues as-
Digital Object Identifier 10.1109/TED.2012.2225838 sociated with scaling C-SiGe HBTs toward the 200 GHz
0018-9383/$31.00 © 2012 IEEE
CHAKRABORTY et al.: INVESTIGATION ON THE OPTIMIZATION AND SCALING OF COMPLEMENTARY SiGe HBTs 35

performance node [21]. In this paper, our previous work is

expanded and employed to develop a C-SiGe HBT scaling
roadmap. This paper presents, for the first time, a calibrated
performance scaling study of C-SiGe HBTs with the develop-
ment and benchmarking of a C-SiGe HBT scaling roadmap;
addresses TCAD-based C-SiGe HBT predictive device model-
ing issues that one necessarily encounters in such a study; and
introduces an optimization methodology that must be consid-
ered while simultaneously optimizing C-SiGe HBTs for use in
both high-performance and low-power circuits.

II. TCAD S IMULATION F RAMEWORK

AND M ETHODOLOGY

The doping and Ge profiles for both npn and pnp SiGe Fig. 2. TCAD simulation steps used in the C-SiGe HBT device design and
HBTs, along with both their vertical and lateral physical cross- optimization methodology for any target performance node.
sections, were carefully parameterized (see Fig. 1). The full hy-
drodynamic carrier transport code, with Philips unified mobility A stability calculation of the SiGe layer (for any given doping
models, and including the Okuto–Crowell model for nonlocal and Ge profile) using the Matthews–Blakeslee criterion with
impact ionization, band-gap narrowing, and carrier recombina- Fisher’s cap layer correction was integrated directly into the
tion (Shockley–Read–Hall and Auger) and the Canali model for simulation environment [28]. This provides an estimation of
high-field velocity saturation (using carrier temperature as the the SiGe layer stability for each profile variation. All profiles
driving force) were used for the device simulations presented considered in this paper were thermodynamically stable. Ac-
[21]–[24]. counting for C incorporation would only improve the SiGe
The model parameter files were calibrated to measured data layer stability.
from a commercial 200 GHz npn SiGe HBT platform. Similar A pinched-base sheet resistance (Rbi ) calculation was per-
parameter files were used for both the npn and pnp devices. formed for each device profile. Strain effects were accounted
The SiGe parameter file (available within SWB) used for this for in this calculation based on the doping and Ge profiles and
paper interpolates between the Si and Ge properties based on the carrier mobility values [29]. Device simulations were per-
the Ge mole fraction. Further accuracy in the modeling of formed to extract the standard dc, ac, and output characteristics
strain effects on the carrier transport within the SiGe layer can (forced-VBE and forced-IB ) for each profile. From the device
be implemented using parameter files generated from separate simulation results, important figures-of-merit (FoM) (e.g., fT ,
Monte Carlo simulations (for the npn and pnp devices) based on fMAX , βDC , BVCEO , and VA ) were extracted. An integrated
their individual doping and Ge profiles. However, this would 1-D and 2-D quasi-static transit-time (QSTT) analysis was
still not account for effects of the Si cap layer, processing used to compare regional transit-times (TTs) and fine tune
steps, and carbon (C) incorporation to suppress boron out- the candidate device profiles based on the limiting factors for
diffusion on the final SiGe layer strain. Important parameters ac performance and the onset of heterojunction barrier effects
for the recombination models were carefully calibrated, since (HBE) in the device [25], [30]–[32].
accuracy of these parameters is key to achieving predictive Half of the device cross-section was simulated to utilize
simulation of IB and the dc current gain (βDC ), and hence, symmetry around the center of the emitter and thereby reduce
BVCEO . the simulation time. Fig. 2 shows a flow diagram of the steps
The selectively implanted collector (SIC) regions of the sim- adopted in the device design and optimization methodology
ulated devices were constructed using two Gaussian profiles, used for developing the profiles of C-SiGe HBTs in this paper.
each of which can be independently tailored to emulate the All simulations were isothermal and performed at room temper-
individual SIC implants in a fabricated device. This allows for ature (300 K) unless otherwise noted. The target performance
greater flexibility in optimizing for the tradeoff between the metrics were defined based on existing npn-only SiGe HBT
onset of the Kirk effect (and heterojunction barrier effects) and device technologies. The ac performance of the optimized
the collector–base (CB) junction breakdown voltage (BVCBO ). devices was simulated for different biasing modes (constant
The SIC region was designed to have a lateral straggle to VCB or VCE ) to ensure that they are comparable in perfor-
emulate the doping profile that extends beyond the emitter mance over a broad range of operating conditions and design
window to the STI, as in a real device. Consequently, each topologies (common-base or common-emitter). For example, a
of the individual SIC Gaussian profiles was parameterized for wide range of relevant VCB and VCE values were considered to
independent control of peak doping position and concentration, simultaneously account for circuit designs ranging from low-
as well as vertical and lateral straggle [21]. There has been power to high-performance applications. However, the same
several earlier studies on TCAD-based device scaling and col- methodology can be used for TCAD-based matching studies of
lector profile optimization of npn SiGe HBTs [25]–[27], and the npn versus pnp performance over temperature, provided that
earlier methods, wherever applicable, have been used in this valid parameter files are available over the entire temperature
investigation for designing the complementary devices. range. This was beyond the scope of this paper.
36 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013

TABLE I neutral region exists within the base of a highly scaled 200 GHz
I MPORTANT 2-D P HYSICAL PARAMETERS FOR THE
O PTIMIZED D EVICE S TRUCTURES pnp HBT (the same holds true for npn devices). This is critical
in defining the quasi-neutral or space-charge regions within the
metallurgical base for an accurate estimation of the regional
TTs from the QSTT analysis [32].
HBE is a stronger constraint for optimizing pnp SiGe HBTs
due to the inherently larger band offset for the minority carrier
transport across the device [16]. The 1-D TT components along
the center of the emitter for a 200 GHz pnp profile shows that
the EB junction TT (or the hole inverse velocity) component
limits the device performance at low-to-moderate injection,
whereas the onset of HBE at high-injection results in the CB
junction TT limiting the performance of the device [21].
For the purpose of this study, the doping of the emitter,
base, and collector contact regions were kept comparable for
the npn and pnp devices at a specific performance node. At
comparable doping, the n-type doped regions will have lower
III. D EVICE M ODELING I SSUES
resistance than the corresponding p-type doped regions due to
Although most of the important device FoM, such as fT , higher majority carrier mobility. Thus, in this study, emitter
fMAX , βDC , and BVCEO , were modeled reasonably well using and collector resistances are higher for the pnp over the npn
our TCAD simulation framework under isothermal conditions, device. Although for simplicity we have assumed complete
realistic VA (early voltage) values for the scaled devices could activation of the dopant concentration, for fabricated devices,
be only simulated by appropriately considering self-heating solid-solubility limits will be another constraint that will induce
together with impact ionization in the hydrodynamic device differences in the emitter, base, and collector contact resistances
simulations [21], [33]. This resulted in longer simulation times of these devices. In general, for fabricated devices with higher
and convergence issues. Greater accuracy in predictive VA contact resistances, parasitics will play a more dominant role in
estimation can be achieved by using 3-D device structures lowering the fMAX .
with more accurate thermal boundary conditions in the device For identical doping concentrations in all regions of the
simulator. The divergence between the VA simulated with and npn and pnp devices, the npn provides a superior performance
without self-heating clearly increases with JC , device ther- compared with the pnp, as expected. To achieve optimized
mal resistance (RTH ), and the device performance, owing to C-SiGe HBT profiles with comparable performance for any
stronger self-heating effects [33]. target technology node, the best npn performance is generally
Lateral scaling of a candidate 200 GHz pnp device has shown reduced to match the performance of the optimized pnp HBT.
that the peak fT and maximum βDC remain fairly stable, being Once the dopant profiles are inverted from the npn to the pnp
solely dependent on the vertical profiles, whereas fMAX scales devices at the same concentration, the doping and Ge profiles
with the evolving lithography node as Rbi , Rbx , Ccb , and Ccs at the CB and EB junctions are key elements, which require
are dependent on the lateral device structure. Lateral scaling redesign and fine tuning. AC simulations were performed for a
in the simulation decks was incorporated through changing wide range of VCB and VCE values to optimize the candidate
both the intrinsic (emitter width or EW) and extrinsic (through devices toward a matched performance for important biasing
emitter–base (EB) spacer width or EBOSEP) parts of the base topologies used in circuit applications. This is important to
region, which is based on the lithography node considered ensure that the devices do not suffer from any unoptimized
(refer to Fig. 1). The 2-D lateral structure parameters were HBE when driven into saturation by a low supply voltage, as in
chosen such that the npn performance was reasonable compared low-power applications, which simultaneously require high
with reported values in the literature, but were kept fixed for the performance.
npn and pnp devices at the same performance node. However,
in general, it needs to be understood that these parameters will
IV. 200 GHz D EVICE O PTIMIZATION R ESULTS
play a key role in determining the fMAX and self-heating of the
device and can be appropriately leveraged as additional tuning A comparison of the final optimized candidate npn and pnp
knobs for achieving comparable electrothermal performance of device profiles for a 200 GHz C-SiGe HBT technology at the
the npn and pnp devices. The present study was mainly focused 120 nm scaling node is shown in Fig. 3. While the Ge profiles
on vertical profile optimization of the devices, with the intent to are not significantly different, the pnp requires much larger
shed light on the intrinsic profile differences of the npn versus SIC doping to achieve comparable performance and delay the
pnp at comparable performance and 2-D physical dimensions. onset of HBE, even with a similar Ge retrograde to the npn.
The values of all the important 2-D lateral and structural The dc and ac performances of the 200 GHz candidate device
parameters shown in Fig. 1 and used for each technology node profiles are shown in Figs. 4 and 5, respectively. While the
are listed as part of Table I. maximum βDC (although it occurs at a higher JC for the pnp),
Analysis of the excess carrier concentration vertically along IC at comparable IB , and peak fT are quite comparable for the
the middle of the emitter shows that no well-defined quasi- C-SiGe devices, peak fMAX for the npn is higher than for the
CHAKRABORTY et al.: INVESTIGATION ON THE OPTIMIZATION AND SCALING OF COMPLEMENTARY SiGe HBTs 37

Fig. 5. Comparison of the ac performance (fT , fMAX ) for the optimized

Fig. 3. Doping and Ge profiles for optimized C-SiGe HBT device structures 200 GHz npn and pnp HBT device profiles in Fig. 3.
with 200 GHz performance.

Fig. 6. Comparison of the simulated peak fT and fMAX for the opti-
mized 200 GHz npn (and pnp) HBT profiles in Fig. 3 obtained at different
(a) VCB (VBC ) and (b) |VCE | values.

Fig. 4. Comparison of the (a) dc performance (Gummel plots and current complementary HBT profiles compare very well in their perfor-
gain) and the (b) output characteristics for the optimized 200 GHz npn and mance over a wide bias range. The regional TT analyses of the
pnp HBT device profiles.
optimized npn and pnp profiles are shown in Fig. 7. For both
pnp due to lower SIC doping. Although the fT and fMAX devices, the EB junction TT (τbe ) limits performance at low-
values are higher for the npn at any JC below the peak values, to-moderate injection, whereas the CB junction TT (τbc + τc )
the peak fT and fMAX occur at a slightly higher JC for the limits the performance at moderate-to-high injection (at or
pnp device due to higher SIC doping, as the onset of both the around peak fT ). The base TT (τb ) limits the performance in the
Kirk effect and the HBE that causes the fT /fMAX rolloff is very high-injection regime of device operation (well beyond
delayed to higher JC in the pnp. BVCEO extracted at moderate peak fT ).
injection using the base-current reversal point under forced- Even at comparable doping, the pnp will have higher Re , Rb ,
VBE conditions are 1.78 and 1.97 V for the npn and pnp devices, and Rc compared with the npn. This contributes to lower fT
respectively. This is mainly due to a lower M − 1 for the pnp and fMAX for the pnp at JC lower than the peak values [21].
compared with the npn, even with a higher collector doping. At
similar JC and VCB values, the pnp device will show slightly
V. C-S I G E HBT S CALING ROADMAP
higher self-heating (J • E) over the npn due to a larger CB
junction electric field (E) resulting from higher doping. To demonstrate the utility of our integrated simulation frame-
Although these device profiles were initially matched for per- work towards developing a C-SiGe HBT scaling roadmap,
formance under a single bias condition, the profiles were further C-SiGe devices were also developed for a target of 100 GHz
optimized for comparable performance over a range of VCE peak fT at the 180 nm lithography node. The optimized npn and
and VCB values. As shown in Fig. 6, the optimized 200 GHz pnp device profiles for the 100 GHz node are shown in Fig. 8.
38 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013

Fig. 9. Comparison of the simulated peak fT and fMAX for the optimized
100 GHz npn (and pnp) HBT profiles obtained at different (a) VCB (VBC ) and
(b) |VCE | values.

TABLE II
Fig. 7. Regional TT parameters extracted from the regional QSTT analysis of S IMULATED F O M FOR THE C OMPLEMENTARY
the 200 GHz (a) npn and (b) pnp device profiles at |VCB | = 0.5 V. D EVICES AS PART OF A S CALING ROADMAP

Fig. 8. Doping and Ge profiles for optimized C-SiGe HBT device structures
with 100 GHz performance.

The 100 GHz profiles are in some ways similar to those of

the 200 GHz profiles. The pnp has higher SIC doping, slightly
higher Ge content in the base, and a comparable retrograde. The
ac performance of the 100 GHz npn and pnp devices compare
very well over a wide range of VCB and VCE values, as shown
in Fig. 9.
Table I shows a list of some of the important 2-D physical
parameters (given in Fig. 1) at each performance node. The
parameters were kept identical for the npn and pnp devices. Fig. 10. Simulated regional TT components at the peak fT condition (at
|VCB | = 0.5 V) as a fraction of the total TT for all the optimized 100 and
Between the 100 and 200 GHz devices, the only physical 200 GHz npn and pnp HBT profiles (in Figs. 3 and 8, respectively).
parameter varied was emitter width WE through EW.
Table II shows a summary of all the important FoM for The performance roadmap in Table II can be extended using
the C-SiGe devices at both the 100 and 200 GHz nodes, the same simulation framework to include other performance
which is displayed as a performance roadmap. Fig. 10 shows nodes at ≤ 200 GHz.
regional TT components for each of these devices as a frac- It is equally important to take into consideration additional
tion of the total emitter-to-collector TT (τec ) at the peak fT reliability FoM during the TCAD-based device performance
condition. optimization process; this has never been previously attempted
CHAKRABORTY et al.: INVESTIGATION ON THE OPTIMIZATION AND SCALING OF COMPLEMENTARY SiGe HBTs 39

Fig. 11. fT versus BVCEO plot of the optimized C-SiGe HBT devices from
this paper, as compared with actual devices reported in [8], [9], and [15],
showing the tradeoff between performance and operating voltage.
Fig. 12. Peak fMAX versus fT plot of the optimized C-SiGe HBT devices
in a TCAD environment for device optimization. For example, from this paper, as compared with actual devices reported in [8], [9], and [15],
showing distinct generations of C-SiGe device performance with fMAX > fT .
the reverse-biased (RB) current or the zero-bias peak electric
field at the EB junction holds a direct correlation to the long-
VI. S UMMARY
term reliability of the device. This is particularly important for
optimization of C-SiGe HBTs that need to be comparable in This paper has, for the first time, successfully developed
both their performance and reliability. A recent investigation an integrated TCAD simulation framework and methodology
using the integrated simulation framework from this study has for predictive optimization and scaling of C-SiGe HBTs to
shown that the optimized C-SiGe HBT profiles developed here achieve comparable performance and reliability. The utility of
compared very well for the simulated RB EB junction tunneling this framework has been demonstrated by showing, for the
current at both the 100 and 200 GHz performance nodes [34]. In first time, a path toward development of a performance scaling
this context, it is important to perform simultaneous predictive roadmap for C-SiGe HBTs. This integrated simulation frame-
estimation of reliability within the device optimization work lends itself to postprocessing and analysis and is highly
framework used in this study. While it is important to achieve flexible for use in any kind of technology development envi-
comparable performance and reliability when scaling C-SiGe ronment within the semiconductor industry.
HBTs, it is equally pertinent to explore and develop new Within the scope of the simulation methodology highlighted
applications that will utilize better device performance, while here, this paper also has proved, for the first time, that perfor-
pushing the performance of existing C-SiGe circuits [35], [36]. mance optimization and scaling of C-SiGe HBTs is feasible,
When the performances of the device profiles optimized here just as in npn-only technologies, as long as there are existing
are compared with that of existing C-SiGe HBTs reported in the methods to commercially fabricate these devices. While the
literature on a fT versus BVCEO plot in Fig. 11, the fT versus optimization results for the npn devices are based on calibration
BVCEO scaling tradeoff commonly known as the “Johnson to existing material, similar calibration was not possible for the
limit” is clearly observed. The 100 GHz optimized devices are pnp devices due to insufficient experimental data. For fabricated
very comparable with those reported in the literature with a devices with the profiles optimized here, this could potentially
similar fT × BVCEO product, further indicating the robustness lead to a performance lower than what is presented here for
and predictive nature of the device optimization methodology the pnp device profiles. It is well understood that any inaccu-
implemented in this paper. With the increase in fT resulting racy in the pnp transport model resulting from the absence of
from device scaling, the C-SiGe devices continually move to a calibration to fabricated devices will clearly induce errors in
higher fT × BVCEO product (dotted lines) due to an increase fT , fMAX , BVCEO , etc. However, practically from a device
in the SIC doping with performance, which is similar to that optimization perspective, this would require some additional
reported for scaling of npn devices in earlier studies [27], fine tuning of the current candidate pnp device profiles (mainly
[37]. This demonstrates the feasibility of a performance scaling doping in the base and collector and the Ge profile) to achieve
roadmap for C-SiGe HBTs akin to that for npn SiGe HBTs [27]. an optimized performance comparable to the npn.
If the performances of C-SiGe devices from this paper are This paper also has demonstrated, for the first time, an
compared with those reported in the literature on a fT versus integrated method to optimize C-SiGe HBTs for comparable
fMAX plot in Fig. 12, then the devices can be clearly grouped performance over different biasing configurations and a wide
into three generations (peak fT of ≤ 50, ∼100, and ∼200 GHz range of bias values, which is important for optimizing devices
with typically fMAX > fT for each generation). This is com- geared for a wide spectrum of low-power and high-performance
parable with the three generations of existing npn-only SiGe applications. Considering that complementary bipolar tech-
HBTs (based on the constant fT + fMAX lines), indicating nologies will remain very attractive for high-performance,
that performance scaling for the C-SiGe HBTs can be enabled high-frequency, analog, and mixed-signal circuits, scaling and
through successful fabrication of the C-SiGe devices. development of such technologies up to 200 GHz performance
40 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013

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CHAKRABORTY et al.: INVESTIGATION ON THE OPTIMIZATION AND SCALING OF COMPLEMENTARY SiGe HBTs 41

Partha Sarathi Chakraborty (S’02–M’04–S’08) John D. Cressler (F’01) received the Ph.D. degree
is currently working toward the Ph.D. degree at from Columbia University, New York, in 1990.
Georgia Institute of Technology, Atlanta. He is a Ken Byers Professor with Georgia In-
His current research interests include semiconduc- stitute of Technology, Atlanta. His research inter-
tor device physics, characterization, reliability, and ests are silicon-based heterostructure technology,
TCAD modeling. devices, and circuits.

Kurt A. Moen (S’05) received the Ph.D. de-

gree from Georgia Institute of Technology, Atlanta,
in 2012.
He is with TowerJazz Semiconductor, Newport
Beach, CA. His research interests include radiation
effects, reliability, and optimization of SiGe HBTs
and SOI CMOS.

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