Experiment-1

4 to 16 Decoder
// Design of 4 to 16 Decoder using two 3 to 8 Decoder
//Design of 2x4 decoder
module dec2_4(b,a,en);
output [3:0] b;
input [1:0]a; input en;
wire [1:0]aa;
not(aa[1],a[1]),(aa[0],a[0]);
and(b[0],en, aa[1],aa[0]),(b[1],en, aa[1],a[0]),(b[2],en, a[1],aa[0]),(b[3],en, a[1],a[0]);
endmodule
//Test bench code for 2 to 4 decoder
module tst_decod_2t4;
wire [3:0]b;
reg[1:0] a;
regen;
dec2_4 a1(b,a,en);
initial
begin
{a,en} =3'b000;
#2{a,en} =3'b001;
#2{a,en} =3'b011;
#2{a,en} =3'b101;
#2{a,en} =3'b111;
end
initial
$monitor ($time , "output b = %b, input a = %b, en=%b ",b, a,en);
initial #70 $stop;

endmodule

// 3 to 8 decoder design using two 2 to 4 decoder

module dec3_8(pp,q,enn);
output[7:0]pp;
input[2:0]q;
input enn;
wire qq;
wire[7:0]p;
not g38(qq,q[2]);
dec2_4 g1(.b(p[3:0]),.a(q[1:0]),.en(qq));
dec2_4 g2(.b(p[7:4]),.a(q[1:0]),.en(q[2]));
and g30(pp[0],p[0],enn);
and g31(pp[1],p[1],enn);
and g32(pp[2],p[2],enn);
and g33(pp[3],p[3],enn);
and g34(pp[4],p[4],enn);
and g35(pp[5],p[5],enn);
and g36(pp[6],p[6],enn);
and g37(pp[7],p[7],enn);
endmodule
// Test bench code for 3 to 8 decoder design using two 2 to 4 decoder
module tst_decod3_8;
// Inputs
reg [2:0] q;
regenn;
// Outputs
wire [7:0] pp;
dec3_8 a2(pp,q,enn);
initial
begin
{q,enn} =4'b0000;
#2{q,enn} =4'b0001;
#2{q,enn} =4'b0011;
#2{q,enn} =4'b0101;
#2{q,enn} =4'b0111;
#2{q,enn} =4'b1001;
#2{q,enn} =4'b1011;
#2{q,enn} =4'b1101;
#2{q,enn} =4'b1111;
end
initial
$monitor ($time , "output b = %b, input q = %b, enn-%b "pp,q enn);
initial #70 $stop;
endmodule
// 4 to 16 decoder design using structural model
module dec4_16(m,n,en);
output[15:0]m;
input[3:0]n;
input en;
not g1(nn,n[3]);
dec3_8 g3(.pp(m[7:0]),.q(n[2:0]),.enn(nn));
dec3_8 g4(.pp(m[15:8]),.q(n[2:0]),.enn(n[3]));
endmodule
// Test bench code for 4 to 16 decoder design using structural model
module tst_dec4to16;
// Inputs
reg [3:0] n;
reg en;
// Outputs
wire [15:0] m;
// Add stimulus here
dec4_16 a3(m,n,en);
initial
begin
{n,en} =5'b00000;
#2{n,en} =5'b00001;
#2{n,en} =5'b00011;
#2{n,en} =5'b00101;
#2{n,en} =5'b00111;
#2{n,en} =5'b01001;
#2{n,en} =5'b01011;
#2{n,en} =5'b01101;
#2{n,en} =5'b01111;
#2{n,en} =5'b10001;
#2{n,en} =5'b10011;
#2{n,en} =5'b10101;
#2{n,en} =5'b10111;
#2{n,en} =5'b11001;
#2{n,en} =5'b11011;
#2{n,en} =5'b11101;
#2{n,en} =5'b11111;
end
initial
$monitor ($time , "output m = %b, input n = %b, en=%b ",m,n,en);
initial #100 $stop;

endmodule

Experiment-2
8 to 3 Encoder
// 8 to 3 Encoder Design using data flow model
module encoder8to3_data(o, a);
output [2:0] o;
input [7:0] a;
assign o=((a== 8'b00000001)?3'b000:
((a==8'b00000010)?3'b001:
((a==8'b00000100)?3'b010:
((a==8'b00001000)?3'b011:
((a==8'b00010000)?3'b100:
((a==8'b00100000)?3'b101:
((a==8'b01000000)?3'b110:
((a==8'b10000000)?3'b111:1'bz))))))));
endmodule
// Test bench code for 8 to 3 Encoder Design using dataflow model
moduleencoder_tstb_dataflow;
// Inputs
reg [7:0] a;
// Outputs
wire [2:0] o;
 encoder8to3_data d2(o, a);
initial begin
a =8'b00000001;
#3 a=8'b00000010;
#3 a=8'b00000100;
#3 a=8'b00001000;
#3 a=8'b00010000;
#3 a=8'b00100000;
#3 a=8'b01000000;
#3 a=8'b10000000;
end
initial $monitor($time,"o=%b,a=%b",o,a);
initial #60 $stop;
endmodule

Experiment-3
8: 1Multiplexer and 1: 8 Demultiplexer
// 8 to 1 Multiplexer using behavioral model
module mux_8t1(o,s,i);
output o;
input [2:0] s;
input [7:0] i;
reg o;
always@(s,i)
begin
case(s)
3'b000:o = i[0];
3'b001:o = i[1];
3'b010:o = i[2];
3'b011:o = i[3];
3'b100:o = i[4];
3'b101:o = i[5];
3'b110:o = i[6];
3'b111:o = i[7];
default:o = 1'bz;
endcase
end
endmodule
// Test bench code for 8 to 1 Multiplexer using behavioral model
module tst_mux_8t1beh;
// Inputs
reg [7:0] i;
reg [2:0] s;
// Outputs
wire o;
mux_8t1 a1(o,s,i);
initial begin
// Initialize Inputs
i = 10101010;
s = 0;
#2 s=3'b001;
#2 s=3'b010;
#2 s=3'b011;
#2 s=3'b100;
#2 s=3'b110;
#2 s=3'b111;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
initial $monitor($time,"inputdata=%b,selectline=%b,output=%b",i,s,o);
endmodule
// 1 to 8 Demultiplexer using behavioral model
module demux_1to8behv(d, s, i);
output [7:0] d;
input [2:0] s;
inputi;
reg [7:0] d;
always @(s,i)
begin
d=8'bz;
if(s==3'b000)
d[0]=i;
else if(s==3'b001)
d[1]=i;
else if(s==3'b010)
d[2]=i;
else if(s==3'b011)
d[3]=i;
else if(s==3'b100)
d[4]=i;
else if(s==3'b101)
d[5]=i;
else if(s==3'b110)
d[6]=i;
else if(s==3'b111)
d[7]=i;
end
endmodule
// Test bench code for 1 to 8 Demultiplexer using behavioral model
module demux_1to8_tstb; //module demuxtestb_v;
// Inputs
reg [2:0] s;
regi;
// Outputs
wire [7:0] d;
demux_1to8behv a5(d, s, i);
initial begin
// Initialize Inputs
s = 3'b000;
i = 1;
#5 s=3'b001;
#5 s=3'b010;
#5 s=3'b011;
#5 s=3'b100;
#5 s=3'b101;
#5 s=3'b110;
#5 s=3'b111;
end
initial $monitor($time,"inputdata=%b,selectline=%b,output=%b",i,s,d);
initial #60 $stop;
endmodule
Experiment-4
8-Bit Comparator
// 8 Bit comparator Design using gate level model
module comp_8bit(d,a,b,en);
input en;
input[7:0]a,b;
output d;
wire [7:0]c;
wiredd;
xor g1[7:0](c,b,a);
or g2(dd,c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]);
notif1 g3(d,dd,en);
endmodule
// Test bench code for 8 Bit comparator Design using gate level model
modulecomp_tsb;
// Inputs
reg [7:0] a;
 reg [7:0] b;
reg en;
// Outputs
wire d;
comp_8bit a7(d,a,b,en);
initial
begin
a = 8'h00;
b = 8'h00;
en = 1'b0;
end
always
#2 en = 1'b1;
always
begin
#2 a = a+1'b1; #2 b = b+2'd2;
end
initial $monitor($time," en = %b , a = %b ,b = %b ,d = %b ",en,a,b,d);
initial #60 $stop;
endmodule

Experiment-5
SR, D, JK and T- Flip flops
SR FLIFLOP:
// SR Flip Flop design using behavioral model
module srff(s, r, clk, q, qb);
input s;
input r;
input clk;
output q;
output qb;
reg q,qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(posedge clk)
begin
case ({s,r})
2'b00:begin q=q;qb=qb;end
2'b01:begin q=1'b0;qb=1'b1;end
2'b10:begin q=1'b1;qb=1'b0;end
2'b11:begin q=1'b1;qb=1'b1;end
default:begin q=q;qb=qb;end
endcase
end
endmodule
// Test bench code for SR Flip Flop design using behavioral model
module srfftest;
wire q,qb;
reg s,r,clk;
srff g1(s,r,clk,q,qb);
initial
begin
clk=1'b0;
{s,r}=2'b00;
#5 {s,r}=2'b01;
#5 {s,r}=2'b10;
#5 {s,r}=2'b11;
end
always #2 clk=~clk;
initial #100 $stop;
endmodule
D FLIPFLOP:
// D Flip Flop design using behavioral model
module dff(d, clk, q, qb);
input d;
input clk;
output q;
output qb;
reg q,qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(posedge clk)
begin
q=d;
qb=~d;
end
endmodule
// Test bench code for D Flip Flop design using behavioral model
module dfftest;
wire q,qb;
reg d,clk;
dff g1(d,clk,q,qb);
initial
begin
clk=1'b0;
d =1'b0;
#5 d =1'b1;
#5 d =1'b0;
#5 d =1'b1;
end
always #2 clk=~clk;
initial #100 $stop;
endmodule
JK FLIPFLOP
// JK Flip Flop design using behavioral model ( using case statement)
module jkff(j, k, clk, q, qb);
input j;
input k;
input clk;
output q;
output qb;
reg q,qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(posedge clk)
begin
case ({j,k})
2'b00:begin q=q;qb=qb;end
2'b01:begin q=1'b0;qb=1'b1;end
2'b10:begin q=1'b1;qb=1'b0;end
2'b11:begin q=~q;qb=~qb;end
default: begin q=q;qb=qb;end
endcase
end
endmodule
// Test bench code for JK Flip Flop design using behavioral model
module jkfftest;
wire q,qb;
reg j,k,clk;
jkff g1(j,k,clk,q,qb);
initial
begin
clk=1'b0;
{j,k}=2'b00;
#5 {j,k}=2'b01;
#5 {j,k}=2'b10;
#5 {j,k}=2'b11;
end
always #2 clk=~clk;
initial #100 $stop;
endmodule
T FLIPFLOP:
// T Flip Flop design using behavioral model
module tff(t, clk, q, qb);
input t;
input clk;
output q;
output qb;
reg q,qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(posedge clk)
begin
if(t)
begin
q=~q;
qb=~qb;
end
else
begin
q=q;
qb=qb;
end
end
endmodule
// Test bench code for T Flip Flop design using behavioral model
module tfftest;
wire q,qb;
reg t,clk;
tff g1(t,clk,q,qb);
initial
begin
clk=1'b0;
t =1'b0;
#5 t =1'b1;
#5 t =1'b0;
#5 t =1'b1;
end
always #2 clk=~clk;
initial #100 $stop;
endmodule
 Experiment-6
Shift Registers (SIPO and PISO)
SIPO Register
// 4-Bit SIPO Shift registers design using behavioral model
module sipo(q, a, clk, reset);
output [3:0] q;
input a;
input clk;
input reset;
reg [3:0]q;
initial q=4'b0000;
always @ (posedge clk )
begin
if(reset)
q<=4'b0000;
else
begin
q[3]<=a;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
end
endmodule

// Test bench code for 4-Bit SIPO Shift registers design using behavioral model
module sipo_test;
wire [3:0]q;
reg a,clk,reset;
sipo g1(q,a,clk,reset);
initial
begin
a = 1'b0;
clk = 0;
reset = 1'b1;
#2 reset = 1'b0;
end
always #2 clk = ~clk;
always #2 a = ~a;
initial $monitor($time, "q=%b, a = %b, clk = %b,reset = %b",q,a,clk,reset);
initial #20 $stop;
endmodule

PISO Shift Register

// 4-Bit PISO Shift registers design using behavioral model
module piso(q, a, load, clk , reset);
output q;
input [3:0] a;
input load;
input clk ;
input reset;
reg q;
reg [3:0]temp;
initial q = 1'b0;
always @ (posedge clk or posedge reset )
begin
if(reset)
q <= 1'b0;
else if (load)
begin
temp<= a;$display("temp =%b",temp);end
else
begin
q <= temp[3];
temp<= {temp[2:0],1'b0};
end
end
endmodule
// Test bench code for 4-Bit PISO Shift registers design using behavioral model
module tb_piso_v;
reg [3:0] a;
reg load;
reg clk;
reg reset;
wire q;
piso g1 (q, a, load, clk , reset);
initial begin
a = 4'b1010;
load = 1'b1;
clk = 0;
reset = 1'b1;
#2 reset=0;
#4 load=0;
end
always #2 reset = 1'b0;
always #1 clk = ~clk;
initial $monitor($time,"reset = %b,load = %b, clk = %b, a = %b, q= %b",reset,load,clk,a,q);
initial #30 $stop;
endmodule

EXPERIMENT 7
DECADE COUNTER
// 4-Bit Decade counter usingbehavioral model
module decade_counter(a,clk,N);
input clk;
input [3:0]N;
output [3:0]a;
reg [3:0]a;
initial a=4'b0000;
always@(negedge clk) a=(a==N)?4'b0000:a+1'b1;
endmodule
// Test bench code for 4-Bit Decade counter using behavioral model
module decade_tstb;
reg clk;
reg [3:0]N;
wire [3:0]a;
decade_countera3(a,clk,N);
initial
begin
clk = 0;
N = 4'b1001;
end
always #2 clk=~clk;
initial $monitor($time,"a=%b,clk=%b,N=%b",a,clk,N);
initial #100 $stop;
endmodule
Experiment-8
4-Bit Parity generator

// 4 Bit Parity generator design using behavioral model

module parity_generator(p,a,en);
input [3:0]a;
input en;
output p;
reg p;
always @ (posedge en)
begin
p=n1 (a) % 2 ;
$display ( $time, "a=%b,en=%b,p=%b",a,en,p);
end
function integer n1;
input [3:0]a;
integer i;
for(i=0;i!=3;i=i+1)
begin
if (i==0) n1=0;
if(a[i])n1=n1+1;
end
endfunction
endmodule
// Test bench code for 4 Bit Parity generator Design using behavioral model
module parity_tstb;
// Inputs
reg [3:0] a;
reg en;

// Outputs
wire p;
parity_generator a7(p,a,en);
initial begin
en=0;
a=4'b0;
end
always #2 en=~en;
always #4 a=a+1'b1;
initial #50 $stop;
endmodule

Experiment-9
4-Bit ALU
// 4 Bit ALU Design using data flow model
module alu_bit_dataflow(d,co,a,b,f,cci);
output[3:0]d;
output co;
input [3:0]a,b;
input[1:0]f;
input cci;
assign {co,d}=(f==2'b00)?(a+b+cci):((f==2'b01)?(a-b):((f==2'b10)?{1'bz,a^b}:{1'bz,~a}));
endmodule
// Test bench code for 4 Bit ALU Design using data flow model
module alu_4bit_data_tstb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [1:0] f;
reg cci;
// Outputs
wire [3:0] d;
wire co;
alu_bit_dataflowa7(d,co,a,b,f,cci);
initial
begin
 // Initialize Inputs
a =4'b1010;
b =4'b0011;
f =2'b00;
cci =1'b0;
#2 f =2'b01;
#2 f=2'b10;
#2 f=2'b11;
end
initial $monitor($time,"cci=%b,a=%b,b=%b,f=%b,d=%b,co=%b",cci,a,b,f,d,co);
initial #60 $stop;
endmodule

Experiment-10
Moore and Mealy
Moore state machine:
// Moore machine design using behavioral model
//sequence generator
//moore machine_a
`define s0 3'b000//wxyz=1000
`define s1 3'b001//wxyz=1100
`define s2 3'b010//0100
`define s3 3'b011//0110
`define s4 3'b100//0010
`define s5 3'b101//0011
`define s6 3'b110//0001
`define s7 3'b111//1001
module a_seqmoorev(clr,clk,w,x,y,z);
input clr,clk;
output w,x,y,z;
reg w,x,y,z;
reg [2:0]present_state;
always@(present_state)
begin
case(present_state)
`s0: {w,x,y,z}=4'b1000;
`s1: {w,x,y,z}=4'b1100;
`s2: {w,x,y,z}=4'b0100;
`s3: {w,x,y,z}=4'b0110;
`s4: {w,x,y,z}=4'b0010;
`s5: {w,x,y,z}=4'b0011;
`s6: {w,x,y,z}=4'b0001;
`s7: {w,x,y,z}=4'b1001;
endcase
end
always@(posedge clk)
begin
if (clr) present_state =`s0;
else begin
case(present_state)
`s0: present_state=`s1;
`s1: present_state=`s2;
`s2: present_state=`s3;
`s3: present_state=`s4;
`s4: present_state=`s5;
`s5: present_state=`s6;
`s6: present_state=`s7;
`s7: present_state=`s0;
default: present_state=`s0;
endcase
end
end
endmodule
// Test bench code for Moore machine design using behavioral model
module test_a_seqmoorev();
reg clr,clk;
wire w,x,y,z;
a_seqmoorev vv(clr,clk,w,x,y,z);
initial begin clk=1'b0;clr=1'b1; #3 clr =1'b0; #50 $stop; end
always #2 clk = ~clk;
initial #100 $stop;
initial $monitor($time, "clk=%b,clr=%b,w=%b,x=%b,y=%b,z=%b",clk,clr,w,x,y,z);
endmodule

// Sequence detector code for 101 overlapping sequence

module seqdet(q,x,clk,clr);
parameter s0=2'b00;
parameter s1=2'b01;
parameter s2=2'b11;
output reg q;
input x,clk,clr;
reg [1:0]ps;
initial ps=s0;
always @(posedge clk)
begin
if(clr)ps=s0;
else
begin
case (ps)
s0:begin ps=x?s1:s0;q=0; end
s1:begin ps=~x?s2:s1;q=0; end
s2:begin ps=x?s1:s0;q=x?1:0; end
endcase
end
end
endmodule

// Test bench for Sequence detector for 101 overlapping sequence

module seqdettest;
wire q;
reg x,clk,clr;
seqdet g1(q,x,clk,clr);
initial
begin
clk=0;
clr=1;
x=0;
#4 clr=0;
#4 x=1;
#4 x=0;
#4 x=1;
#4 x=0;
#4 x=1;
end
always #2 clk=~clk;
initial $monitor($time,"clk=%b,clr=%b,x=%b,q=%b",clk,clr,x,q);
initial #30 $stop;
endmodule