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21EC71 - Module 1 1

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41 views14 pages

21EC71 - Module 1 1

Uploaded by

dhanushvgowda2803
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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21EC71

Advanced VLSI

Dr. Manasa M G; Dinesh M A


Adopted from the slides of Prof. Jagannath B R
INTRODUCTION TO Module-1
ASICs
INTRODUCTION TO ASICs

• An ASIC (“a-sick”) is an application-specific integrated circuit

9/4/20XX Presentation Title 3


Types of ASICs

• ICs are made on a wafer. Circuits are built up with successive


mask layers.
• The number of masks used to define the interconnect and other
layers is different between full-custom ICs and programmable
ASICs
• Full-custom ICs
• Semi-custom ICs
• Standard-cell-based ASICs
• Gate-array-based ASICs

9/4/20XX Presentation Title 4


Types of ASICs

Standard Cell Gate Array Programmable


based based ASICs ASICs
• Channelled • Programmable
• Channelless gate array
• Structured • Filed
Gated Array Programmable
gate array
Full-custom offers the highest
All mask layers are customized in performance and lowest part cost
a full-custom ASIC. It only makes (smallest die size) with the
sense to design a full-custom IC if disadvantages of increased
there are no libraries available design time, complexity,
(Speed, Size and Power) design expense, and highest
risk

Full-Custom ASICs

Other examples of full-custom


Microprocessors were exclusively
ICs or ASICs are requirements for
full-custom, but designers are
high-voltage (automobile),
increasingly turning to
analog/digital
semicustom ASIC techniques in
(communications), or sensors
this area too
and actuators.
Standard-Cell–Based ASICs

• A cell-based ASIC (CBIC—“sea-bick”)


• predesigned logic cells (AND gates, OR gates,
multiplexers, and flip-flops, for example) known as
standard cells
• Possibly megacells, megafunctions, fullcustom
blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks
(FSBs)
• All mask layers are customized—transistors and
interconnect
• Custom blocks can be embedded
• Manufacturing lead time is about eight weeks.
Standard-Cell–Based ASICs

• In datapath (DP) logic we


may use a datapath
compiler and a datapath
library. Cells such as
arithmetic and logical units
(ALUs) are pitch-matched
to each other to improve
timing and density
9/4/20XX Presentation Title 9
Gate-Array–Based ASICs

A gate array, masked gate array


(MGA), or pre-diffused array uses
macros (books) to reduce Structured
gate Array
Channelled

turnaround time and comprises a


base array made from a base cell
or primitive cell
Channelless
Channelled Gate Array

Channelled
gate Array
One difference is that the
The space for interconnect
interconnect between rows of cells are
Manufacturing fixed in height in a channeled
Only uses
Lead time is 2 gate array, whereas the
Interconnect is predefined
days to 2 space between rows of cells
customised spaces
weeks may be adjusted in a CBIC.
between Rows
of Base cells
Channelless Gate Array

Channelless gate
Array
Manufacturing
Also called Top Few mask
Lead time is 2
SEA of Gate are
days to 2
ARRAY customized
weeks

The key difference between a channelless gate array and channeled gate array is that there are no
predefined areas set aside for routing between cells on a channelless gate array.
Instead we route over the top of the gate-array devices.
The logic density - the amount of logic that can be implemented in a given silicon area is higher for
channelless gate arrays than for channeled gate arrays. This is usually attributed to the difference in
structure between the two types of array.
Structured Gate Array

Structured
gate Array
Only Manufacturing
Custom Blocks
Interconnects Lead time is 2
can be
are days to 2
embedded
Customized weeks
Programmable Logic Devices

Examples and types of PLDs:


• read-only memory (ROM)
• programmable ROM or PROM
• electrically programmable ROM, or EPROM
• An erasable PLD (EPLD)
• electrically erasable PROM, or EEPROM
• UV-erasable PROM, or UVPROM
• mask-programmable ROM
• A mask-programmed PLD usually uses bipolar technology Logic
arrays may be either a Programmable Array Logic (PAL®, a registered
trademark of AMD) or a programmable logic array (PLA); both have
an AND plane and an OR plane

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