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21EC71 - Module 1 3

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25 views

21EC71 - Module 1 3

Uploaded by

dhanushvgowda2803
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© © All Rights Reserved
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You are on page 1/ 14

9/4/20XX Presentation Title 29

The Carry equations allow us to build the carry


chain from two-input NAND gates, one per cell,
using different logic in even and odd stages

9/4/20XX Presentation Title 30


Carry-save adder (CSA)

• CSA (A1[i], A2[i], A3[i ], CIN, S1[i], S2[i], COUT) has three
outputs:

9/4/20XX Presentation Title 31


Carry-save adder (CSA)

• The carries are “saved” at each stage and shifted left onto
the bus S1.
• So there is no carry propagation and the delay of a CSA is
constant.
• At the output we still need to add all the saved carries and
all the sums to get n-bit result.

9/4/20XX Presentation Title 32


• We can use a CSA to add multiple inputs ( Ex.: an adder
with four 4-bit inputs)
• The last stage sums two input buses using a carry-
propagate adder (CPA) (RCA has been used as CPA; but
any adder type can be used)
• Two CSA cells and one RCA cell form a bit-slice (or slice)
• 4 slices are stacked vertically to form the Datapath

9/4/20XX Presentation Title 33


• By using registers between stages of combinational logic
we use pipelining to increase the speed and pay a price of
increased area (for the registers) and introduce latency.
(latency is the time it takes for a clock signal to travel from its
source to the clock pin of a flip-flop.)
• It takes a few clock cycles to fill the pipeline, but once it is
filled the answers emerge every clock cycle.

9/4/20XX Presentation Title 34


carry-bypass adders (CBA)

• The problem with an RCA is that every stage has to wait to make
its carry decision, C[i], until the previous stage has calculated C[i
-1].
• If we examine the propagate signals we can bypass this critical
path.
• for example. to bypass the carries for bits 4-7 (stages 5-8) of an
adder we can compute BYPASS = P[4].P[5].P[6].P[7] and then use
a MUX as C[7]=(G[7]+P[7]·C[6])·BYPASS'+C[3]·BYPASS
• Manchester-carry chains can compute the carries and the
bypass operation using TGs or just pass transistors.

9/4/20XX Presentation Title 35


Carry-skip Adder

• Instead of checking the propagate signals we can check the


inputs.
• For example we can compute
SKIP = (A[i − 1]⨁ B[i − 1]) + (A[i]⨁ B[i])
CSKIP i = G i + P i . C i − 1 . SKIP + C i − 2 . SKIP
• Carry-bypass and carry-skip adders may include redundant
logic (carry is computed in two different ways).
• Logic synthesis process may optimize way the redundant logic.

9/4/20XX Presentation Title 36


Carry-lookahead Adder (CLA)

• If we evaluate the above


equation recursively for
i=1,2,3…
• We can “look ahead” by
two stages and calculate
the carry into the third
stage (bit 2), which is
C[1], using only the first-
stage inputs.
9/4/20XX Presentation Title 37
• As we look ahead further these equations become more
complex.
• Take longer to calculate and the logic becomes less
regular.
• The physical and logical structure of each bit must be
similar, so that the Datapath layout fits in a bit slice.
• Regular structures are not of concern in standard cell or
gate array logic.

9/4/20XX Presentation Title 38


Brent-Kung adder

• Reduces the
delay and
increases the
regularity of the
carry-Iookahead
scheme

9/4/20XX Presentation Title 39


Brent-Kung adder

• Carry generation in a 4-bit CLA.

9/4/20XX Presentation Title 40


Brent-Kung adder

• A cell to generate the lookahead terms. C[0]-C[3].

9/4/20XX Presentation Title 41


Brent-Kung adder

• Cells L1, L2, and L3 are rearranged into a tree that has less delay.
Cell L4 is added to calculate C[2] that is lost in the translation.

9/4/20XX Presentation Title 42

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