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EEE 4307 All Questions

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EEE 4307 All Questions

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Name of the Program: B. Sc.

in Electrical and Electronic Date: 07 September, 20211


Engineering
Semester: Winter Time: 10:30 am – 12:00 pm

ISLAMIC UNIVERSITY OF TECHNOLOGY (IUT)


ORGANISATION OF ISLAMIC COOPERATION (OIC)
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

Semester Final Examination Winter Semester: 2020 - 2021


Course Number: EEE 4307 Full Marks: 75
Course Title: Digital Electronics Time: 1.5 Hours

There are 3 (three) questions. Answer 3 (three) questions. The symbols have their usual
meanings. The examination is Online and Open Book. Marks of each question and
corresponding CO and PO are written in the brackets.

1 (a) Explain the operation of an SR flip-flop if you provide S = 1, R = 1. (7)


(CO1)
(PO1)
(PO2)
(b) For a negative edge-triggered J-K flip-flop with inputs as shown in figure (9)
1(b), determine the Q output relative to the clock. Assume Q starts LOW. (CO1)
(PO1,
PO2)

Figure 1(b)

(c) Convert a D flip-flop to a J-K flip-flop by including input gates to the D (9)
flip-flop. The gates needed for the input of the D flip-flop can be (CO2)
determined by means of sequential-circuit design procedures. The (PO1,
sequential circuit to be considered will have one D flip-flop and two inputs, PO3)
J and K.

Page 1
2 (a) Construct a state table for the circuit shown in figure 2.a and identify the (9)
stable states of the circuit. Derive a Boolean expression for the next value (CO4)
(PO1,
of the output Q in terms of Q, A, and B.
PO4)

Figure 2.a

(b) Design a synchronous counter that will produce the binary equivalent of the (9)
following sequence up to the binary value of 5 as shown in the following (CO5)
table. (PO1,
PO9,
PO12)

(c) Implement the following logic circuit in CMOS. (7)


(CO4)
(PO1,
PO4)

Figure 2.c

Page 2
3 (a) Design a sequence detector using R-S flip-flop that has a form shown in (10)
figure 3.a. The output Z should be 1 if the input sequence ends in either 111 (CO4)
or 0110 and Z should be 0 otherwise. For example: (PO1,
PO4)
X 01110110111011001

Z 00010001001000100

Figure 3.a

(b) Design a (256K × 16) bit RAM. You must show the logic diagram, address (9)
lines, read/write input, data inputs, and data outputs. (CO5)
(PO1,
PO9,
PO12)
(c) (i) How many 64K × 16 RAM chips are needed to provide a memory (6)
capacity of 4MB? (CO2)
(PO1,
(ii) How many address lines are required to access 4 MB? How many of PO3)
these lines are connected to the address inputs of all chips?

(iii) How many lines must be decoded to produce the chip select inputs?
Specify the size of the decoder.

Page 3

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