Distributed Gate ESD Network Architecture for Inter-

Power Domain Signals

Eugene R. Worley
Conexant Systems
4000 McArthur Blvd., Newport Beach, CA 92660
Tel: (949) 483-4922, FAX: (949) 483-9501, e-mail: [email protected]

Abstract - This paper examines the issue of transmitting signals between circuits of different power domains within
an IC and the ESD sensitivity of the receiving logic’s oxide in advanced processes. It is also shown that the ESD
stress voltage appearing across a receiving gate’s oxide can be distributed among several inverters. Also, design of
interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will
be examined.

digital circuit, with a significant circuit block-to-

I. Introduction tester-plate capacitance, CcdmD, is connected to a
small area block, say a PLL circuit with a small
In mixed signal chips, power connections to various block-to-CDM-plate-capacitance, CcdmA. Although
circuit blocks are independent of each other to reduce the CDM capacitance is distributed, it is lumped here
noise coupling. A circuit block with independent for illustration purposes. Also shown in the figure is a
power pads will be referred to as a power domain. signal connection between two blocks and the
Signal lines are typically required to connect one corresponding terminating logic gates, in this case two
circuit block with an independent power supply inverters, InvA and InvD. It will be assumed that a
connection to another block. Thus, under normal positive charge exists on the chip relative to the CDM
operating conditions, only signal lines connect a tester plate, which is considered to be ground. Diode
circuit of one power domain to the circuit of another Ds represents the parasitic drain/substrate diode of the
power domain. During an ESD event, however, a NFET of InvD that can couple VssD to the signal line.
means is required to link the power domain buses The worst-case discharge is from the analog power
together otherwise the voltage drop between domains pin to the CDM plate or ground. Note that, because of
can become large and rupture the gate oxide of input the small analog domain CDM capacitance, CcdmA,
logic that receives signals from another domain. The the VssA node rapidly discharges to ground with V4,
means that is typically used to link power domains the Vss potential of InvA, going to ground potential
together during an ESD event yet isolate the domains very early in the discharge. CcdmD must discharge
during normal operation are back-to-back diodes through the VssD bus resistance and the VssA
placed between the power nodes of the various resistance, and the coupling diode D1, as shown by
domains. But, with multiple diode drops and bus IR the arrows. Assume that the effective resistance
drops combined with gate oxides that are expected to between node points V1 and V2 is 1 Ω for the lumped
ultimately go to 12Å, a simple, non-disciplined capacitor, CcdmD, the “on” resistance of D1 is 0.2Ω,
approach of back-to-back diode placement will result and the resistance between V3 and VssA pad is 1Ω.
in poor CDM performance [1,2] and even poor HBM For a 5A discharge current and a diode offset voltage
performance. Note that there can be many series back- of 1.1V the voltage drop from V1 to V4 is 12.1V, a
to-back diodes in an ESD discharge path if the path voltage high enough to rupture a 20 Å oxide as will be
involves crossing many domains. Also, it is not shown later.
uncommon to find a transmitting gate of one power
domain having a high fan-out to many receiving gates The above example shows how even small bus
of a second power domain or even to logic gates of resistances in the discharge path can make thin gate
many different power domains. oxides of power domain to power domain interface
gates susceptible to gate oxide rupture during a CDM
Fig. 1 shows a diagram illustrating the current path event.
and voltage drops of a CDM discharge involving a
signal line running between two power domains. The
worst-case situation is when a large area block, say a

1-58537-063-0
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 leakage current is 4.9nA, which is the normal oxide
VssA leakage. Also notice that the oxide TLP current rises
Substrate above the background level at about 4.65V. The TLP
Tie
Rings current reaches a maximum at 2.2mA and then
D1 collapses to 0 just after 6.0V. The leakage current
CcdmA reaches a maximum, 590µA, at 6.0V thus indicating
V3 V2 an oxide short then collapses to 2.3nA. It is apparent
that the oxide gate has blown open beyond 6V. This
V4
D2 NFET’s gate oxide is conducting only 2mA or
InvA 40µA/µm of width just before failure, a small value
Ds relative to the TLP current flowing in an ESD current
Signal Line
shunting network. Just after failure the current is
InvD V1 2.2mA. For the PFET the current just before rupture is
1.4mA or 28µA/µm.
CcdmD

VssD
2.5 1.0E-02
Itlp
Fig. 1. Example of voltage drops associated with a CDM 2.0 1.0E-03
Ileak
discharge. 1.0E-04

[email protected] (A)
Itlp (mA) 1.5
1.0E-05
II. Oxide Rupture Voltage 1.0
1.0E-06
0.5
To understand the susceptibility of cross domain 1.0E-07
interface logic gates to ESD it is first necessary to 0.0 1.0E-08
examine the failure criteria for gate oxides. According
-0.5 1.0E-09
to Wu [3] the following gate oxide rupture equation
2 3 4 5 6 7 8
can be applied for rectangular pulses:
Vtlp (V)
Vg _ fail − Voffset = 4.31Tox / ln(1792t pulse ) (1)
Fig. 2. TLP I-V and leakage plot of a 20Å NFET gate oxide.

where Vg_fail = the oxide failure voltage, Voffset = the Eq. 1, unfortunately, cannot be used to predict the
conduction offset voltage that is dependent on a peak rupture voltage for an HBM waveform. Since
number of factors such as work function difference, the electric fields in ultra-thin oxides during ESD
poly depletion voltage, and substrate voltage drop, Tox stress are very high, conduction is dominated by
= oxide thickness in Å, and tpulse = pulse width in ns. Fowler-Nordheim (FN) tunneling and not by direct
Using a Barth 100ns TLP, it was found that for tunneling. If it is assumed that an accumulated charge
NFETs with a 20Å the average gate oxide rupture was threshold causes breakdown and that the charge
5.9V for a positive pulse and for PFETs the average conduction is essentially exponential with 1/Eox then
gate oxide rupture was 7.0V for a negative pulse. it can be inferred that
Thus, the offset term, Voffset, is -1.22V for 20 Å aTox
−
NFETs and -0.1V for 20 Å PFETs and is consistent trupture Vg ( t ) −Voffset
with that reported in [4]. Thus, for a 1ns CDM pulse
the rupture voltage for a 20 Å NFET oxide is 10.3V
to = ∫
0
e
-13
dt (2)
where to = 5.58 x 10 sec and a = 4.31V/ Å. Note
using Eq. 1.
that integration of Eq. 2 results in Eq. 1 for a positive
rectangular pulse. Eq. 1 was numerically integrated
The high impedance nature of oxide conduction at
for a 20Å NFET oxide using an HBM waveform with
failure is evident in Fig. 2, which shows a composite
a linear rise time of 8ns and an exponential fall time
TLP I-V and Ileak-V plot of a 20Å oxide with the test
constant of 150ns resulting in a peak NFET
data being collected on the Barth 100ns TLP system.
breakdown voltage of 7.3V.
The leakage was measured at 1.2V for the
50µm/0.15µm test NFET. Notice that before 6V the

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If it is assumed that for ultra-thin oxides Eqs. 1 and 2 capacitance of domain 1 is contained in Css1. What is
are still valid then for a 12Å NFET oxide the failure of interest in this case is the voltage drop between
voltage would be 5.7V for a 1ns rectangular pulse and Vdd1 at Inv1 and Vdd2 at Inv2. Assume that Vdd2 is
3.9V peak for an HBM waveform. Ultra-thin oxides, grounded for the CDM discharge and that the CDM
therefore, pose an HBM threat as well as a CDM capacitances of domain 2 are quickly discharged. The
threat for domain-to-domain interface gates. CDM current flows from the Vdd2 pad, through
Clamp2, though the Vss2 bus to the back-to-back
III. Interface to Adjacent Blocks diodes, Dvss, through the back-to-back diodes, and
through the Vss1 bus to the distributed CDM
capacitance Css1. A small current component will
An example of a typical haphazard power domain to
flow through the N well/P substrate parasitic diode
power domain signal interface is shown in Fig. 3 in
Dws1 to discharge Cdd1. The voltage drop between
which the circuit blocks of two isolated power
Vdd2 at Inv2 and Vdd1 at Inv1 is therefore
domains are adjacent to each other. In this
implementation the power bus clamps, Clamp1 and
V dd ( Inv 2 − Inv1) = Vclamp 2 + Rvss 2 I cdm + V Dvss + RCss 1 I cdm + V Dws 1
Clamp2, are located near the power bus pads. Also
located near the power bus pads Vdd1 and Vss1 is a
set of back-to-back Vss bus coupling diodes. It should = V offClamp + 2V offD + (R Clamp + RVss 2 + RVss1 + R Dss )I cdm (3)
be noted that the location of the ESD clamps near
power pads is a typical layout style since it is where VoffClamp is the offset voltage of the power bus
convenient to place the clamps within the power pad Clamp 2, VoffD is the offset voltage of the Dvss and
cells. A signal that is transmitted from Inv1 associated Dws1 diodes, Rclamp is the effective series resistance of
with domain 1 is received by a number of gates in Clamp 2, RVss2 is the resistance of Vss2 from Clamp2
domain 2 which are scattered about the domain. to Dvss, RVss1 is the effective resistance of Vss1 from
Assume that power domain 1 represents a large core Dvss to Dws1, and RDvss is the series resistance of
circuit with a significant amount of CDM capacitance diode Dvss. It is assumed that the voltage drop across
and that power domain 2 represents a small circuit Dws1 is primarily the offset voltage with the IR
such as a PLL and has a small amount of CDM component being negligible since most of the CDM
capacitance. current is assumed to be flowing into Css1 with a
smaller amount flowing into Cdd1.
Vdd1
Vdd2
Inv1 Inv2
Clamp
For the power bus clamp such as Clamp2, 3 series
2
diodes will be assumed. 3 series diodes were found to
Vss2 have the highest conduction density, 1.5mA/µm2,
Vss1 relative to NFET snap-back devices and BigFETs or
transient clamps. For a worst-case leakage current of
Cdd1 Css1 10µA at 125ºC and 1.32V, a 3-stack diode can be
realized with an “on” resistance (Rclamp) of 0.7Ω and
an offset voltage of 3.3V. Reasonable values for ESD
diodes are 1.1V for the conduction offset voltage and
Dws1
Vdd1 0.2Ω “on” resistance and for RVss2 assume a value of
1Ω and for RVss2 a value of 0.5Ω. Thus, for this case
Dvss
Vdd(Inv2-Inv1)=5.5V+2.4Icdm. For a 5A CMD pulse the
Clamp voltage drop is 17.5V, which is way too high for a 20
1 Å oxide.
Vss1

The best way to layout an interface between the

Fig. 3. Example of a haphazard domain to domain signal interface. circuits of two adjacent, isolated power domains that
have interconnecting signals is to use a structured
To get an idea of the intra domain voltage drop that interface block as illustrated in Fig. 4. Changes made
can be incurred for this layout style assume that Cdd1 from the circuit of Fig. 3 include a receiving buffer,
and Css1 are negatively charged with respect to chuck InvB, to eliminate the fan-out to scattered gates,
ground. Also assume that most of the CDM relocating the Vss back-to-back diodes to be near the

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Vss buses of Inv1 and InvB, adding back-to-back
diodes, Dvdd, to the Vdd buses, and placing the (R Clamp + 2 RD )I cdm + VoffD
(R + RD )
power bus clamps near the interface gates Inv1 and Clamp
InvB. Placing the power bus clamps near the interface 2 RClamp + 3RD
gates is typically not an issue since external chip
interfaces use a separate, higher voltage bus with Using the previous parameters Eq. 5 is equal to
different power bus clamps. For this configuration, 4.9+0.5ICDM. Thus, for a CDM current of 5A the
the worst case destructive voltage drop is between voltage drop is 7.4V.
Vdd2 at InvB and Vss1 of Inv1 which is caused by
shorting Vdd2 to ground with the chip charged The above analysis neglects the transient clamping
negatively. Again, it is assumed that Css1 is much effect of the core circuitry and the effects of Vdd-to-
larger than Cdd1. The voltage drop due to a CDM Vss capacitance. The transient response of the core
current is given by circuitry is very complex and difficult to simulate.
The effect of the Vdd to Vss capacitance can be
1 estimated providing the effective series resistance is
VddInv 2 − VssInv1 = VoffClamp + VoffD + (RClamp + RD )I cdm (4) small or the effective time constant associated with
2
the capacitance and its parasitic series resistance is
where RD is the ‘on” resistance of the back-to-back much smaller than the CDM rise time. If we assume
diodes. Note that there are two current paths from that it takes 400ps to reach 4V across the Vdd to Vss
Vdd2 to Vss1; one through the Vdd diodes and Clamp buses then the CDM current shunted by this
1 and the other through the Vss diodes and Clamp 2. capacitance is 10mA/pF.
For the same parameter values as before Eq. 4 is equal
to 4.4V + 0.45ICDM. For ICDM = 5A the voltage drop is For HBM the core circuitry transient clamping effect
therefore 6.65V which has a margin of about 3.7V for and the Vdd to Vss capacitance clamping effect is
a 20Å oxide. typically very small and can be neglected. Looking at
Dvdd Fig. 3 and assuming that the Vdd1 pad is grounded
Vdd1
Vdd2 and a positive discharge is applied to the Vdd2 pad
InvB then the voltage drop in going from the Vdd2 pad,
Inv1
through Clamp2, through the Vss2 bus from Clamp 2
Vss2 to Dvss, through Dvss, from Vss1 at Dvss to Vss1 at
Clamp Clamp Dws1, through Dws1, and through the Vdd1 bus to
1 2 the Vdd1 pad from Dws1 is given by
Cdd1 Css1
Vdd ( Inv1− Inv 2 ) = Vclamp 2 + Rvss 2 I hbm + VDvss (6)

Vdd1 + RVss 1 I hbm + V Dws 1 + RVdd 1 I hbm

Vss1 = V offClamp + 2VoffD (7)

+ (RClamp + Rvss 2 + R Dvss + RVss1 + R Dws1 + RVdd 1 )I hbm
Fig. 4. Example of a structured domain to domain signal interface.
As before, assume that VcffClamp = 3.3V, VcffD = 1.1V
If power supply sequencing is an issue for Vdd1 and Rclamp = 0.7Ω, Rvss2 = 1.0Ω, RDvss = 0.2Ω, Rvss1 = 0.5Ω,
Vdd2 then the single back-to-back diodes of Fig. 4 RDws1 = 0.2Ω, and RVdd1 = 0.5Ω. Thus, for a 2kV HBM
between Vdd1 and Vdd2 can be replaced by two discharge with a peak current of 1.33A the peak
series back-to-back diodes. For two series diodes it voltage appearing from Vdd1 to Vdd2 is 5.5V +
was found that no more than a few mA would flow 3.1Ihbm or 9.63V. Note that the gate oxide of Inv2 can
between the Vdd buses worst case if one bus is turned support a current on the order of 1mA just before
on ahead of the other. For this case the voltage drop rupture. This relatively small current can forward bias
between Vdd2 at InvB and Vss2 at Inv1 is given by the PFET drain/well diode of Inv1 causing a voltage
drop of about 0.8V from the output of Inv1 to Vdd1.
Vdd ( Inv1− Inv 2 ) = VoffClamp + VoffD + (5) Thus, the PFET gate oxide of Inv2 is exposed to a
voltage of 8.83V, high enough to rupture the oxide.

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 current that can flow from VddA1 to VssA4 is 0.824A
For Fig. 4 the worst case discharge is from Vdd2 to or 1.24kV HBM and for CDM about 2.47A. It should
Vss1 or from Vdd1 to Vss2. For Vdd2 to Vss1 Eq. 4 be noted that extending the bus out from the ends and
is valid. Assuming the same parameters as in the case adding 600µm bus clamps between intervals of 3Ω of
for Fig. 3 the voltage drop from Vdd2 to Vss1 is given bus resistance wouldn’t improve this result much.
by 4.4V + 0.45IHBM. Thus, for a 2kV HBM discharge Thus, for the approach of Fig. 5 it becomes difficult to
the peak voltage is 5.0V, well within the oxide rupture maintain sufficiently low voltage drops between
voltage of both NFETs and PFETs. transmitting and receiving gates of different,
independent power domains as oxide thicknesses are
Another consideration for the circuit of Fig. 4 is to use scaled down.
HV transistors for the receiving inverter, InvB, if
speed is not an issue. The speed issue can be A1 A2 A3 A4
mitigated by using two inverters for the interface with
the receiving inverter made of HV transistors and a VssA1 VddA1
VddA4 VssA4
second, buffering inverter made of LV transistors.
3.3V HV transistors can tolerate roughly 3 times the
gate stress voltage as 1.2V LV transistors. Inv1 Inv2

IV. Interface to Remote Blocks D1

D2 D4 Bus Bus D8
Clamp Clamp
D5 D7
D3 D6
VddESD
This section will deal with circuit blocks with VssESD
independent power domains that communicate with Fig. 5. An existing ESD network for circuits of different power
each other but are not adjacent to each other. Fig. 5 domains.
shows a diagram of an existing ESD network design
for circuit blocks with isolated power domains. Two Fig. 6 shows a relatively common case where a digital
dedicated ESD buses are used, VssESD and VddESD, circuit block, labeled “Digital Block”, spans the
which can also be used as global power buses. Bi- distance between a circuit block A1, the transmitting
directional diodes such as D1 and D2 are used to link block, and a second circuit block, A4, the receiving
the power buses of circuit blocks such as A1 and A4 block. The digital block is used as a transport block
to the ESD buses. Distributed along the 2 ESD buses for the signal being transmitted from A1 to A4. That
are bus clamps, which can be either NFET snap-back is, the digital block contains both a receiving gate,
devices or BigFETs. For 20Å NFETs with a grounded Inv3, and a transmitting gate, Inv4, for the signal from
gate the trigger voltage is 5.5V, the conduction offset Inv1 of block A1. Note that the voltage difference
voltage is 3.6V, and the width conduction resistance is between the VssA1 and VssD and the voltage
286 Ω-µm. The worst-case discharge for this ESD difference between VddA1 and VddD is only one
network is a discharge from a VssA to a VddA. For diode drop. The same is true for the voltage difference
example, assume that there is a discharge from between VssA4 and VssD and between VddA4 and
VddA1 to VssA4. Also assume that there are two VddD. The worst case HBM stress would be a
NFET bus clamps each of which has a width of discharge from a Vdd to a Vss such as a discharge
600µm and that the bus resistance between clamps is from VddA1 to VssD. In this case the voltage that
3Ω, a maximum value specified by a foundry. Further could appear on the input of Inv3 would be a bypass
assume that one of the two clamps is located at the capacitor/bus clamp drop plus a diode drop. Thus,
anode of D8 of Fig. 5 and that the cathode of D3 is inserting inverters in the signal path from A1 to A4
located between the two clamps on the VddESD bus. and placing these inverters close to the transmitting or
For each clamp it will be assumed that the conduction receiving gate significantly lowers the gate oxide
offset voltage is 3.6V and that the conduction stress for domain to domain interface circuits over the
resistance is 286Ω-µm/600µm or 0.477Ω and for the case of Fig. 5. Thus, the strategic distribution of
diodes D3 and D8 an offset voltage of 1.1V and a buffer inverters in the signal path lowers the voltage
resistance of 0.2Ω. The resulting voltage drop stress any gate oxide experiences in an ESD event.
between VddA1 and VssA4 is given by
5.8V+1.82Iesd. Thus, to keep the peak HBM voltage
under 7.3V for a 20Å NFET oxide the maximum

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 label VddESD are used. The dedicated ESD buses
A1 A2 A3 A4 have power applied to them. The powered ESD buses
VssA1 VddA1 VddA4 VssA4 thus allow the transmitting and receiving logic gates
to be located near each other with bi-directional
Power
Bus
Clamp
Power
Bus
Clamp
coupling diodes used to link the various power buses
of the circuit blocks to the ESD buses. Also, bus
Inv1 clamps can be located in the ESD bus region and
Inv2
hooked up to the ESD buses as shown and, because of
the bi-directional diode clamps between the block
D1
D2 D3 D4 power buses and ESD buses, the ESD bus clamps are
VddD shared with the block power buses thereby creating
VssD
shunt paths between the Vdd’s and Vss’s of the circuit
blocks. Thus, the ESD bus network including bus
Inv3 Inv4 coupling diodes, interface logic gates, and power bus
clamps is placed between circuit blocks as shown and
is used as the routing channel for signal lines that go
Digital Block between circuit blocks with independent power buses.

A1 A2 A3 A4
VssA1 VddA1 VssA2 VddA2 VddA3 VssA3 VddA4 VssA4
Fig. 6. Using an adjacent, “third party” block to transmit a signal DS
from one block to another.
Inv2
Inv1
Fig. 7 shows the case where there is no adjacent “third
party” block that spans the distance from a signal-
transmitting block to a receiving block as in the case
of Fig. 3. For this case the signal is transmitted from Dbb2 Dbb1

A1 (Inv1) to A4 (Inv4) through the intervening blocks Inv3 Bus

Clamp
Bus
Clamp Inv4
A2 and A3 using inverters, Inv2 and Inv3, within the
block boundaries. Not shown are the power supply VddESD
bus clamps for each domain. Thus, the clamping
effect for each of the interface inverters is similar to VssESD

that of Fig. 4. Note also that the signal can be received Dvdd

by multiple blocks, in this case potentially A2 and A3,

by making a tap into the signal path.

A1 A2 A3 A4
Inv1 Inv2 Inv3 Inv4
VddA1 VssB1 VddB1 VddB2 VssB2 VddB3 VssB3 VssB4 VddB4
VddA4

VssA1 VssA4
B1 B2 B3 B4

Fig. 8. Using a powered VssESD and VddESD to localize

different power bus connections between a signal transmitting
logic gate and the corresponding receiving gate.
B1 B2 B3 B4
The ESD buses can be operated at higher voltages so
Fig. 7. Using intervening blocks to transmit a signal from one
that high voltage drivers can be used to send a signal
block to another from one block to another. In most integrated circuits
high voltage transistors are provided for the I/O while
Fig. 8 shows another case in which the power bus for low voltage transistors are used for the interior logic.
the transmitting logic gate is local to the power bus of For example, in a 0.13µm process the interior logic
the receiving gate. In this case a dedicated ESD Vss transistors use MOSFETs with 20 Å oxides that
bus labeled VssESD and a dedicated ESD Vdd bus operate at 1.2V whereas the I/O circuits use

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MOSFETs with 65 Å oxides that operate at 3.3V.
Thus, if VddESD is 3.3V and VddA1 is 1.2V then
V. Resistor-Clamp Interface
Inv3 would be a level-shifting gate. Also, for reduced As seen from the previous examples, it gets harder to
performance, 3.3V transistors can be operated from lower the voltage drop between independent power
the low voltage (1.2V in this example) or core supply. domain buses as the gate oxide of the low voltage
The advantage in using high voltage transistors to transistor is scaled down. Rather than trying to lower
transmit the signals between blocks is that the the voltage drop of the current shunt path between
resistance of the VddESD and the VssESD buses can domains, an alternative is to increase the voltage
be on the order of several Ohms from the transmitting tolerance of the cross-domain interface logic. This can
point to the receiving point. That is, the resistance be accomplished by a resistor-clamp approach as
from the Vdd of Inv3 to the Vdd of Inv4 can be shown in Fig. 9. The attenuation-clamp network
several Ohms. For example, if the CDM current under consists of D3, D4, and R1. NFET snap-back devices
spec conditions is 5A and the 3.3V MOSFETs are can replace the diodes if the trigger voltage is below
used to transmit signals from one block to another the gate oxide rupture voltage. The voltage at the
then, for 65 Å of gate oxide, the maximum IR voltage logic gate input with respect to the power rails when
drop of either ESD bus is about 36V. Thus, the either diode is forward biased is given by
resistance of the ESD buses can be as high as 36V/5A
or 6.6Ω. If low voltage transistors are used to transmit Rd Rin R
V gs = Vin + VoffD ≈ d Vin + VoffD (7)
and receive the block-to-block signals of Fig. 7 and Rd + Rin Rd + Rin Rin
assuming that LV transistors have an oxide thickness
of 20 Å then the breakdown voltage would be about where Vgs is the gate to source voltage of either the
10V for a CDM pulse. This translates to a maximum input gate NFET or PFET, depending on input voltage
point-to-point resistance of 2Ω for each of the two polarity, Rd is the diode conduction resistance, Vin is
ESD buses. The down side to using 3.3V for the Vesd the input voltage, and VoffsetD is diode offset voltage. If
buses is the need to stack diodes between VddXn and Rin >> Rd then the second term of Eq. 7 becomes
VddESD where VddXn is a circuit block supply valid. For a diode in an advanced process with a
voltage equal to the core voltage. For example, if 0.38µm stripe width and a single row of contacts in
VddXn has a worst-case low voltage of 1.1V and the middle of the stripe the following characteristics
VddESD has a worst case high of 3.6V then a apply:
minimum stack of 5 diodes back-to-back would be Rd = 30 / Ld (8) and C d 0 = 0.17 + 0.91Ld (9)
required for the 2.5V drop. The number of diodes in a
stack becomes less of a problem in the future as the where Ld is the diode stripe length in µm, and Cd0 is
I/O voltage drops faster than the core power supply the 0V junction capacitance in fF. The parameters of
voltage. Also, it may be more advantageous to omit the above equation were based on the P+/N well diode
the VddXn and VddESD back-to-back diodes such as since it has more capacitance than N+/P sub diode.
Dbb1 and instead create a path from VddXn to Thus, for a P+/N well diode with a 3µm long P+
VddESD using a power bus clamp consisting of 3 stripe the “on” resistance is 10Ω and the load
stacked diodes such as DS, Vss back-to-back diodes capacitance 2.9fF. A 10 to 1 attenuation can be easily
such as Dbb2, and a reverse bus diode such as DVdd. achieved for inputs above or below the power rails
This means that, for this case, there are 5 diode drops
using a 100Ω input poly resistor for Rin and a 3 µm
from VddA1 to VddESD or 5.5V before significant
long stripe for D3 or D4 of Fig. 9. Therefore, for a
conduction takes place. This large offset voltage will
practical attenuator the signal RC time constant for
require that all interface gate transistors on both sides
normal signal inputs is on the order of pico-seconds.
of the domain boundary use high voltage transistors
or, perhaps, cascoded low voltage transistors. A VddA1 VddA2
BigFET clamp in place of DS would have a dynamic
offset voltage of about 1V and, therefore, it would be
Rin D4 Bus
more desirable than the 3 series diode clamp in spite
of its increased area. For the BigFET clamp scenario, Clamp
D3
therefore, the VddA1 to VddESD conduction offset
voltage would be about 3.2V. VssA1 VssA2
Fig. 9. Cross-domain interface using a resistor-diode clamp.

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It was found that, especially for HBM, the voltage Fig. 11 is a plot of the TLP “failure” voltage versus
tolerance of a poly resistor-diode clamp is determined the poly length for several different sizes of salicide
by the failure point of the resistor and not by the oxide blocked P+ poly resistors including L/W ratios of
breakdown voltage or diode failure current for 1.5µm/25µm, 4/25, 10/25, 30/25, 10/10, and 10/3.
practical values of Rin and clamp diode sizes. The failure point was defined as the snap-back trigger
voltage since the resistor characteristics are altered
Fig. 10 shows a salicide blocked P+ polysilicon after snap-back. The failure voltage is essentially
resistor TLP plot of current versus voltage and current independent of resistor width whereas the failure
versus Rdc/Rdc0 were Rdc is the DC resistance current is essentially independent of length.
measured between TLP pulses and Rdc0 is the initial
DC resistance. The nominal resistivity of the poly 90
resistor is 360Ω/square. As in [5] the TLP plot of poly 80 Vfail = 2.592Lpoly + 2.1069
resistor has a linear region followed by a region in 70
which the current decreases relative to the initial
60
linear curve, which is then followed by a snap-back

VfailTLP
curve. After snap-back, the voltage almost stabilizes 50
to a constant value before the resistor opens. The 40
increase in resistance prior to snap-back is due to 30
mobility reduction related to heating and the snap- 20
back is due to second-breakdown or the point where
10
the intrinsic carrier concentration becomes significant
relative to the background doping concentration [6]. 0
Note that the DC resistance ratio, Rdc/Rdc0, remains 0 5 10 15 20 25 30
constant at 1 until just before “Vtrigger” of the snap- Lpoly (um)
back curve. A slight rise in the ratio is seen just before
snap-back and then the ratio collapses to values in the Fig. 11. Plot of VfailTLP Vs. Vpoly for various sizes of P+ poly
range of 0.49 to 0.65 after snap-back. This substantial resistors.
reduction in the resistance of the poly resistor could to
be due to the poly melting and then re-crystallizing To convert from VfailTLP to the corresponding HBM
resulting in an increase in mobility or an increase in failure voltage the factor found in [5] will be used.
the activation of the doping or the migration of the According to [5], the conversion factor in going from
contact and metal material into silicon or any a 100ns TLP failure current to the tester HBM voltage
combination of the above. Finally, the resistor opens is 2kV HBM/A TLP. Since the failure voltage of the
at a high enough current. resistor of [5] was low, the HBM tester is essentially a
Rdc/Rdc0
current source. A poly resistor model, which will be
0.40 0.60 0.80 1.00
discussed later, shows that for a 10ns rise time the
500
poly resistor undergoes little heating at the peak
voltage for the HBM stress that ultimately causes
400 snap-back, and, therefore, the resistance at the peak
Imeas
voltage of an HBM waveform is essentially the same
300 as the initial value. Thus, for an HBM waveform
Itlp (mA)

Rdc/Rdc0
200 VHBM / TLP I failTLP R0
V failHBM ( Poly ) = = 1.333I failTLP R0 (10)
100 1.5

0 where VfailHBM(Poly) is the peak HBM voltage causing

0 5 10 15 20 25 30 failure that appears across the poly resistor, VHBM/TLP is
Vtlp (V) the HBM tester failure voltage to TLP failure current
conversion factor, which is equal to 2kV HBM/A
Fig. 10. TLP I-V and I-Rdc/Rdc0 Plot of 10µm x 10µm P+ poly TLP, R0 is the resistance of the poly resistor, and the
resistor.
1.5 factor is the HBM source resistance in kΩ.

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Fig. 12 is a plot of the product of the initial TLP another one multiplies 7.4mA/µm by 360 / ρ . Thus,
resistance and the TLP failure current versus failure for 75Ω/square poly the snap-back linear current
voltage. Based on the equations appearing in Figs. 11
density would be 16.2mA/µm, a number in the ball
and 12 and Eq. 10 then
park of the 13mA/µm reported in [5].
V failHBM = 3.23L poly + 3.14 (11) A model of the resistor was made to demonstrate that
second breakdown is responsible for the snap-back
where VfailHBM is the peak HBM waveform voltage characteristic of the poly resistor. The model accounts
causing failure that appears across the resistor. The not only for heating in the poly but also heat escaping
large offset voltage of Eq. 11 is believed to be due to into the SiO2 boundary layers and, finally, heat going
the end regions of the resistor where the contacts can from the field oxide into the bulk silicon. The upper
remove heat. In fact, the snap-back swing becomes or inter-level oxide thickness was made large enough
smaller as L becomes smaller and the post snap-back so that the temperature at the top boundary of the
current larger before the resistor opens thus oxide remained very close to room temperature. Also,
suggesting a series resistor with reduced temperature the bulk silicon layer was made thick enough so that
effects. Therefore, based on Eq. 11 a 5µm long the temperature at the lower silicon boundary
resistor will snap-back at a peak HBM waveform remained close to room temperature. Heating in the
voltage of 19.3V. Since electrical heating is poly was assumed to be uniform and that the heavily
proportional to V2/R for a voltage source, then Eq. 11 doped poly behaves like bulk silicon with respect to
can be modified to include resistivities other than thermal parameters, mobility, bandgap, etc. Also, the
360Ω/square by multiplying the equation by ρ / 360 . temperature coefficients of both silicon and oxide, and
the poly electrical conduction parameters were
assumed to be functions of temperature and not
constants. The source impedance was set to 50Ω, the
value of the TLP.
80
IfailRo = 0.9342Vfail + 0.3834
The poly power equations for electrical heat
70
generation and heat absorption are therefore
60
L I2
Ifail x Ro (V)

50
Pelectrical = (12)
40 qt polyW (µ n (T ) n + µ p (T ) p )
30
20 ⎛ ∂T poly ⎛ ∂ 2Tox1 ∂ 2Tox 2 ⎞ ⎞
Pheat = WL⎜ C p (T ) gt poly + ⎜⎜ K ox1 + K ⎟⎟
⎜ ∂t ox2 2 ⎟⎠ ⎟⎠
ox 2
10 ⎝ ∂t ⎝ ∂t ox2 1
0
0 10 20 30 40 50 60 70 80 90 (13)
Vfail
Pelectrical = electrically generated heat power, Pheat =
power absorbed by heating poly plus power lost to
Fig. 12. Plot of Ifail x Ro product Vs. Vfail for the resistors of
Fig. 11.
upper and lower oxide of the poly due to oxide heat
conduction, Cp(T) = specific heat of silicon (J/g°C), W
Failure or snap-back “trigger” current versus poly = width of the poly, L = length of the poly, I = current
width was also plotted for the aforementioned resistor flowing through poly, µn and µp = carrier mobilities, n
sizes and it was found that the points closely lie along and p = carrier densities, g = density of Si =
a linear curve with a slope of 7.4mA/µm. The snap- 2.33g/cm3, tpoly = thickness of poly, Kox = thermal
back linear current density reported in [5] is conductivity of SiO2, Tpoly = temperature of the poly,
13mA/µm for a 75Ω/square poly resistor. To a first and Tox = temperature of the oxide.
order approximation, the electrical heating is
proportional to I2R so that to convert the snap-back The standard heat flow differential equation was used
linear current density from one poly resistivity to for the oxide and bulk silicon regions. Since no
literature could be found related to the high

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temperature behavior of oxide heat capacity and heat different, adjacent power domains near each other
conductivity the high temperature equations for fused with a locally placed back-to-back diode clamp
quartz [7] were used which yield values of heat between power buses of the domains, locating power
parameters very close to that of SiO2 at room bus clamps near the logic, and not permitting signals
temperature. Mobility as a function of doping came external to a domain from propagating into a circuit
from [8] and the intrinsic concentration and bandgap block without buffering can reduce oxide stress
energy as a function of temperature came from [9]. during an ESD event. For non-adjacent domains
Finally, poly thickness, field oxide thickness, etc. distributing logic gates in a signal path can greatly
came from the nominal thicknesses specified by the reduce oxide stress. An inter-domain architecture is
foundry. proposed that has excellent noise isolation and low
oxide stress. This architecture can also make use of
Fig. 13 shows a plot of the simulated and measured high voltage transistors to reduce internal ESD
TLP I-V curves. The simulated curve shows a slightly susceptibility. Finally, resistor-clamp networks are
lower snap-back “trigger” voltage and more gradual examined in which it was determined that the voltage
or rounded snap-over. For the simulated post snap- limit for HBM is controlled by the poly resistor and
back region the “holding voltage” is slightly higher not the oxide breakdown voltage for easily achieved
relative to the measured curve. The simulation also high attenuation factors. Design equations for the poly
shows a polysilicon temperature above the melting resistor failure or snap-back point are given based on
point of silicon at the “holding current”, thus empirical data and simulated data for HBM and
confirming that the silicon is in the liquid state after simulated data for CDM.
snap-back. A simulation of the 10µm long poly
resistor using an HBM waveform and a source References
resistance of 10Ω yielded a snap-back “trigger”
voltage of 37.0V, which is close to the value, 35.4V, [1] Lee, et al., IEEE Trans. Computer-Aided Design
predicted by Eq. 11. Finally, a simulation of a 1ns Int. Cir. and Systems, Vol. 22, No. 1, pp. 67-81, 2003.
pulse roughly corresponding to a CDM pulse yielded [2] Lee et al., EOS/ESD Symp. Proceedings, pp. 456-
a “failure” length coefficient of 12.7V/µm. 464, 2000.
[3] Wu et al, EOS/ESD Symp. Proceedings, pp. 287-
500 295, 2000.
[4] Shi et al., IEEE Trans. Elec. Dev., pp. 2355-2360,
Imeas
400 1998.
Isim
[5] Smedes and Li, EOS/ESD Symp. Proceedings, pp.
300
108-115, 2003.
[6] E. Worley, “Unexpected effect in the conduction
I (mA)

characteristic of P+SOI resistors when exposed to

200
ESD”, SOS/SOI Technology Conference, pp.50–51,
1989.
100 [7] D. Buttsworth, “A Finite Difference Routine for
the Solution of Transient One dimensional Heat
0 Conduction Problems with Curvature and Varying
0 5 10 15 20 25 30 Thermal Properties”,
V www.usq.edu.au/engineering/techrep/2001/tr-2001-
01.pdf, p. 18, 2001.
Fig. 13. Plot of measured and simulated TLP I-V of 10x10 poly [8] Reggiani et. al., “Electron and Hole Mobility in
resistor. Silicon at large Operating Temperatures—Part I: Bulk
Mobility”, IEEE Trans. Elec. Dev., pp.490-499, 2002.
[9] Robert Pierret, Semiconductor Device
V. Summary Fundamentals, Addison-Westley Publishing Co., pp.
55-70, 1996.
It has been shown that ultra thin oxides can make
logic gates at independent power domain interfaces
highly susceptible to both CDM and HBM failures.
Locating transmitting and receiving interface logic of

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